soc/intel/xeon_sp: Refactor IOAT compiler optimization outs
IOAT logics are optimized out for non-IOAT platforms where CONFIG(HAVE_IOAT_DOMAINS) as false. This patch puts CONFIG(HAVE_IOAT_DOMAINS) check together ahead of is_ioat_iio_stack_res() check in the corresponding if statement to fulfill the optimization outs. TEST=intel/archercity CRB Change-Id: I2d16c6ff5320bc9195a1033b6d55e3d997b19b88 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80683 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -25,14 +25,7 @@ struct iiostack_resource {
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void get_iiostack_info(struct iiostack_resource *info);
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bool is_pcie_iio_stack_res(const STACK_RES *res);
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bool is_ubox_stack_res(const STACK_RES *res);
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#if CONFIG(HAVE_IOAT_DOMAINS)
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bool is_ioat_iio_stack_res(const STACK_RES *res);
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#else
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static inline bool is_ioat_iio_stack_res(const STACK_RES *res)
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{
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return false;
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}
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#endif
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void bios_done_msr(void *unused);
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#endif
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@ -336,7 +336,7 @@ static unsigned long acpi_create_drhd(unsigned long current, int socket,
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}
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// Add IOAT End Points (with memory resources. We don't report every End Point device.)
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if (is_ioat_iio_stack_res(ri)) {
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if (CONFIG(HAVE_IOAT_DOMAINS) && is_ioat_iio_stack_res(ri)) {
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for (int b = ri->BusBase; b <= ri->BusLimit; ++b) {
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struct device *dev = pcidev_path_on_bus(b, PCI_DEVFN(0, 0));
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while (dev) {
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@ -520,7 +520,7 @@ static unsigned long acpi_create_satc(unsigned long current, const IIO_UDS *hob)
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for (int stack = (MAX_LOGIC_IIO_STACK - 1); stack >= 0; --stack) {
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const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack];
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// Add the IOAT ATS devices to the SATC
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if (is_ioat_iio_stack_res(ri))
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if (CONFIG(HAVE_IOAT_DOMAINS) && is_ioat_iio_stack_res(ri))
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current = xeonsp_create_satc_ioat(current, ri);
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}
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}
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