soc/intel/mtl: Fixed TBT PCIe devtree remapping

The TBT PCIe devicetree settings are not remapped properly when
TBT PCIe port 0 is disabled.
This code refer SHA:58bc5d937 to remap the PCIe devtree settings
properly in case of TBT PCIe port0 is disabled,

TEST=Tested on screebo and found "Remapping PCIe Root Port #2 msg"
     showed up in coreboot log

Change-Id: I7c7549ddf8ccdd67d7af7c69f51a84614cff9a03
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81841
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kane Chen
2024-04-12 21:16:15 +08:00
committed by Felix Held
parent 8bcd8210ea
commit 8c927c4dbf
3 changed files with 20 additions and 0 deletions

View File

@@ -185,6 +185,9 @@ void soc_init_pre_device(void *chip_info)
/* Swap enabled PCI ports in device tree if needed. */
pcie_rp_update_devicetree(get_pcie_rp_table());
/* Swap enabled TBT root ports in device tree if needed. */
pcie_rp_update_devicetree(get_tbt_pcie_rp_table());
/*
* Earlier when coreboot used to send EOP at late as possible caused
* issue of delayed response from CSE since CSE was busy loading payload.

View File

@@ -6,5 +6,6 @@
#include <intelblocks/pcie_rp.h>
const struct pcie_rp_group *get_pcie_rp_table(void);
const struct pcie_rp_group *get_tbt_pcie_rp_table(void);
#endif /* __SOC_METEORLAKE_PCIE_H__ */

View File

@@ -5,6 +5,17 @@
#include <soc/pcie.h>
#include <soc/soc_info.h>
/*
* TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe
* root ports index starts from 1). Thus keeping lcap_port_base 0x10 for TBT, so that coreboot's
* PCIe remapping logic can return correct index (0-based)
*/
static const struct pcie_rp_group tbt_rp_groups[] = {
{ .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 0x10 },
{ 0 }
};
static const struct pcie_rp_group mtlp_rp_groups[] = {
{ .slot = PCI_DEV_SLOT_PCIE_1, .start = 0, .count = 8, .lcap_port_base = 1 },
{ .slot = PCI_DEV_SLOT_PCIE_2, .start = 0, .count = 3, .lcap_port_base = 1 },
@@ -17,6 +28,11 @@ const struct pcie_rp_group *get_pcie_rp_table(void)
return mtlp_rp_groups;
}
const struct pcie_rp_group *get_tbt_pcie_rp_table(void)
{
return tbt_rp_groups;
}
enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev)
{
return PCIE_RP_PCH;