soc/intel/mtl: Fixed TBT PCIe devtree remapping
The TBT PCIe devicetree settings are not remapped properly when TBT PCIe port 0 is disabled. This code refer SHA:58bc5d937 to remap the PCIe devtree settings properly in case of TBT PCIe port0 is disabled, TEST=Tested on screebo and found "Remapping PCIe Root Port #2 msg" showed up in coreboot log Change-Id: I7c7549ddf8ccdd67d7af7c69f51a84614cff9a03 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81841 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@@ -185,6 +185,9 @@ void soc_init_pre_device(void *chip_info)
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/* Swap enabled PCI ports in device tree if needed. */
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pcie_rp_update_devicetree(get_pcie_rp_table());
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/* Swap enabled TBT root ports in device tree if needed. */
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pcie_rp_update_devicetree(get_tbt_pcie_rp_table());
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/*
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* Earlier when coreboot used to send EOP at late as possible caused
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* issue of delayed response from CSE since CSE was busy loading payload.
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@@ -6,5 +6,6 @@
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#include <intelblocks/pcie_rp.h>
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const struct pcie_rp_group *get_pcie_rp_table(void);
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const struct pcie_rp_group *get_tbt_pcie_rp_table(void);
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#endif /* __SOC_METEORLAKE_PCIE_H__ */
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@@ -5,6 +5,17 @@
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#include <soc/pcie.h>
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#include <soc/soc_info.h>
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/*
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* TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe
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* root ports index starts from 1). Thus keeping lcap_port_base 0x10 for TBT, so that coreboot's
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* PCIe remapping logic can return correct index (0-based)
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*/
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static const struct pcie_rp_group tbt_rp_groups[] = {
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{ .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 0x10 },
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{ 0 }
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};
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static const struct pcie_rp_group mtlp_rp_groups[] = {
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{ .slot = PCI_DEV_SLOT_PCIE_1, .start = 0, .count = 8, .lcap_port_base = 1 },
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{ .slot = PCI_DEV_SLOT_PCIE_2, .start = 0, .count = 3, .lcap_port_base = 1 },
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@@ -17,6 +28,11 @@ const struct pcie_rp_group *get_pcie_rp_table(void)
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return mtlp_rp_groups;
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}
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const struct pcie_rp_group *get_tbt_pcie_rp_table(void)
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{
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return tbt_rp_groups;
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}
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enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev)
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{
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return PCIE_RP_PCH;
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