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dram/ddr3: Use the same naming convention as DDR4

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Change-Id: Ifaff19c0117b5247d3321605ccc2e97bf8226ca8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82216
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes Haouas
2024-05-06 11:48:41 +02:00
parent 0f45e17f56
commit 8bcd8210ea
7 changed files with 39 additions and 39 deletions
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2
src/device/dram/ddr3.c
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@@ -365,7 +365,7 @@ int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd)
memcpy(dimm->part_number, &spd[128], 16);
printram(" Part number : %s\n", dimm->part_number);
memcpy(dimm->serial, &spd[SPD_DIMM_SERIAL_NUM], SPD_DIMM_SERIAL_LEN);
memcpy(dimm->serial, &spd[SPD_DDR3_SERIAL_NUM], SPD_DDR3_SERIAL_LEN);
return ret;
}

14
src/include/device/dram/ddr3.h
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@@ -27,12 +27,12 @@
*
* @{
*/
#define SPD_DIMM_MOD_ID1 117
#define SPD_DIMM_MOD_ID2 118
#define SPD_DIMM_SERIAL_NUM 122
#define SPD_DIMM_SERIAL_LEN 4
#define SPD_DIMM_PART_NUM 128
#define SPD_DIMM_PART_LEN 18
#define SPD_DDR3_MOD_ID1 117
#define SPD_DDR3_MOD_ID2 118
#define SPD_DDR3_SERIAL_NUM 122
#define SPD_DDR3_SERIAL_LEN 4
#define SPD_DDR3_PART_NUM 128
#define SPD_DDR3_PART_LEN 18
/** @} */
/* Byte 3 [3:0]: DDR3 Module type information */
@@ -145,7 +145,7 @@ struct dimm_attr_ddr3_st {
/* ASCII part number - NULL terminated */
u8 part_number[17];
/* Serial number */
u8 serial[SPD_DIMM_SERIAL_LEN];
u8 serial[SPD_DDR3_SERIAL_LEN];
};
enum ddr3_xmp_profile {

12
src/northbridge/intel/gm45/raminit_meminfo.c
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@@ -24,14 +24,14 @@ static u8 get_dimm_mod_type(const sysinfo_t *sysinfo, const int idx)
static void ddr3_read_ids(const sysinfo_t *sysinfo, struct dimm_info *dimm, const int idx)
{
const u8 addr = sysinfo->spd_map[idx];
for (int k = 0; k < SPD_DIMM_SERIAL_LEN; k++) {
dimm->serial[k] = smbus_read_byte(addr, SPD_DIMM_SERIAL_NUM + k);
for (int k = 0; k < SPD_DDR3_SERIAL_LEN; k++) {
dimm->serial[k] = smbus_read_byte(addr, SPD_DDR3_SERIAL_NUM + k);
}
for (int k = 0; k < SPD_DIMM_PART_LEN; k++) {
dimm->module_part_number[k] = smbus_read_byte(addr, SPD_DIMM_PART_NUM + k);
for (int k = 0; k < SPD_DDR3_PART_LEN; k++) {
dimm->module_part_number[k] = smbus_read_byte(addr, SPD_DDR3_PART_NUM + k);
}
dimm->mod_id = (smbus_read_byte(addr, SPD_DIMM_MOD_ID2) << 8) |
(smbus_read_byte(addr, SPD_DIMM_MOD_ID1) << 0);
dimm->mod_id = (smbus_read_byte(addr, SPD_DDR3_MOD_ID2) << 8) |
(smbus_read_byte(addr, SPD_DDR3_MOD_ID1) << 0);
}
static u32 get_mem_clock_mt(const int clock_index)

12
src/northbridge/intel/haswell/broadwell_mrc/raminit.c
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@@ -219,14 +219,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
dimm->dimm_num = slot;
dimm->bank_locator = ch * 2;
memcpy(dimm->serial,
&pei_data->spd_data[ch][slot][SPD_DIMM_SERIAL_NUM],
SPD_DIMM_SERIAL_LEN);
&pei_data->spd_data[ch][slot][SPD_DDR3_SERIAL_NUM],
SPD_DDR3_SERIAL_LEN);
memcpy(dimm->module_part_number,
&pei_data->spd_data[ch][slot][SPD_DIMM_PART_NUM],
SPD_DIMM_PART_LEN);
&pei_data->spd_data[ch][slot][SPD_DDR3_PART_NUM],
SPD_DDR3_PART_LEN);
dimm->mod_id =
(pei_data->spd_data[ch][slot][SPD_DIMM_MOD_ID2] << 8) |
(pei_data->spd_data[ch][slot][SPD_DIMM_MOD_ID1] & 0xff);
(pei_data->spd_data[ch][slot][SPD_DDR3_MOD_ID2] << 8) |
(pei_data->spd_data[ch][slot][SPD_DDR3_MOD_ID1] & 0xff);
dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
dimm->bus_width = MEMORY_BUS_WIDTH_64;
dimm_cnt++;

12
src/northbridge/intel/haswell/haswell_mrc/raminit.c
View File

@@ -252,14 +252,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
dimm->dimm_num = d_num;
dimm->bank_locator = ch * 2;
memcpy(dimm->serial,
&pei_data->spd_data[index][SPD_DIMM_SERIAL_NUM],
SPD_DIMM_SERIAL_LEN);
&pei_data->spd_data[index][SPD_DDR3_SERIAL_NUM],
SPD_DDR3_SERIAL_LEN);
memcpy(dimm->module_part_number,
&pei_data->spd_data[index][SPD_DIMM_PART_NUM],
SPD_DIMM_PART_LEN);
&pei_data->spd_data[index][SPD_DDR3_PART_NUM],
SPD_DDR3_PART_LEN);
dimm->mod_id =
(pei_data->spd_data[index][SPD_DIMM_MOD_ID2] << 8) |
(pei_data->spd_data[index][SPD_DIMM_MOD_ID1] & 0xff);
(pei_data->spd_data[index][SPD_DDR3_MOD_ID2] << 8) |
(pei_data->spd_data[index][SPD_DDR3_MOD_ID1] & 0xff);
dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
dimm->bus_width = MEMORY_BUS_WIDTH_64;
dimm_cnt++;

2
src/northbridge/intel/sandybridge/raminit.c
View File

@@ -142,7 +142,7 @@ static void read_spd(spd_ddr3_raw_data *spd, u8 addr, bool id_only)
{
int j;
if (id_only) {
for (j = SPD_DIMM_MOD_ID1; j < 128; j++)
for (j = SPD_DDR3_MOD_ID1; j < 128; j++)
(*spd)[j] = smbus_read_byte(addr, j);
} else {
for (j = 0; j < SPD_SIZE_MAX_DDR3; j++)

24
src/northbridge/intel/sandybridge/raminit_mrc.c
View File

@@ -467,14 +467,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
dimm->dimm_num = 0;
dimm->bank_locator = i * 2;
memcpy(dimm->serial, /* bytes 122-125 */
&pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM],
sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN);
&pei_data->spd_data[0][SPD_DDR3_SERIAL_NUM],
sizeof(uint8_t) * SPD_DDR3_SERIAL_LEN);
memcpy(dimm->module_part_number, /* bytes 128-145 */
&pei_data->spd_data[0][SPD_DIMM_PART_NUM],
sizeof(uint8_t) * SPD_DIMM_PART_LEN);
&pei_data->spd_data[0][SPD_DDR3_PART_NUM],
sizeof(uint8_t) * SPD_DDR3_PART_LEN);
dimm->mod_id = /* bytes 117/118 */
(pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) |
(pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF);
(pei_data->spd_data[0][SPD_DDR3_MOD_ID2] << 8) |
(pei_data->spd_data[0][SPD_DDR3_MOD_ID1] & 0xFF);
dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
dimm->bus_width = MEMORY_BUS_WIDTH_64;
dimm_cnt++;
@@ -491,14 +491,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
dimm->dimm_num = 1;
dimm->bank_locator = i * 2;
memcpy(dimm->serial, /* bytes 122-125 */
&pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM],
sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN);
&pei_data->spd_data[0][SPD_DDR3_SERIAL_NUM],
sizeof(uint8_t) * SPD_DDR3_SERIAL_LEN);
memcpy(dimm->module_part_number, /* bytes 128-145 */
&pei_data->spd_data[0][SPD_DIMM_PART_NUM],
sizeof(uint8_t) * SPD_DIMM_PART_LEN);
&pei_data->spd_data[0][SPD_DDR3_PART_NUM],
sizeof(uint8_t) * SPD_DDR3_PART_LEN);
dimm->mod_id = /* bytes 117/118 */
(pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) |
(pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF);
(pei_data->spd_data[0][SPD_DDR3_MOD_ID2] << 8) |
(pei_data->spd_data[0][SPD_DDR3_MOD_ID1] & 0xFF);
dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
dimm->bus_width = MEMORY_BUS_WIDTH_64;
dimm_cnt++;