mb/system76: Enable S0ix support but prefer S3

Enable S0ix support but continue using S3 by default as it is not
tested on most boards. TGL-U boards continue to only use S0ix as S3 is
not supported on them.

Change-Id: Idc881d30009e3ef170e5430596652548aa434fda
Signed-off-by: Tim Crawford <tcrawford@system76.com>

.clang-format

@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0-only
+# SPDX-License-Identifier: GPL-2.0
 #
 # clang-format configuration file. Intended for clang-format >= 16.
 #

.gitignore

@@ -9,7 +9,6 @@ defconfig
 build/
 coreboot-builds/
 coreboot-builds*/
-generated/
 
 site-local
 

.gitreview

@@ -2,4 +2,4 @@
 host=review.coreboot.org
 port=29418
 project=coreboot
-defaultbranch=main
+defaultbranch=master

Documentation/contributing/coding_style.md

@@ -808,7 +808,7 @@ eDP display panel encounters an I2C error, it should print a "cannot read EDID"
 message and return an error code. The calling display initialization function
 knows that without the EDID there is no way to initialize the display correctly,
 so it will also immediately return with an error code without running its
-remaining code that would initialize the SoC's display controller. Execution
+remaining code that would initialize the SoC's display controller. Exeuction
 returns further up the function stack to the mainboard initialization code
 which continues booting despite the failed display initialization, since
 display functionality is non-essential to the system. (Code is encouraged but

Documentation/distributions.md

@@ -43,16 +43,6 @@ ships with coreboot and support upstream maintenance for the devices through a
 third party, [3mdeb](https://3mdeb.com). They provide current and tested
 firmware binaries on [GitHub](https://pcengines.github.io).
 
-### Protectli
-
-[Protectli](https://protectli.com) is dedicated to providing reliable,
-cost-effective, and secure computer equipment with coreboot-based firmware
-tailored for their hardware. It comes with the [Dasharo](#dasharo)
-firmware, maintained by [3mdeb](https://3mdeb.com/). Protectli hardware has
-verified support for many popular operating systems, such as Linux distributions,
-FreeBSD, and Windows. Support includes Debian, Ubuntu, OPNsense, pfSense,
-ProxMox VE, VMware ESXi, Windows 10 and 11, and many more.
-
 ### Purism
 
 [Purism](https://www.puri.sm) sells laptops with a focus on user privacy and

Documentation/getting_started/build_system.md

@@ -7,10 +7,10 @@ to the point of providing its own custom language.
 The overhead of learning this new syntax is (hopefully) offset by its lower
 complexity.
 
-The build system is defined in the toplevel `Makefile` and `toolchain.mk`
+The build system is defined in the toplevel `Makefile` and `toolchain.inc`
 and is supposed to be generic (and is in fact used with a number of other
 projects).  Project specific configuration should reside in files called
-`Makefile.mk`.
+`Makefile.inc`.
 
 In general, the build system provides a number of "classes" that describe
 various parts of the build. These cover the various build targets in coreboot
@@ -36,7 +36,7 @@ TODO: explain how to create new classes and how to evaluate them.
 ### subdirs
 `subdirs` contains subdirectories (relative to the current directory) that
 should also be handled by the build system. The build system expects these
-directories to contain a file called `Makefile.mk`.
+directories to contain a file called `Makefile.inc`.
 
 Subdirectories are not read at the point where the `subdirs` statement
 resides but later, after the current directory is handled (and potentially
@@ -66,7 +66,7 @@ supported options are:
 
 You can use the `add_intermediate` helper to add new post-processing steps for
 the final `coreboot.rom` image. For example you can add new files to CBFS by
-adding something like this to `site-local/Makefile.mk`
+adding something like this to `site-local/Makefile.inc`
 
 ```
 $(call add_intermediate, add_mrc_data)
@@ -100,4 +100,4 @@ The default implementation just returns `COREBOOT` (the default region) for
 all files.
 
 vboot provides its own implementation of `regions-for-file` that can be used
-as reference in `src/vboot/Makefile.mk`.
+as reference in `src/vboot/Makefile.inc`.

Documentation/getting_started/faq.md

@@ -1,312 +0,0 @@
-# coreboot FAQ
-
-## General coreboot questions
-
-
-### What is coreboot?
-
-coreboot is a free and open software project designed to initialize
-computers and embedded systems in a fast, secure, and auditable fashion.
-The focus is on minimal hardware initialization: to do only what is
-absolutely needed, then pass control to other software (a payload, in
-coreboot parlance) in order to boot the operating system securely.
-
-
-### What is a coreboot payload?
-
-coreboot itself does not deal with boot media such as hard-drives,
-SSDs, or USB flash-drives, beyond initializing the underlying hardware.
-So in order to actually boot an operating system, another piece of
-software which does do those things must be used. coreboot supports
-a large number of diverse payloads; see below for more details.
-
-
-### Is coreboot the same as UEFI?
-
-No. coreboot and UEFI are both system firmware that handle the
-initialization of the hardware, but are otherwise not similar.
-coreboot’s goal is to **just** initialize the hardware and exit.
-This makes coreboot smaller and simpler, leading to faster boot times,
-and making it easier to find and fix bugs. The result is a higher
-overall security.
-
-
-### What's the difference between coreboot and UEFI?
-
-UEFI is actually a firmware specification, not a specific software
-implementation. Intel, along with the rest of the Tianocore project,
-has released an open-source implementation of the overall framework,
-EDK2, but it does not come with hardware support. Most hardware running
-UEFI uses a proprietary implementation built on top of EDK2.
-
-coreboot does not implement the UEFI specification, but it can be used to
-initialize the system, then launch a UEFI payload such as EDK2 in order
-to provide UEFI boot services.
-
-The UEFI specification also defines and allows for many things that are
-outside of coreboot’s scope, including (but not limited to):
-
-* Boot device selection
-* Updating the firmware
-* A CLI shell
-* Network communication
-* An integrated setup menu
-
-
-### Can coreboot boot operating systems that require UEFI?
-
-Yes, but... again, coreboot **just** initializes the hardware. coreboot
-itself doesn’t load operating systems from storage media other than the
-flash chip. Unlike UEFI, coreboot does not, and will not contain a Wi-Fi
-driver or communicate directly with any sort of network. That sort of
-functionality is not related to hardware initialization.
-
-To boot operating systems that require UEFI, coreboot can be compiled with
-EDK2 as the payload. This allows coreboot to perform the hardware init,
-with EDK2 supplying the UEFI boot interface and runtime services to
-the operating system.
-
-
-### What non-UEFI payloads does coreboot support?
-
-* SeaBIOS, behaves like a classic BIOS, allowing you to boot operating
-  systems that rely on the legacy interrupts.
-
-* GRUB can be used as a coreboot payload, and is currently the most
-  common approach to full disk encryption (FDE).
-
-* A Linux kernel and initramfs stored alongside coreboot in the boot
-  ROM can also be used as a payload. In this scenario coreboot
-  initializes hardware, loads Linux from boot ROM into RAM, and
-  executes it. The embedded Linux environment can look for a target OS
-  kernel to load from local storage or over a network and execute it
-  using kexec. This is sometimes called LinuxBoot.
-
-* U-boot, depthcharge, FILO, etc.
-
-There’s [https://doc.coreboot.org/payloads.html](https://doc.coreboot.org/payloads.
-html) with a list, although it’s not complete.
-
-
-### What does coreboot leave in memory after it's done initializing the hardware?
-
-While coreboot tries to remove itself completely from memory after
-finishing, some tables and data need to remain for the OS. coreboot
-reserves an area in memory known as CBMEM, to save this data after it
-has finished booting. This contains things such as the boot log, tables
-that get passed to the payload, SMBIOS, and ACPI tables for the OS.
-
-In addition to CBMEM, on X86 systems, coreboot will typically set up
-SMM, which will remain resident after coreboot exits.
-
-
-## Platforms
-
-### What’s the best coreboot platform for a user?
-
-The choice of the best coreboot platform for a user can vary depending
-on their specific needs, preferences, and use cases.
-
-Typically, people who want a system with a minimum of proprietary
-firmware are restricted to older systems like the Lenovo X220, or more
-expensive, non-x86 solutions like TALOS, from Raptor Engineering.
-
-There are a number of companies selling modern systems, but those all
-require more proprietary binaries in addition to coreboot (e.g., Intel
-FSP). However, unlike the older ThinkPads, many of these newer devices
-use open-source embedded controller (EC) firmware, so there are
-tradeoffs with either option.
-
-The coreboot project mantains a list of companies selling machines
-which use coreboot on the [website](https://coreboot.org/users.html).
-
-
-### What’s the best platform for coreboot development?
-
-Similar to the best platform for users, the best platform for
-developers very much depends on what a developer is trying to do.
-
-* QEMU is generally the easiest platform for coreboot development, just
-  because it’s easy to run anywhere. However, it’s possible for things
-  to work properly in QEMU but fail miserably on actual hardware.
-
-While laptops tend to be harder to develop than desktop platforms, a
-majority of newer platforms on coreboot tend to be laptops. The
-development difficulty is due to a few different factors:
-
-1. The EC (Embedded Controller) is a specialized microcontroller that
-   typically handles keyboard and sometimes mouse input for a laptop.
-   It also controls many power management functions such as fans, USB-C
-   power delivery, etc. ECs run mainboard-specific firmware, which is
-   typically undocumented.
-2. ThinkPads (X230, 30-series, 20-series, T430, T540, T520). Sandy
-   Bridge and Ivy Bridge are well-supported. Some may have
-   difficult-to-reach SPI flash chips. Boards with two flash chips (e.g.
-   30-series ThinkPads) are harder to externally reflash as one needs to
-   make sure the non-targeted flash chip remains disabled at all times.
-   The X230 is notoriously sensitive to external reflashing issues.
-3. Laptops often lack a convenient method to obtain firmware boot logs.
-   One can use EHCI debug on older systems and Chromebook-specific
-   solutions for Chromebooks, but one often has to resort to flashconsole
-   (writing coreboot logs to the flash chip where coreboot resides). On
-   the other hand, several desktop mainboards still have a RS-232 serial
-   port.
-
-Some of the easiest physical systems to use for coreboot development
-are Chromebooks. Newer Chromebooks allow for debug without opening the
-case. Look for SuzyQ Cables or SuzyQables or instructions on how to
-build one. These cables only work on a specific port in a specific
-orientation. Google [supplies
-specifications](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/master/docs/ccd.md#SuzyQ-SuzyQable)
-for these cables.
-
-
-### What platforms does coreboot support?
-
-The most accurate way to determine what systems coreboot supports is by
-browsing the src/mainboard tree or running “make menuconfig” and going
-through the “Mainboard” submenu. You can also search Gerrit to see if
-there are any unmerged ports for your board.
-
-There is also the board status page
-([https://coreboot.org/status/board-status.html](https://coreboot.org/status/board-status.html)),
-however this does not currently show supported board variants.
-
-
-## coreboot Development
-
-### Can coreboot be ported to [this board]?
-
-The best way to determine if coreboot can be ported to a system is to
-see if the processor and chipset is supported. The next step is to see
-whether the system is locked to the proprietary firmware which comes
-with the board.
-
-Intel Platforms:
-
-* coreboot only supports a few northbridges (back when northbridges
-  were on a separate package), and there's next to no support for
-  "server" platforms (multi-socket and similar things). Here's a list
-  of more recent supported Intel processors:
-    * Alder Lake (2021 - Core Gen 12)
-    * Apollo Lake (2016 - Atom)
-    * Baytrail (2014 - Atom)
-    * Braswell (2016 - Atom)
-    * Broadwell (2014 - Core Gen 5)
-    * Comet Lake (2019 - Core Gen 10)
-    * Cannon Lake (2018 - Core Gen 8/9)
-    * Denverton (2017)
-    * Elkhart lake (2021 - Atom)
-    * Haswell (2013 - Core Gen 4)
-    * Ivy Bridge (2012 - Core Gen 3)
-    * Jasper Lake (2021 - Atom)
-    * Kaby Lake (2016 - Core Gen 7/8)
-    * Meteor Lake (2023 - Gen 1 Ultra-mobile)
-    * Sandy Bridge (2011 - Core Gen 2)
-    * Sky Lake (2015 - Core Gen 6)
-    * Tiger Lake (2020 - Core Gen 11)
-    * Whiskey Lake (2018 - Core Gen 8)
-
-* Intel Boot Guard is a security feature which tries to prevent loading
-  unauthorized firmware by the mainboard. If supported by the platform,
-  and the platform is supported by intelmetool, you should check if Boot
-  Guard is enabled. If it is, then getting coreboot to run will be
-  difficult or impossible even if it is ported. You can run
-  `intelmetool -b` on supported platforms to see if Boot Guard is
-  enabled (although it can fail because it wants to probe the ME
-  beforehand).
-
-AMD Ryzen-based platforms:
-
-* The AMD platforms Ryzen-based platforms unfortunately are currently
-  not well supported outside of the Chromebooks (and AMD reference
-  boards) currently in the tree.
-  The responsible teams are trying to fix this, but currently it's
-  **very** difficult to do a new port. Recent supported SoCs:
-    * Stoney Ridge
-    * Picasso
-    * Cezanne
-    * Mendocino
-    * Phoenix
-
-General notes:
-
-* Check the output of `lspci` to determine what processor/chipset
-  family your system has. Processor/chipset support is the most
-  important to determine if a board can be ported.
-* Check the output of `superiotool` to see if it detects the Super I/O
-  on the system. You can also check board schematics and/or boardviews
-  if you can find them, or physically look at the mainboard for a chip
-  from one of the common superio vendors.
-* Check what EC your system has (mostly applicable to laptops, but some
-  desktops have EC-like chips). You will likely need to refer to the
-  actual board or schematics/boardviews for this. Physical observation
-  is the most accurate identification procedure; software detection can
-  then be used to double-check if the chip is correct, but one should
-  not rely on software detection alone to identify an EC.
-
-
-### How do I port coreboot to [this board]?
-
-A critical piece for anyone attempting to do a board port is to make
-sure that you have a method to recover your system from a failed flash.
-
-We need an updated motherboard porting guide, but currently the guide
-on the [wiki](https://www.coreboot.org/Motherboard_Porting_Guide) looks
-to be the best reference.
-
-At the moment, the best answer to this question is to ask for help on
-one of the [various community
-forums](https://doc.coreboot.org/community/forums.html).
-
-
-### What about the Intel ME?
-
-There seems to be a lot of FUD about what the ME can and can’t do.
-coreboot currently does not have a clear recommendation on how to
-handle the ME. We understand that there are serious concerns about the
-ME, and would like to flatly recommend removing as much as possible,
-however modifying the ME can cause serious stability issues.
-
-Additionally, coreboot and the Intel ME are completely separate entites
-which in many cases simply happen to occupy the same flash chip. It is
-not necessary to run coreboot to modify the ME, and running coreboot
-does not imply anything about the ME's operational state.
-
-
-#### A word of caution about the modifying ME
-
-Messing with the ME firmware can cause issues, and this is outside the
-scope of the coreboot project.
-
-If you do decide to modify the ME firmware, please make sure coreboot
-works **before** messing with it. Even if the vendor boot firmware
-works when the ME isn't operating normally, it's possible that coreboot
-doesn't handle it the same way and something breaks. If someone asks
-for help with coreboot and we think the ME state may be a factor, we'll
-ask them to try reproducing the issue with the ME running normally to
-reduce the number of variables involved. This is especially important
-when flashing coreboot for the first time, as it's best for newbies to
-start with small steps: start by flashing coreboot to the BIOS region
-and leaving the remaining regions untouched, then tinker around with
-coreboot options (e.g. other payloads, bootsplash, RAM overclock...),
-or try messing with the ME firmware **without changing coreboot**.
-
-Most people don't understand the implications of messing with the ME
-firmware, especially the use of `me_cleaner`. We admit that we don't
-know everything about the ME, but we try to understand it as much as
-possible. The ME is designed to operate correctly with the HAP (or
-AltMeDisable) bit set, and it will gracefully enter a debug state (not
-normal, but not an error). However, when using `me_cleaner` to remove
-parts of the ME firmware, the ME will often end up in an error state
-because parts of its FW are missing. It is known that removing some of
-these parts ([`EFFS` and `FCRS` on Cougar Point,
-c.f.](https://review.coreboot.org/c/coreboot/+/27798/6/src/mainboard/asus/p8h61-m_lx/Kconfig#63))
-can cause problems. We do not know whether the state the ME ends up in
-after applying `me_cleaner` is as secure as the state the ME goes to
-when only the HAP bit is set: the removed FW modules could contain
-steps to lock down important settings for security reasons.
-
-To sum up, **we do not recommend messing with the ME firmware**. But if
-you have to, please use `ifdtool` to set the HAP bit initially before
-progressing to `me_cleaner` if necessary.

Documentation/getting_started/index.md

@@ -7,4 +7,3 @@
 * [Writing Documentation](writing_documentation.md)
 * [Setting up GPIOs](gpio.md)
 * [Adding devices to a device tree](devicetree.md)
-* [Frequently Asked Questions](faq.md)

Documentation/getting_started/kconfig.md

@@ -963,7 +963,7 @@ variable.  This is not set in coreboot, which uses the default CONFIG_ prefix
 for all of its symbols.
 
 The coreboot makefile forces the config.h file to be included into all coreboot
-C files. This is done in Makefile.mk on the compiler command line using the
+C files. This is done in Makefile.inc on the compiler command line using the
 “-include $(obj)/config.h” command line option.
 
 Example of various symbol types in the config.h file:

Documentation/infrastructure/admin.md

@@ -1,52 +0,0 @@
-# Operating our services
-
-## Mailing list moderation
-
-Our [mailing lists] experience the same barrage of spam mails than any
-other email address. We do have a spam filter in front of it, and
-since the lists require registration, spam ends up in the moderation
-queue. But not only spam ends up there, sometimes users send inquiries
-without registering first. It's a custom of the project to let these
-through, so that such emails can be discussed. This requires manual
-intervention.
-
-This section describes the tasks related to mailing list management.
-
-### Registration
-
-To participate in mailing list moderation, you need to become a list
-moderator or owner. This is up for the existing owners to handle and
-if you want to contribute in that area, it might be best to bring it
-up at the leadership meeting.
-
-After gaining leadership approval, list admins can add you to the
-appropriate group in the [mailing list backend] by selecting the list,
-then User / group-name, and add your email address there.
-
-### Regular tasks
-
-Most of our lists are auto-subscribing, so users can register
-themselves and finish the process by responding to the double-opt-in
-email. Some lists are manually managed though. The [mailing list
-backend] shows the number of open subscription requests for these
-lists on the mailing list's main page.
-
-It also provides a list of held messages, where they can be accepted,
-rejected or dropped. Spam should be dropped, that's clear. Emails with
-huge attachments (e.g. screenshots) should be rejected, which gives
-you an opportunity to explain the reason (in case of large
-attachments, something like "Please re-send without attachments, offer
-the files through some other mechanism please: Our emails are
-distributed to hundreds of readers, and sending the files to everybody
-is inconsiderate of traffic and storage constraints.")
-
-Legit emails (often simple requests of the form "is this or that
-supported") can be accepted, which means they'll be sent out.
-
-If you notice recurring spam sources (e.g. marketers) you can put them
-on the [global ban list] to filter them out across all lists. It takes
-entries in regular expression format.
-
-[mailing lists]: https://mail.coreboot.org/hyperkitty/
-[mailing list backend]: https://mail.coreboot.org/postorius/
-[global ban list]: https://mail.coreboot.org/postorius/bans/

Documentation/infrastructure/index.md

@@ -5,7 +5,7 @@ This section contains documentation about our infrastructure
 ## Services
 
 * [Project services](services.md)
-* [Administrator's handbook](admin.md)
+
 
 ## Jenkins builders and builds
 * [Setting up Jenkins build machines](builders.md)

Documentation/mainboard/ocp/deltalake.md

@@ -222,4 +222,4 @@ and [u-root] as initramfs.
 [All about u-root]: https://github.com/linuxboot/book/tree/master/u-root
 [u-root]: https://u-root.org/
 [ChromeOS VPD]: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md
-[src/mainboard/ocp/deltalake/vpd.h]: https://review.coreboot.org/plugins/gitiles/coreboot/+/HEAD/src/mainboard/ocp/deltalake/vpd.h
+[src/mainboard/ocp/deltalake/vpd.h]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/src/mainboard/ocp/deltalake/vpd.h

Documentation/releases/coreboot-24.02-relnotes.md

@@ -1,17 +1,17 @@
 Upcoming release - coreboot 24.02
 ========================================================================
 
-The 24.02 release is scheduled for February 19, 2024. The next release,
-which will be 24.05, is scheduled for mid-May.
+The 24.02 release is scheduled for Mid February, 2024
 
-The coreboot project is happy to announce our next release for February
-2024. Over the past three months, our contributors have focused on
-refining the coreboot codebase, generally prioritizing cleanup and
-quality enhancements. We extend our gratitude to all the contributors
-who have dedicated their time and expertise. Thank you for your
-invaluable contributions to this vital phase of maintenance and
-optimization.
 
+Update this document with changes that should be in the release notes.
+
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+* Note that all changes before the release are done are marked upcoming.
+  A final version of the notes are done after the release.
 
 ### Release number format update
 
@@ -19,255 +19,72 @@ The previous release was the last to use the incrementing 4.xx release
 name scheme. For this and future releases, coreboot has switched to a
 Year.Month.Sub-version naming scheme. As such, the next release,
 scheduled for May of 2024 will be numbered 24.05, with the sub-version
-of 00 implied. If we need to do a fix or incremental release, we'll
+of 00 implied. If we need to do a fix or incremental release, we’ll
 append the values .01, .02 and so on to the initial release value.
 
 
-### The master branch is being deleted
-
-The coreboot project changed from master to main roughly 6 months ago,
-and has been keeping the two branches in sync since then to ease the
-transition. As of this release, we are getting rid of the master branch
-completely. Please make sure any scripts you're using that reference the
-'master' branch have been switched to 'main'.
-
-
-
 Significant or interesting changes
 ----------------------------------
 
-### acpi: Add Arm IO Remapping Table structures
+* Add changes that need a full description here
 
-Input Output Remapping Table (IORT) represents the IO topology of an Arm
-based system.
-
-Document number: ARM DEN 0049E.e, Sep 2022
-
-
-### acpi: Add PPTT support
-
-This patch adds code to generate Processor Properties Topology Tables
-(PPTT) compliant to the ACPI 6.4 specification.
-
- - The 'acpi_get_pptt_topology' hook is mandatory once ACPI_PPTT is
-   selected. Its purpose is to return a pointer to a topology tree,
-   which describes the relationship between CPUs and caches. The hook
-   can be provided by, for example, mainboard code.
-
-Background: We are currently working on mainboard code for qemu-sbsa and
-Neoverse N2. Both require a valid PPTT table. Patch was tested against
-the qemu-sbsa board.
-
-
-### acpi: Add support for WDAT table
-
-This commit lays the groundwork for implementing the ACPI WDAT (Watchdog
-Action Table) table specification. The WDAT is a special ACPI table
-introduced by Microsoft that describes the watchdog for the OS.
-
-Platforms that need to implement the WDAT table must describe the
-hardware watchdog management operations as described in the
-specification. See “Links to ACPI-Related Documents”
-(http://uefi.org/acpi) under the heading “Watchdog Action Table”.
-
-
-### lib/jpeg: Replace decoder with Wuffs' implementation
-
-To quote its repo[0]: Wuffs is a memory-safe programming language (and a
-standard library written in that language) for Wrangling Untrusted File
-Formats Safely. Wrangling includes parsing, decoding and encoding.
-
-It compiles its library, written in its own language, to a C/C++ source
-file that can then be used independently without needing support for the
-language. That library is now imported to src/vendorcode/wuffs/.
-
-This change modifies our linters to ignore that directory because it's
-supposed to contain the wuffs compiler's result verbatim.
-
-Nigel Tao provided an initial wrapper around wuffs' jpeg decoder that
-implements our JPEG API. I further changed it a bit regarding data
-placement, dropped stuff from our API that wasn't ever used, or isn't
-used anymore, and generally made it fit coreboot a bit better. Features
-are Nigel's, bugs are mine.
-
-This commit also adapts our jpeg fuzz test to work with the modified
-API. After limiting it to deal only with approximately screen sized
-inputs, it fuzzed for 25 hours CPU time without a single hang or crash.
-This is a notable improvement over running the test with our old decoder
-which crashes within a minute.
-
-Finally, I tried the new parser with a pretty-much-random JPEG file I
-got from the internet, and it just showed it (once the resolution
-matched), which is also a notable improvement over the old decoder which
-is very particular about the subset of JPEG it supports.
-
-In terms of code size, a QEmu build's ramstage increases
-from 128060 bytes decompressed (64121 bytes after LZMA)
-  to 172304 bytes decompressed (82734 bytes after LZMA).
-
-[0] https://github.com/google/wuffs
+* This section should have full descriptions and can or should have
+  a link to the referenced commits.
 
 
 
 Additional coreboot changes
 ---------------------------
 
-* Rename Makefiles from .inc to .mk to better identify them
-* SPI: Add GD25LQ255E and IS25WP256D chip support
-* device: Add support for multiple PCI segment groups
-* device: Drop unused multiple downstream link support
-* device: Rename bus and link_list to upstream and downstream
-* Updated devicetree files for modern Intel platforms to use chipset.cb
-* Updated xeon-sp to use the coreboot allocator
+The following are changes across a number of patches, or changes worth
+noting, but not needing a full description.
 
+* Changes that only need a line or two of description go here.
 
 
 Changes to external resources
 -----------------------------
 
 ### Toolchain updates
-* Add buildgcc support for Apple M1/M2 devices
-* crossgcc: Upgrade GCC from 11.4.0 to 13.2.0
-* util/crossgcc: Update CMake from 3.26.4 to 3.27.7
-* util/kconfig: Uprev to Linux 6.7 kconfig
 
 
 ### Git submodule pointers
 
-* /3rdparty/amd_blobs: Update from commit id e4519efca7 to 64cdd7c8ef
-  (5 commits)
-* /3rdparty/arm-trusted-firmware: Update from commit id 88b2d81345 to
-  17bef2248d (701 commits)
-* /3rdparty/fsp: Update from commit id 481ea7cf0b to 507ef01cce (16 commits)
-* /3rdparty/intel-microcode: Update from commit id 6788bb07eb to
-  ece0d294a2 (1 commits)
-* /3rdparty/vboot: Update from commit id 24cb127a5e to 3d37d2aafe (121
-  commits)
-
 
 ### External payloads
-* payload/grub2: Update from 2.06 to 2.12
-* payload/seabios: Update from 1.16.2 to 1.16.3
-
 
 
 Platform Updates
 ----------------
 
 ### Added mainboards:
-* Google: Dita
-* Google: Xol
-* Lenovo: ThinkPad X230 eDP Mod (2K/FHD)
+* To be filled in immediately before the release by the release team
 
 
 ### Removed Mainboards
-* Google ->  Primus4ES
+* To be filled in immediately before the release by the release team
 
 
+### Updated SoCs
+* To be filled in immediately before the release by the release team
+
+
+Plans to move platform support to a branch
+------------------------------------------
+* To be filled in immediately before the release by the release team
+
 
 Statistics from the 4.22 to the 24.02 release
 --------------------------------------------
-
-* Total Commits: 814
-* Average Commits per day: 8.65
-* Total lines added: 105203
-* Average lines added per commit: 129.24
-* Number of patches adding more than 100 lines: 46
-* Average lines added per small commit: 41.34
-* Total lines removed: 16505
-* Average lines removed per commit: 20.28
-* Total difference between added and removed: 88698
-* Total authors: 111
-* New authors: 19
+* To be filled in immediately before the release by the release team
 
 
 
 Significant Known and Open Issues
 ---------------------------------
 
-* AMD chromebooks will not currently work with the signed vboot image.
-
-
-## Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-
-
-### coreboot-wide or architecture-wide issues
-
-```eval_rst
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 522 | 'region_overlap()' issues due to an integer overflow.           |
-+-----+-----------------------------------------------------------------+
-| 519 | make gconfig - could not find glade file                        |
-+-----+-----------------------------------------------------------------+
-| 518 | make xconfig - g++: fatal error: no input files                 |
-+-----+-----------------------------------------------------------------+
-```
-
-
-### Payload-specific issues
-
-```eval_rst
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled       |
-+-----+-----------------------------------------------------------------+
-| 496 | Missing malloc check in libpayload                              |
-+-----+-----------------------------------------------------------------+
-| 484 | No USB keyboard support with secondary payloads                 |
-+-----+-----------------------------------------------------------------+
-| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-+-----+-----------------------------------------------------------------+
-```
-
-
-### Platform-specific issues
-
-```eval_rst
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 517 | lenovo x230 boot stuck with connected external monitor          |
-+-----+-----------------------------------------------------------------+
-| 509 | SD Card hotplug not working on Apollo Lake                      |
-+-----+-----------------------------------------------------------------+
-| 507 | Windows GPU driver fails on Google guybrush & skyrim boards     |
-+-----+-----------------------------------------------------------------+
-| 506 | APL/GML don't boot OS when CPU microcode included "from tree"   |
-+-----+-----------------------------------------------------------------+
-| 505 | Harcuvar CRB - 15 of 16 cores present in the operating system   |
-+-----+-----------------------------------------------------------------+
-| 499 | T440p - EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled    |
-+-----+-----------------------------------------------------------------+
-| 495 | Stoney Chromebooks not booting PSPSecureOS                      |
-+-----+-----------------------------------------------------------------+
-| 478 | X200 booting Linux takes a long time with TSC                   |
-+-----+-----------------------------------------------------------------+
-| 474 | X200s crashes after graphic init with 8GB RAM                   |
-+-----+-----------------------------------------------------------------+
-| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb  |
-+-----+-----------------------------------------------------------------+
-| 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit   |
-+-----+-----------------------------------------------------------------+
-| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-+-----+-----------------------------------------------------------------+
-| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-+-----+-----------------------------------------------------------------+
-| 446 | Optiplex 9010 No Post                                           |
-+-----+-----------------------------------------------------------------+
-| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-+-----+-----------------------------------------------------------------+
-| 427 | x200: Two battery charging issues                               |
-+-----+-----------------------------------------------------------------+
-| 412 | x230 reboots on suspend                                         |
-+-----+-----------------------------------------------------------------+
-| 393 | T500 restarts rather than waking up from suspend                |
-+-----+-----------------------------------------------------------------+
-| 350 | I225 PCIe device not detected on Harcuvar                       |
-+-----+-----------------------------------------------------------------+
-```
+Issues from the coreboot bugtracker: https://ticket.coreboot.org/
+* To be filled in immediately before the release by the release team
 
 
 

Documentation/sbom/sbom.md

@@ -114,7 +114,7 @@ defconfig pointing to your [software-name] generated File.
 as part of your software's build process. For example in form of a
 Makefile target.
 
-2. Change src/sbom/Makefile.mk (in order to know where to find the
+2. Change src/sbom/Makefile.inc (in order to know where to find the
 CoSWID/SWID/uSWID file) as well as the Makefile in coreboot which
 builds said software. For example for GRUB2 that could mean to add a
 Makefile target in payloads/external/GRUB2/Makefile.

Documentation/security/vboot/list_vboot.md

@@ -1,8 +1,7 @@
 # vboot-enabled devices
 
 ## AMD
-- Birman for Phoenix SoC using FSP
-- Birman for Phoenix SoC using openSIL
+- Birman for Phoenix SoC
 - Birman for Glinda SoC
 - Chausie
 - Majolica
@@ -38,7 +37,6 @@
 - Agah
 - Anahera
 - Anahera4ES
-- Anraggar
 - Aurash
 - Banshee
 - Brask
@@ -47,7 +45,6 @@
 - Craaskov
 - Constitution
 - Crota
-- Dochi
 - Felwinter
 - Gaelin
 - Gimble
@@ -65,11 +62,11 @@
 - Moli
 - Nivviks
 - Nereid
-- Nokris
 - Omnigul
 - Osiris
 - Pirrha
 - Primus
+- Primus4ES
 - Pujjo
 - Quandiso
 - Redrix
@@ -86,7 +83,9 @@
 - Yaviks
 - Yavilla
 - Zydron
-- Xol
+- Nokris
+- Dochi
+- Anraggar
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
 - Dojo
@@ -221,18 +220,18 @@
 - Sand (Acer Chromebook 15 CB515-1HT/1H)
 - Snappy (HP Chromebook x360 11 G1 EE)
 - Coral
-- Deku
-- Deku4ES
-- Karis
-- Karis4ES
-- Ovis
-- Ovis4ES
 - Rex 0
-- Rex EC ISH
-- Rex4ES
-- Rex4ES EC ISH
 - Screebo
 - Screebo4ES
+- Karis
+- Karis4ES
+- Rex EC ISH
+- Ovis
+- Ovis4ES
+- Deku
+- Deku4ES
+- Rex4ES
+- Rex4ES EC ISH
 - Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
 - Sarien (Dell Latitude 5400 Chromebook Enterprise)
 - Crystaldrift

Documentation/technotes/2020-03-unit-testing-coreboot.md

@@ -247,13 +247,13 @@ tests/lib/string-test and tests/device/i2c-test:
 │   ├── include
 │   │   ├── mocks <- mock headers, which replace original headers
 │   │
-│   ├── Makefile.mk <- top Makefile for unit tests subsystem
+│   ├── Makefile.inc <- top Makefile for unit tests subsystem
 │   ├── lib
-│   │   ├── Makefile.mk
+│   │   ├── Makefile.inc
 │   │   ├── string-test.c <- test code for src/lib/string.c
 │   │   │
 │   ├── device
-│   │   ├── Makefile.mk
+│   │   ├── Makefile.inc
 │       ├── i2c-test.c
 │
 ├── build

Documentation/tutorial/part3.md

@@ -96,8 +96,8 @@ suffix `-test` to the UUT name when creating a new test harness file.
    be registered with the coreboot unit testing infrastructure.
 ```
 
-Every directory under `tests/` should contain a Makefile.mk, similar to
-what can be seen under the `src/`. Register a new test in Makefile.mk,
+Every directory under `tests/` should contain a Makefile.inc, similar to
+what can be seen under the `src/`. Register a new test in Makefile.inc,
 by __appending__ test name to the `tests-y` variable.
 
 ```eval_rst
@@ -285,7 +285,7 @@ stimulate UUT as required without changing the source code.
 
 coreboot unit test infrastructure supports overriding of functions at
 link time.  This is as simple as adding a `name_of_function` to be
-mocked into <test_name>-mocks variable in Makefile.mk. The result is
+mocked into <test_name>-mocks variable in Makefile.inc. The result is
 that the test's implementation of that function is called instead of
 coreboot's.
 

Documentation/util.md

@@ -144,6 +144,7 @@ from the local git repository for auditing or release `Bash`
 Does not show variants. `Shell`
 	* _ucode_h_to_bin.sh_ - Microcode conversion tool `Bash`
 	* _update_submodules_ - Check all submodules for updates `Bash`
+* __showdevicetree__ - Compile and dump the device tree `C`
 * __spdtool__ - Dumps SPD ROMs from a given blob to separate files
 using known patterns and reserved bits. Useful for analysing firmware
 that holds SPDs on boards that have soldered down DRAM. `python`

LICENSES/LGPL-2.1-or-later.txt

@@ -1,175 +0,0 @@
-GNU LESSER GENERAL PUBLIC LICENSE
-
-Version 2.1, February 1999
-
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-51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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-
-[This is the first released version of the Lesser GPL.  It also counts as the successor of the GNU Library Public License, version 2, hence the version number 2.1.]
-
-Preamble
-
-The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public Licenses are intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users.
-
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-
-When we speak of free software, we are referring to freedom of use, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish); that you receive source code or can get it if you want it; that you can change the software and use pieces of it in new free programs; and that you are informed that you can do these things.
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-14. If you wish to incorporate parts of the Library into other free programs whose distribution conditions are incompatible with these, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally.
-
-NO WARRANTY
-
-15. BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE LIBRARY, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE LIBRARY "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE LIBRARY IS WITH YOU. SHOULD THE LIBRARY PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
-
-16. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE LIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-
-END OF TERMS AND CONDITIONS
-
-How to Apply These Terms to Your New Libraries
-
-If you develop a new library, and you want it to be of the greatest possible use to the public, we recommend making it free software that everyone can redistribute and change. You can do so by permitting redistribution under these terms (or, alternatively, under the terms of the ordinary General Public License).
-
-To apply these terms, attach the following notices to the library. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found.
-
-     one line to give the library's name and an idea of what it does.
-     Copyright (C) year  name of author
-
-     This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version.
-
-     This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public License for more details.
-
-     You should have received a copy of the GNU Lesser General Public License along with this library; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA Also add information on how to contact you by electronic and paper mail.
-
-You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the library, if necessary. Here is a sample; alter the names:
-
-Yoyodyne, Inc., hereby disclaims all copyright interest in
-the library `Frob' (a library for tweaking knobs) written
-by James Random Hacker.
-
-signature of Ty Coon, 1 April 1990
-Ty Coon, President of Vice
-That's all there is to it!

MAINTAINERS

@@ -359,7 +359,6 @@ GOOGLE BRYA MAINBOARDS
 M:	Subrata Banik <subratabanik@google.com>
 M:	Nick Vaccaro <nvaccaro@chromium.org>
 M:	Eric Lai <ericllai@google.com>
-M:	Kapil Porwal <kapilporwal@google.com>
 S:	Maintained
 F:	src/mainboard/google/brya/
 
@@ -896,7 +895,6 @@ F:	src/soc/intel/meteorlake/
 INTEL ALDERLAKE SOC
 M:	Subrata Banik <subratabanik@google.com>
 M:	Nick Vaccaro <nvaccaro@chromium.org>
-M:	Kapil Porwal <kapilporwal@google.com>
 S:	Maintained
 F:	src/soc/intel/alderlake/
 
@@ -941,14 +939,10 @@ M:	Johnny Lin <Johnny_Lin@wiwynn.com>
 M:	Tim Chu <Tim.Chu@quantatw.com>
 M:	Arthur Heymans <arthur@aheymans.xyz>
 M:	Christian Walter <christian.walter@9elements.com>
-M:	Shuo Liu <shuo.liu@intel.com>
-M:	Patrick Rudolph <patrick.rudolph@9elements.com>
-M:	Lean Sheng Tan <sheng.tan@9elements.com>
 S:	Supported
 F:	src/soc/intel/xeon_sp/
 F:	src/vendorcode/intel/fsp/fsp2_0/skylake_sp/
 F:	src/vendorcode/intel/fsp/fsp2_0/copperlake_sp/
-F:	src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/
 
 MEDIATEK SOCS
 M:	Hung-Te Lin <hungte@chromium.org>

Makefile

@@ -50,7 +50,7 @@ rwildcard=$(wildcard $1$2) $(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2))
 SYMLINK_LIST = $(call rwildcard,site-local/,symlink.txt)
 
 
-# Directory containing the toplevel Makefile.mk
+# directory containing the toplevel Makefile.inc
 TOPLEVEL := .
 
 CONFIG_SHELL := sh
@@ -102,7 +102,7 @@ help_coreboot help::
 
 # This include must come _before_ the pattern rules below!
 # Order _does_ matter for pattern rules.
-include $(srck)/Makefile.mk
+include $(srck)/Makefile.inc
 
 # The cases where we don't need fully populated $(obj) lists:
 # 1. when no .config exists
@@ -153,12 +153,11 @@ ifeq ($(NOCOMPILE),1)
 HOSTCC ?= $(if $(shell type gcc 2>/dev/null),gcc,cc)
 HOSTCXX ?= g++
 
-include $(TOPLEVEL)/Makefile.mk
-include $(TOPLEVEL)/payloads/Makefile.mk
-include $(TOPLEVEL)/util/testing/Makefile.mk
--include $(TOPLEVEL)/site-local/Makefile.mk
+include $(TOPLEVEL)/Makefile.inc
+include $(TOPLEVEL)/payloads/Makefile.inc
+include $(TOPLEVEL)/util/testing/Makefile.inc
 -include $(TOPLEVEL)/site-local/Makefile.inc
-include $(TOPLEVEL)/tests/Makefile.mk
+include $(TOPLEVEL)/tests/Makefile.inc
 printall real-all:
 	@echo "Error: Trying to build, but NOCOMPILE is set." >&2
 	@echo "  Please file a bug with the following information:"
@@ -199,7 +198,7 @@ endif
 export LANG LC_ALL TZ SOURCE_DATE_EPOCH
 
 ifneq ($(UNIT_TEST),1)
-include toolchain.mk
+include toolchain.inc
 endif
 
 strip_quotes = $(strip $(subst ",,$(subst \",,$(1))))
@@ -277,7 +276,7 @@ src-to-ali=\
 	$(subst .$(1),,\
 	$(filter %.ads %.adb,$(2)))))))))
 
-# Clean -y variables, include Makefile.mk & Makefile.inc
+# Clean -y variables, include Makefile.inc
 # Add paths to files in X-y to X-srcs
 # Add subdirs-y to subdirs
 includemakefiles= \
@@ -296,12 +295,9 @@ includemakefiles= \
 
 # For each path in $(subdirs) call includemakefiles
 # Repeat until subdirs is empty
-# TODO: Remove Makefile.inc support
 evaluate_subdirs= \
 	$(eval cursubdirs:=$(subdirs)) \
 	$(eval subdirs:=) \
-	$(foreach dir,$(cursubdirs), \
-		$(eval $(call includemakefiles,$(dir)/Makefile.mk))) \
 	$(foreach dir,$(cursubdirs), \
 		$(eval $(call includemakefiles,$(dir)/Makefile.inc))) \
 	$(if $(subdirs),$(eval $(call evaluate_subdirs)))
@@ -310,11 +306,11 @@ evaluate_subdirs= \
 subdirs:=$(TOPLEVEL)
 postinclude-hooks :=
 
-# Don't iterate through Makefiles under src/ when building tests
+# Don't iterate through Makefile.incs under src/ when building tests
 ifneq ($(UNIT_TEST),1)
 $(eval $(call evaluate_subdirs))
 else
-include $(TOPLEVEL)/tests/Makefile.mk
+include $(TOPLEVEL)/tests/Makefile.inc
 endif
 
 ifeq ($(FAILBUILD),1)

Makefile.inc

@@ -498,7 +498,6 @@ CFLAGS_common += -Wdangling-else -Wmissing-include-dirs
 CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
 CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie
 ifeq ($(CONFIG_COMPILER_GCC),y)
-CFLAGS_common += -Wold-style-declaration
 # Don't add these GCC specific flags when running scan-build
 ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
 CFLAGS_common += -Wno-packed-not-aligned
@@ -768,7 +767,7 @@ gitconfig:
 install-git-commit-clangfmt:
 	cp util/scripts/prepare-commit-msg.clang-format .git/hooks/prepare-commit-msg
 
-include util/crossgcc/Makefile.mk
+include util/crossgcc/Makefile.inc
 
 .PHONY: tools
 tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER) $(AMDFWREAD)
@@ -1158,7 +1157,7 @@ FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE))
 
 endif # ifeq ($(CONFIG_ARCH_X86),y)
 
-$(obj)/fmap.fmd: $(top)/Makefile.mk $(DEFAULT_FLASHMAP) $(obj)/config.h
+$(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h
 	sed -e "s,##ROM_BASE##,$(FMAP_ROM_ADDR)," \
 	    -e "s,##ROM_SIZE##,$(FMAP_ROM_SIZE)," \
 	    -e "s,##BIOS_BASE##,$(FMAP_BIOS_BASE)," \

README.md

@@ -30,7 +30,7 @@ Code reviews are done in [the project's Gerrit
 instance](https://review.coreboot.org/).
 
 The code may be browsed via [coreboot's Gitiles
-instance](https://review.coreboot.org/plugins/gitiles/coreboot/+/HEAD).
+instance](https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master).
 
 The coreboot project also maintains a
 [mirror](https://github.com/coreboot/coreboot) of the project on github.

payloads/Kconfig

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 menu "Payload"
 
 config PAYLOAD_NONE
@@ -82,14 +80,13 @@ config COMPRESSED_PAYLOAD_LZ4
 endchoice
 
 config PAYLOAD_OPTIONS
-	string "Additional cbfstool options"
+	string
 	default ""
 	help
 	  Additional cbfstool options for the payload
 
 config PAYLOAD_IS_FLAT_BINARY
-	bool "Payload is a flat binary"
-	default n
+	def_bool n
 	help
 	  Add the payload to cbfs as a flat binary type instead of as an
 	  elf payload

payloads/coreinfo/Makefile

@@ -70,7 +70,7 @@ $(obj)/config.h:
 
 $(shell mkdir -p $(objk)/lxdialog $(KCONFIG_SPLITCONFIG))
 
-include $(srck)/Makefile.mk
+include $(srck)/Makefile.inc
 
 .PHONY: $(PHONY) prepare all real-all defaultbuild
 

payloads/external/BOOTBOOT/Kconfig

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 if PAYLOAD_BOOTBOOT
 
 config PAYLOAD_FILE

payloads/external/BOOTBOOT/Kconfig.name

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 config PAYLOAD_BOOTBOOT
 	bool "BOOTBOOT"
 	depends on ARCH_X86 || ARCH_ARM64

payloads/external/FILO/Kconfig

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 if PAYLOAD_FILO
 
 choice

payloads/external/FILO/Kconfig.name

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 config PAYLOAD_FILO
 	bool "FILO"
 	depends on ARCH_X86

payloads/external/GRUB2/Kconfig

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 config PAYLOAD_BUILD_GRUB2
 	bool
 
@@ -17,7 +15,7 @@ choice
 	default GRUB2_STABLE
 
 config GRUB2_STABLE
-	bool "2.12"
+	bool "2.06"
 	help
 	  Stable GRUB2 version
 

payloads/external/GRUB2/Kconfig.name

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 config PAYLOAD_GRUB2
 	bool "GRUB2"
 	depends on ARCH_X86 || ARCH_ARM

payloads/external/GRUB2/Makefile

@@ -1,9 +1,9 @@
 TAG-$(CONFIG_GRUB2_MASTER)=origin/HEAD
 TAG-$(CONFIG_GRUB2_REVISION)=$(CONFIG_GRUB2_REVISION_ID)
-TAG-$(CONFIG_GRUB2_STABLE)=grub-2.12
+TAG-$(CONFIG_GRUB2_STABLE)=grub-2.06
 NAME-$(CONFIG_GRUB2_MASTER)=HEAD
 NAME-$(CONFIG_GRUB2_REVISION)=$(CONFIG_GRUB2_REVISION_ID)
-NAME-$(CONFIG_GRUB2_STABLE)=2.12
+NAME-$(CONFIG_GRUB2_STABLE)=2.06
 
 project_git_repo=https://git.savannah.gnu.org/git/grub.git/
 project_dir=grub2

payloads/external/Memtest86Plus/Kconfig.secondary

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 if MEMTEST_SECONDARY_PAYLOAD
 
 comment "Memtest86+"

payloads/external/SeaBIOS/Kconfig

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 config PAYLOAD_BUILD_SEABIOS
 	bool
 
@@ -17,7 +15,7 @@ choice
 	default SEABIOS_STABLE
 
 config SEABIOS_STABLE
-	bool "1.16.3"
+	bool "1.16.2"
 	help
 	  Stable SeaBIOS version
 config SEABIOS_MASTER

payloads/external/SeaBIOS/Kconfig.name

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 config PAYLOAD_SEABIOS
 	bool "SeaBIOS"
 	depends on ARCH_X86

payloads/external/SeaBIOS/Makefile

@@ -1,5 +1,5 @@
 TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
-TAG-$(CONFIG_SEABIOS_STABLE)=a6ed6b701f0a57db0569ab98b0661c12a6ec3ff8
+TAG-$(CONFIG_SEABIOS_STABLE)=ea1b7a0733906b8425d948ae94fba63c32b1d425
 TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)
 
 project_git_repo=https://review.coreboot.org/seabios.git

payloads/external/U-Boot/Kconfig

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 if PAYLOAD_UBOOT
 
 config PAYLOAD_SPECIFIC_OPTIONS

payloads/external/U-Boot/Kconfig.name

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 config PAYLOAD_UBOOT
 	bool "U-Boot"
 	depends on ARCH_X86

payloads/external/coreDOOM/Kconfig.secondary

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 if COREDOOM_SECONDARY_PAYLOAD
 
 config COREDOOM_WAD_FILE

payloads/external/depthcharge/Kconfig

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 if PAYLOAD_DEPTHCHARGE
 
 choice

payloads/external/depthcharge/Kconfig.name

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 config PAYLOAD_DEPTHCHARGE
 	bool "Depthcharge"
 	depends on CHROMEOS

payloads/external/edk2/Kconfig

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 if PAYLOAD_EDK2
 
 config PAYLOAD_FILE

payloads/external/edk2/Kconfig.name

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 config PAYLOAD_EDK2
 	bool "edk2 payload"
 	depends on ARCH_X86 || ARCH_ARM64

payloads/external/linux/Kconfig

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 if PAYLOAD_LINUX
 
 config PAYLOAD_FILE

payloads/external/linux/Kconfig.name

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 config PAYLOAD_LINUX
 	bool "A Linux payload"
 	depends on ARCH_X86 || ARCH_ARM || ARCH_RISCV

payloads/libpayload/Kconfig

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 ##
 ##
 ## Copyright (C) 2008 Advanced Micro Devices, Inc.

payloads/libpayload/Makefile

@@ -56,7 +56,7 @@ export KCONFIG_NEGATIVES := 1
 export KBUILD_KCONFIG := Kconfig
 export CONFIG_ := CONFIG_LP_
 
-# directory containing the toplevel Makefile.mk
+# directory containing the toplevel Makefile.inc
 TOPLEVEL := .
 
 CONFIG_LP_SHELL := sh
@@ -103,7 +103,7 @@ endif
 
 # This include must come _before_ the pattern rules below!
 # Order _does_ matter for pattern rules.
-include $(srck)/Makefile.mk
+include $(srck)/Makefile.inc
 
 include $(HAVE_DOTCONFIG)
 
@@ -127,7 +127,7 @@ ARCH-$(CONFIG_LP_ARCH_MOCK)    := mock
 # 3. when make distclean is run
 # 4. when make help% or make clean% is run
 # 5. when make %-test or make %-tests or make %coverage-report is run
-# Don't waste time on reading all Makefiles in these cases
+# Don't waste time on reading all Makefile.incs in these cases
 ifeq ($(strip $(HAVE_DOTCONFIG)),)
 NOCOMPILE := 1
 endif
@@ -159,8 +159,8 @@ $(xcompile): $(top)/../../util/xcompile/xcompile
 	\mv -f $@.tmp $@ 2> /dev/null
 
 ifeq ($(NOCOMPILE),1)
-include $(TOPLEVEL)/Makefile.mk
-include $(TOPLEVEL)/tests/Makefile.mk
+include $(TOPLEVEL)/Makefile.inc
+include $(TOPLEVEL)/tests/Makefile.inc
 real-all: config
 
 else
@@ -285,7 +285,7 @@ add-special-class= \
 	$(eval $(1):=) \
 	$(eval special-classes+=$(1))
 
-# Clean -y variables, include Makefile.mk
+# Clean -y variables, include Makefile.inc
 # Add paths to files in X-y to X-srcs
 # Add subdirs-y to subdirs
 includemakefiles= \
@@ -308,7 +308,7 @@ evaluate_subdirs= \
 	$(eval cursubdirs:=$(subdirs)) \
 	$(eval subdirs:=) \
 	$(foreach dir,$(cursubdirs), \
-		$(eval $(call includemakefiles,$(dir)/Makefile.mk))) \
+		$(eval $(call includemakefiles,$(dir)/Makefile.inc))) \
 	$(if $(subdirs),$(eval $(call evaluate_subdirs)))
 
 # collect all object files eligible for building or run unit-tests
@@ -316,7 +316,7 @@ ifneq ($(UNIT_TEST),1)
 subdirs:=$(TOPLEVEL)
 $(eval $(call evaluate_subdirs))
 else
-include $(TOPLEVEL)/tests/Makefile.mk
+include $(TOPLEVEL)/tests/Makefile.inc
 endif
 
 # Converts one or more source file paths to the corresponding build/ paths.

payloads/libpayload/Makefile.inc

@@ -120,16 +120,23 @@ $(obj)/head.o: $(obj)/arch/$(ARCHDIR-y)/head.head.o.o
 install: real-target
 	printf "    INSTALL    $(DESTDIR)/libpayload/lib\n"
 	install -m 755 -d $(DESTDIR)/libpayload/lib
-	install -m 644 $(library-targets) $(DESTDIR)/libpayload/lib/
+	for lib in $(library-targets); do \
+		install -m 644 $$lib $(DESTDIR)/libpayload/lib/; \
+	done
 	install -m 644 arch/$(ARCHDIR-y)/libpayload.ldscript $(DESTDIR)/libpayload/lib/
 	install -m 755 -d $(DESTDIR)/libpayload/lib/$(ARCHDIR-y)
 	install -m 644 $(obj)/head.o $(DESTDIR)/libpayload/lib/$(ARCHDIR-y)
 	printf "    INSTALL    $(DESTDIR)/libpayload/include\n"
 	install -m 755 -d $(DESTDIR)/libpayload/include
-	find include -type d -exec install -m755 -d $(DESTDIR)/libpayload/{} \;
-	find include -type f -exec install -m644 {} $(DESTDIR)/libpayload/{} \;
-	cd $(coreboottop)/src/commonlib/bsd && find include -type d -exec install -m755 -d $(abspath $(DESTDIR))/libpayload/{} \;
-	cd $(coreboottop)/src/commonlib/bsd && find include -type f -exec install -m644 {} $(abspath $(DESTDIR))/libpayload/{} \;
+	for file in `find include -name *.h -type f`; do \
+		install -m 755 -d $(DESTDIR)/libpayload/`dirname $$file`; \
+		install -m 644 $$file $(DESTDIR)/libpayload/$$file; \
+	done
+	for file in `find $(coreboottop)/src/commonlib/bsd/include -name *.h -type f`; do \
+		dest_file=$$(realpath --relative-to=$(coreboottop)/src/commonlib/bsd/ $$file); \
+		install -m 755 -d "$(DESTDIR)/libpayload/`dirname $$dest_file`"; \
+		install -m 644 "$$file" "$(DESTDIR)/libpayload/$$dest_file"; \
+	done
 	install -m 644 $(obj)/libpayload-config.h $(DESTDIR)/libpayload/include
 	$(foreach item,$(includes), \
 		install -m 755 -d $(DESTDIR)/libpayload/include/$(call extract_nth,2,$(item)); \

payloads/libpayload/arch/arm/Kconfig

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 ##
 ##
 ## Copyright (c) 2012 Google Inc.

payloads/libpayload/arch/arm64/Kconfig

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 ##
 ##
 ## Copyright (c) 2012 Google Inc.

payloads/libpayload/arch/arm64/libpayload.ldscript

@@ -62,6 +62,8 @@ SECTIONS
 	}
 
 	.bss : {
+		*(.ttb_buffer)
+
 		_bss = .;
 		*(.sbss)
 		*(.sbss.*)

payloads/libpayload/arch/arm64/mmu.c

@@ -41,14 +41,8 @@ static unsigned int max_tables;
 static uint64_t *xlat_addr;
 
 static int free_idx;
-
-/*
- * We refer to the section ".bss.ttb_buffer" in the linker script for ChromeOS's depthcharge
- * payload. Please DO NOT change the section name without discussing with us.
- * Please contact: jwerner@chromium.org or yich@chromium.org
- */
 static uint8_t ttb_buffer[TTB_DEFAULT_SIZE] __aligned(GRANULE_SIZE)
-	__section(".bss.ttb_buffer");
+	__attribute__((__section__(".ttb_buffer")));
 
 static const char * const tag_to_string[] = {
 	[TYPE_NORMAL_MEM] = "normal",

payloads/libpayload/arch/x86/Kconfig

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 ##
 ##
 ## Copyright (c) 2012 Google Inc.

payloads/libpayload/drivers/timer/arm64_arch_timer.c

@@ -32,7 +32,7 @@
 #include <arch/lib_helpers.h>
 #include <libpayload.h>
 
-uint64_t timer_hz(void)
+uint32_t timer_hz(void)
 {
 	return raw_read_cntfrq_el0();
 }

payloads/libpayload/drivers/timer/generic.c

@@ -33,8 +33,10 @@
 #include <assert.h>
 #include <libpayload.h>
 
-uint64_t timer_hz(void)
+uint32_t timer_hz(void)
 {
+	/* libc/time.c currently requires all timers to be at least 1MHz. */
+	assert(CONFIG_LP_TIMER_GENERIC_HZ >= 1000000);
 	return CONFIG_LP_TIMER_GENERIC_HZ;
 }
 

payloads/libpayload/drivers/timer/rdtsc.c

@@ -35,9 +35,10 @@
 #include <arch/rdtsc.h>
 #include <assert.h>
 
-uint64_t timer_hz(void)
+uint32_t timer_hz(void)
 {
-	return (uint64_t)lib_sysinfo.cpu_khz * 1000;
+	assert(UINT32_MAX / 1000 >= lib_sysinfo.cpu_khz);
+	return lib_sysinfo.cpu_khz * 1000;
 }
 
 uint64_t timer_raw_value(void)

payloads/libpayload/include/coreboot_tables.h

@@ -30,7 +30,7 @@
 #define _COREBOOT_TABLES_H
 
 #include <arch/types.h>
-#include <commonlib/bsd/ipchksum.h>
+#include <ipchksum.h>
 #include <stdint.h>
 
 enum {

payloads/libpayload/include/ipchksum.h

@@ -0,0 +1,39 @@
+/*
+ *
+ * Copyright (c) 2012 The ChromiumOS Authors.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __IPCHKSUM_H__
+#define __IPCHKSUM_H__
+
+/**
+ * @defgroup ipchecksum IP checksum functions
+ * @{
+ */
+unsigned short ipchksum(const void *ptr, unsigned long nbytes);
+/** @} */
+
+#endif

payloads/libpayload/include/libpayload.h

@@ -48,12 +48,12 @@
 #include <commonlib/bsd/elog.h>
 #include <commonlib/bsd/fmap_serialized.h>
 #include <commonlib/bsd/helpers.h>
-#include <commonlib/bsd/ipchksum.h>
 #include <commonlib/bsd/mem_chip_info.h>
 #include <ctype.h>
 #include <die.h>
 #include <endian.h>
 #include <fmap.h>
+#include <ipchksum.h>
 #include <kconfig.h>
 #include <stddef.h>
 #include <stdio.h>
@@ -519,7 +519,7 @@ void lib_sysinfo_get_memranges(struct memrange **ranges,
 
 /* Timer functions. */
 /* Defined by each architecture. */
-uint64_t timer_hz(void);
+uint32_t timer_hz(void);
 uint64_t timer_raw_value(void);
 uint64_t timer_us(uint64_t base);
 /* Generic. */

payloads/libpayload/libc/Makefile.inc

@@ -28,7 +28,7 @@
 ##
 
 libc-$(CONFIG_LP_LIBC) += malloc.c printf.c console.c string.c
-libc-$(CONFIG_LP_LIBC) += memory.c ctype.c lib.c libgcc.c
+libc-$(CONFIG_LP_LIBC) += memory.c ctype.c ipchecksum.c lib.c libgcc.c
 libc-$(CONFIG_LP_LIBC) += rand.c time.c exec.c
 libc-$(CONFIG_LP_LIBC) += readline.c getopt_long.c sysinfo.c
 libc-$(CONFIG_LP_LIBC) += args.c
@@ -47,5 +47,4 @@ endif
 ifeq ($(CONFIG_LP_LIBC),y)
 libc-srcs += $(coreboottop)/src/commonlib/bsd/elog.c
 libc-srcs += $(coreboottop)/src/commonlib/bsd/gcd.c
-libc-srcs += $(coreboottop)/src/commonlib/bsd/ipchksum.c
 endif

payloads/libpayload/libc/getopt_long.c

@@ -122,7 +122,7 @@ permute_args(int panonopt_start, int panonopt_end, int opt_end,
 	 */
 	nnonopts = panonopt_end - panonopt_start;
 	nopts = opt_end - panonopt_end;
-	ncycle = gcd(nnonopts, nopts);
+	ncycle = gcd32(nnonopts, nopts);
 	cyclelen = (opt_end - panonopt_start) / ncycle;
 
 	for (i = 0; i < ncycle; i++) {

payloads/libpayload/libc/ipchecksum.c

@@ -0,0 +1,52 @@
+/*
+ *
+ * It has originally been taken from the FreeBSD project.
+ *
+ * Copyright (c) 2001 Charles Mott <cm@linktel.net>
+ * Copyright (c) 2008 coresystems GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <libpayload.h>
+
+unsigned short ipchksum(const void *vptr, unsigned long nbytes)
+{
+	int sum, oddbyte;
+	const unsigned short *ptr = vptr;
+
+	sum = 0;
+	while (nbytes > 1) {
+		sum += *ptr++;
+		nbytes -= 2;
+	}
+	if (nbytes == 1) {
+		oddbyte = 0;
+		((u8 *) & oddbyte)[0] = *(u8 *) ptr;
+		((u8 *) & oddbyte)[1] = 0;
+		sum += oddbyte;
+	}
+	sum = (sum >> 16) + (sum & 0xffff);
+	sum += (sum >> 16);
+	return (~sum);
+}

payloads/libpayload/libc/time.c

@@ -171,19 +171,18 @@ void arch_ndelay(uint64_t ns)
 
 u64 timer_us(u64 base)
 {
-	static u64 hz;
-	static u32 mult = USECS_PER_SEC;
+	static u32 hz, mult = USECS_PER_SEC;
 	u32 div;
 
 	// Only check timer_hz once. Assume it doesn't change.
 	if (hz == 0) {
 		hz = timer_hz();
 		if (hz < mult) {
-			printf("Timer frequency %" PRIu64 " is too low, "
+			printf("Timer frequency %" PRIu32 " is too low, "
 			       "must be at least 1MHz.\n", hz);
 			halt();
 		}
-		div = gcd(hz, mult);
+		div = gcd32(hz, mult);
 		hz /= div;
 		mult /= div;
 	}

payloads/libpayload/tests/Makefile.inc

@@ -105,7 +105,7 @@ define TEST_CC_template
 $(1)-config-file := $(testobj)/$(1)/libpayload-config.h
 $$($(1)-config-file): $(TEST_KCONFIG_AUTOHEADER)
 	mkdir -p $$(dir $$@);
-	printf '// File generated by tests/Makefile.mk\n// Do not change\n' > $$@;
+	printf '// File generated by tests/Makefile.inc\n// Do not change\n' > $$@;
 	printf '#ifndef TEST_LIBPAYLOAD_CONFIG_H_\n' >> $$@;
 	printf '#define TEST_LIBPAYLOAD_CONFIG_H_\n' >> $$@;
 	printf '#include <%s>\n\n' "$(notdir $(TEST_KCONFIG_AUTOHEADER))" >> $$@;

payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c

@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
+/* SPDX-License-Identifier: GPL-2.0.-only */
 
 #include <libpayload-config.h>
 #include <cbfs.h>

payloads/libpayload/vboot/Kconfig

@@ -31,16 +31,6 @@ config VBOOT_X86_SHA_EXT
 	  This option enables SHA256 implementation using x86 SHA processor extension
 	  instructions: sha256msg1, sha256msg2, sha256rnds2.
 
-config VBOOT_X86_RSA_ACCELERATION
-	bool "Use SSE2 instructions for RSA signature verification"
-	default y if CHROMEOS
-	default n
-	depends on ARCH_X86
-	help
-	  Use paddq, pmuludq, psrlq, punpckldq and punpcklqdq SSE2
-	  instructions to accelerate the modulus exponentiation which
-	  is part of the RSA signature verification process.
-
 config VBOOT_SHA_ARMV8_CE
 	bool "SHA256 implementation using ARMv8 Crypto Extension"
 	default y if CHROMEOS

payloads/libpayload/vboot/Makefile.inc

@@ -13,27 +13,20 @@ vboot-fixup-includes = $(filter -I$(coreboottop)/%, $(1)) \
 		       $(patsubst include/%.h,$(top)/include/%.h,\
 		       $(filter-out -I$(obj),\
 		       $(filter-out -I$(coreboottop)/%,$(1)))))
-
-VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM) := arm
-VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_X86) := x86
-VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64
-
-ifneq ($(CONFIG_LP_ARCH_MOCK),)
-VBOOT_FIRMWARE_ARCH-y := mock
-else
+ifeq ($(CONFIG_LP_ARCH_MOCK),)
 VBOOT_CFLAGS += $(call vboot-fixup-includes,$(CFLAGS))
 VBOOT_CFLAGS += -I$(abspath $(obj))
 endif
 
-ifeq ($(VBOOT_FIRMWARE_ARCH-y),)
-$(error vboot requires architecture to be set in the configuration)
-endif
-
 # Enable vboot debug by default
 VBOOT_CFLAGS += -DVBOOT_DEBUG
 
-ifeq ($(CONFIG_LP_VBOOT_X86_RSA_ACCELERATION),y)
-CPPFLAGS_common += -DVB2_X86_RSA_ACCELERATION
+VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM) := arm
+VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_X86) := x86
+VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64
+
+ifeq ($(CONFIG_LP_ARCH_MOCK)$(VBOOT_FIRMWARE_ARCH-y),)
+$(error vboot requires architecture to be set in the configuration)
 endif
 
 $(VBOOT_FW_LIB): $(obj)/libpayload-config.h
@@ -44,7 +37,6 @@ $(VBOOT_FW_LIB): $(obj)/libpayload-config.h
 		$(MAKE) -C "$(VBOOT_SOURCE)" \
 		TPM2_MODE=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_TPM2_MODE)) \
 		X86_SHA_EXT=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_X86_SHA_EXT)) \
-		VB2_X86_RSA_ACCELERATION=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_X86_RSA_ACCELERATION)) \
 		ARMV8_CRYPTO_EXT=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_SHA_ARMV8_CE)) \
 		UNROLL_LOOPS=1 \
 		BUILD="$(VBOOT_BUILD_DIR)" \

src/Kconfig

@@ -759,7 +759,8 @@ config RTC
 
 config HEAP_SIZE
 	hex
-	default 0x100000
+	default 0x100000 if FLATTENED_DEVICE_TREE
+	default 0x4000
 
 config STACK_SIZE
 	hex
@@ -906,7 +907,6 @@ menu "System tables"
 config GENERATE_MP_TABLE
 	prompt "Generate an MP table" if HAVE_MP_TABLE
 	bool
-	depends on !ECAM_MMCONF_SUPPORT || ECAM_MMCONF_BUS_NUMBER <= 256
 	default HAVE_MP_TABLE
 	help
 	  Generate an MP table (conforming to the Intel MultiProcessor
@@ -1492,7 +1492,7 @@ config MEMLAYOUT_LD_FILE
 	  This variable allows SoC/mainboard to supply in a custom linker file
 	  if required. This determines the linker file used for all the stages
 	  (bootblock, romstage, verstage, ramstage, postcar) in
-	  src/arch/${ARCH}/Makefile.mk.
+	  src/arch/${ARCH}/Makefile.inc.
 
 ###############################################################################
 # Set default values for symbols created before mainboards.  This allows the

src/acpi/acpi.c

@@ -150,14 +150,9 @@ static void acpi_create_madt(acpi_header_t *header, void *unused)
 
 static unsigned long acpi_fill_mcfg(unsigned long current)
 {
-	for (int i = 0; i < PCI_SEGMENT_GROUP_COUNT; i++) {
-		current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
-			CONFIG_ECAM_MMCONF_BASE_ADDRESS + i * PCI_PER_SEGMENT_GROUP_ECAM_SIZE,
-			i,
-			0,
-			PCI_BUSES_PER_SEGMENT_GROUP - 1);
-	}
-
+	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
+			CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0, 0,
+			CONFIG_ECAM_MMCONF_BUS_NUMBER - 1);
 	return current;
 }
 
@@ -352,22 +347,17 @@ int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek,
 }
 
 int acpi_create_srat_gia_pci(acpi_srat_gia_t *gia, u32 proximity_domain,
-			     struct device *dev, u32 flags)
+				u16 seg, u8 bus, u8 dev, u8 func, u32 flags)
 {
-	/* Only handle PCI devices. */
-	if (dev->path.type != DEVICE_PATH_PCI)
-		return 0;
-
 	gia->type = ACPI_SRAT_STRUCTURE_GIA;
 	gia->length = sizeof(acpi_srat_gia_t);
 	gia->proximity_domain = proximity_domain;
 	gia->dev_handle_type = ACPI_SRAT_GIA_DEV_HANDLE_PCI;
 	/* First two bytes has segment number */
-	gia->dev_handle[0] = dev->upstream->segment_group;
-	gia->dev_handle[1] = 0;
-	gia->dev_handle[2] = dev->upstream->secondary; /* Byte 2 has bus number */
+	memcpy(gia->dev_handle, &seg, 2);
+	gia->dev_handle[2] = bus; /* Byte 2 has bus number */
 	/* Byte 3 has bits 7:3 for dev, bits 2:0 for func */
-	gia->dev_handle[3] = dev->path.pci.devfn;
+	gia->dev_handle[3] = PCI_SLOT(dev) | PCI_FUNC(func);
 	gia->flags = flags;
 
 	return gia->length;
@@ -705,8 +695,7 @@ void acpi_create_ipmi(const struct device *device,
 
 	if (device->path.type == DEVICE_PATH_PCI) {
 		spmi->pci_device_flag = ACPI_IPMI_PCI_DEVICE_FLAG;
-		spmi->pci_segment_group = device->upstream->segment_group;
-		spmi->pci_bus = device->upstream->secondary;
+		spmi->pci_bus = device->bus->secondary;
 		spmi->pci_device = device->path.pci.devfn >> 3;
 		spmi->pci_function = device->path.pci.devfn & 0x7;
 	} else if (type != IPMI_INTERFACE_SSIF) {
@@ -1367,6 +1356,9 @@ static void acpi_create_dsdt(acpi_header_t *header, void *dsdt_file_arg)
 		if (CONFIG(CHROMEOS_NVS))
 			acpi_fill_cnvs();
 
+		for (const struct device *dev = all_devices; dev; dev = dev->next)
+			if (dev->ops && dev->ops->acpi_inject_dsdt)
+				dev->ops->acpi_inject_dsdt(dev);
 		current = (unsigned long)acpigen_get_current();
 		memcpy((char *)current,
 		       (char *)dsdt_file + sizeof(acpi_header_t),

src/acpi/acpi_dmar.c

@@ -26,7 +26,7 @@ void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags,
 	header->length = sizeof(acpi_dmar_t);
 	header->revision = get_acpi_table_revision(DMAR);
 
-	dmar->host_address_width = soc_phys_address_size() - 1;
+	dmar->host_address_width = cpu_phys_address_size() - 1;
 	dmar->flags = flags;
 
 	current = acpi_fill_dmar(current);

src/acpi/acpigen.c

@@ -868,17 +868,6 @@ void acpigen_write_BBN(uint8_t base_bus_number)
 	acpigen_pop_len();
 }
 
-void acpigen_write_SEG(uint8_t segment_group_number)
-{
-	/*
-	 * Method (_SEG, 0, NotSerialized) { Return (status) }
-	 */
-	acpigen_write_method("_SEG", 0);
-	acpigen_emit_byte(RETURN_OP);
-	acpigen_write_byte(segment_group_number);
-	acpigen_pop_len();
-}
-
 void acpigen_write_LPI_package(u64 level, const struct acpi_lpi_state *states, u16 nentries)
 {
 	/*

src/acpi/device.c

@@ -83,11 +83,11 @@ const char *acpi_device_name(const struct device *dev)
 	}
 
 	/* Walk up the tree to find if any parent can identify this device */
-	while (pdev->upstream) {
-		pdev = pdev->upstream->dev;
+	while (pdev->bus) {
+		pdev = pdev->bus->dev;
 		if (!pdev)
 			break;
-		if (is_root_device(pdev))
+		if (pdev->path.type == DEVICE_PATH_ROOT)
 			break;
 		if (pdev->ops && pdev->ops->acpi_name)
 			name = pdev->ops->acpi_name(dev);
@@ -147,15 +147,16 @@ static ssize_t acpi_device_path_fill(const struct device *dev, char *buf,
 		return cur;
 
 	/* Walk up the tree to the root device */
-	if (!is_root_device(dev) && dev->upstream && dev->upstream->dev)
-		next = acpi_device_path_fill(dev->upstream->dev, buf, buf_len, cur);
+	if (dev->path.type != DEVICE_PATH_ROOT && dev->bus && dev->bus->dev)
+		next = acpi_device_path_fill(dev->bus->dev, buf, buf_len, cur);
 	if (next < 0)
 		return next;
 
 	/* Fill in the path from the root device */
 	next += snprintf(buf + next, buf_len - next, "%s%s",
-			 (is_root_device(dev) || (strlen(name) == 0)) ?
-			 "" : ".", name);
+			 (dev->path.type == DEVICE_PATH_ROOT
+				|| (strlen(name) == 0)) ?
+					"" : ".", name);
 
 	return next;
 }
@@ -182,10 +183,10 @@ const char *acpi_device_scope(const struct device *dev)
 {
 	static char buf[DEVICE_PATH_MAX] = {};
 
-	if (!dev || !dev->upstream || !dev->upstream->dev)
+	if (!dev || !dev->bus || !dev->bus->dev)
 		return NULL;
 
-	if (acpi_device_path_fill(dev->upstream->dev, buf, sizeof(buf), 0) <= 0)
+	if (acpi_device_path_fill(dev->bus->dev, buf, sizeof(buf), 0) <= 0)
 		return NULL;
 
 	return buf;

src/arch/arm/Kconfig

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 config ARCH_ARM
 	bool
 

src/arch/arm/armv4/Kconfig

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 config ARCH_BOOTBLOCK_ARMV4
 	bool
 	select ARCH_BOOTBLOCK_ARM

src/arch/arm/armv7/Kconfig

@@ -1,5 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
 config ARCH_BOOTBLOCK_ARMV7
 	bool
 	select ARCH_BOOTBLOCK_ARM

src/arch/arm/include/arch/memlayout.h

@@ -20,7 +20,7 @@
 /* ARM stacks need 8-byte alignment and stay in one place through ramstage. */
 #define STACK(addr, size) \
 	REGION(stack, addr, size, 8) \
-	_ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.mk");
+	_ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc");
 
 #define DMA_COHERENT(addr, size) \
 	REGION(dma_coherent, addr, size, SUPERPAGE_SIZE) \