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278 Commits

Author SHA1 Message Date
Tim Crawford
4bfe54231a mb/system76: Enable S0ix support but prefer S3
Enable S0ix support but continue using S3 by default as it is not
tested on most boards. TGL-U boards continue to only use S0ix as S3 is
not supported on them.

Change-Id: Idc881d30009e3ef170e5430596652548aa434fda
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-12-20 15:58:19 -07:00
Tim Crawford
dfc6451830 soc/intel: Add config to use S3 over S0ix
When S0ix support is enabled it is always advertised to the OS that it
is the preferred suspend method via the FADT feature flag. This config
prevents the feature flag from being set, indicating to the OS that S3
suspend is the preferred sleep method.

Test: `/sys/power/mem_sleep` defaults to "deep" on system76/darp8.

Change-Id: Ife98166338c5457fb2c7dad81a30e54f487495f6
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-12-20 15:49:14 -07:00
Martin Roth
677d15e8a8 .editorconfig: Add indent style & size of 2 spaces for shell
This adds a default style for shell scripts. fmtsh now looks for this
when reformatting shell scripts.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I348f23badf302a48c851231a08c1ce4be94738a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78830
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20 22:30:33 +00:00
Felix Held
e4b080ee56 mb/amd/onyx_poc/devicetree: enable UART0
UART0 is routed to a USB-serial converter chip on the Onyx board, so
also enable this UART in the devicetree, so that the OS will be able to
use this UART.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b2577d799fd82a0aa0c9b01324930237e204aa0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-20 21:58:41 +00:00
Ivy Jian
17295c8288 mb/google/brox: Enable FSP UPD LpDdrDqDqsReTraining
FSP default value for LpDdrDqDqsReTraining is 1. For boards
that didn't set LpDdrDqDqsReTraining to any value, 0 was being
assigned and it caused black screen issue.

BUG=b:311450057
BRANCH=NONE
TEST=emerge-brox coreboot

Change-Id: I4a009076e50408a4f7ff16ddc96a0f2e47b09470
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79646
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-20 17:31:45 +00:00
Martin Roth
fab89b34e7 device/i2c_bus.c: Check pointer for NULL before using it
Found-by: Coverity Scan #1489753
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4f3794cf17875cdb35010c79a6537a4c13a18224
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-12-20 17:01:49 +00:00
Felix Held
9bcbdbf9e4 nb,sb/amd/pi/*/pci_devs: drop unused PCI device IDs
SATA_IDE_DEVID, AHCI_DEVID_MS and AHCI_DEVID_AMD are still kept even
though they're unused at the moment, but those might still be useful to
keep around, since the SATA controller can have different PCI device IDs
depending on in which mode it is in.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia05683b732d9748d9198225acaecbd4dc196733a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-20 14:40:46 +00:00
Eran Mitrani
2dfce0fd94 mb/google/rex/variants/deku: correct GPIO configuration
GPP_B02 and GPP_B03 were set incorrectly previously.
This CL corrects these settings according to schematics.

BUG=b:305793886
TEST=Built FW image correctly.

Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id62f15f7a77ac43c72cc6b2645816d6c87133a0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-20 14:14:02 +00:00
Tyler Wang
83775d151d mb/google/rex/var/karis: Add PANEL_PWRSEQ_EC_CONTROL in fw_config
Only EC will use field "PANEL_PWRSEQ_EC_CONTROL".
Add this field in coreboot for align fw_config settings.

BUG=b:314245238
TEST=emerge coreboot pass

Change-Id: Icecb44a338ddc28027e362332c6a69cc9fd268d5
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79570
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20 14:13:39 +00:00
Tyler Wang
a077ba53cb mb/google/rex/var/karis: Update fw_config FAN field
After confirm with thermal, only EC will reference FAN field in
fw_config.
Update the settings for align fw_config.

BUG=b:307822225
TEST=emerge coreboot pass

Change-Id: Id7c4cdba29c5500c06d0f2293495650bb14b9e9c
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79573
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
2023-12-20 14:13:24 +00:00
Varshit Pandya
0f666f7f78 soc/amd/genoa_poc: select DEFAULT_X2APIC
Allow SoC code to set LAPIC access mode to X2APIC

Change-Id: I208cca35c328e1566a57aaaa8ee7809e0760261c
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-12-20 14:12:24 +00:00
Varshit Pandya
f86375fd88 mb/amd/onyx_poc/devicetree: Enable UART1
UART1 is selected for debug uart in Kconfig, it also needs to enabled
in devicetree. With this serial output doesn't stop during the device
enable step.

TEST:Build onyx_poc board

Change-Id: I7c910301c6eca5d3057785607139ac03b344bc15
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-12-20 14:12:16 +00:00
Felix Singer
68a4c2ae8d util/{cbfstool,nvramtool}: Use same indent levels for switch/case
Use same indent levels for switch/case in order to comply with the
linter.

Change-Id: I2dd0c2ccc4f4ae7af7dd815723adf757244d2005
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-20 08:35:03 +00:00
Felix Singer
df98b8168f mainboard: Use same indent levels for switch/case
Use same indent levels for switch/case in order to comply with the
linter.

Change-Id: I602cf024ec84b15b783d36014c725826f9d6595e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79418
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20 08:34:50 +00:00
Felix Singer
6ff711c48f arch/riscv: Use same indent levels for switch/case
Use same indent levels for switch/case in order to comply with the
linter.

Change-Id: Icf41e823c42ffea7b73bdd9112081af4d1f94bc9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-20 08:34:26 +00:00
Pratikkumar Prajapati
9963aa359a commonlib/bsd: Tag CBMEM IDs deprecated for crashlog
These IDs are not used as crashlog data is not stored in CBMEM now.
(Ref CL: I43bb61485b77d786647900ca284b7f492f412aee
Title: soc/intel/common,mtl: Refactor BERT generation flow for crashlog)

BUG=b:298234592
TEST=Able to build REX.

Change-Id: Ie38571dece89a995d582099d34f0a1dd57cb936f
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-20 04:29:25 +00:00
Pratikkumar Prajapati
4db921317f soc/intel/common,mtl: Refactor BERT generation flow for crashlog
With earlier flow, a chunk of CBMEM region was allocated for each SRAM
e.g., PUNIT SRAM, SOC PMC SRAM and IOE PMC SRAM. Then entire SRAM
content was copied to dedicated CBMEM region. Later in acpi_bert.c, the
BERT table was getting created for each chunk of CBMEM. This flow was
not considering creating separate entries for each region of crashlog
records. It resulted in only the first entry getting decoded from each
SRAM.

New flow aims to fix this issue. With new flow, a simple singly linked
list is created to store each region of crashlog records from all
SRAMs. The crashlog data is not copied to CBMEM. The nodes are
allocated dynamically and then copied to ACPI BERT table and then
freed. This flow also makes the overall crashlog code much simpler.

BUG=b:298234592
TEST=With this change decoding crashlog show comprehensive details,
tested on REX.

Change-Id: I43bb61485b77d786647900ca284b7f492f412aee
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78257
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20 04:29:12 +00:00
Sukumar Ghorai
9b3c5afc00 acpi: Reduce wait interval in delay loop for sleep
The optimization of sleep time in acpi code includes reducing the sleep
duration and increasing the polling frequency within the acpi _ON/_OFF
method. StorageD3Enable is activated in Google/Rex, and this
optimization results in a saving of approximately 25ms in D3cold resume
time, reducing it from around 160ms to 135ms.

BUG=b:296206467
BRANCH=firmware-rex-15709.B

TEST=boot test verified on google/rex
     verified _ON/_OFF Method in SSDT.
     verifid kernel log in s0ix test -
          0000:00:06.0: PM: pci_pm_resume_noirq

Change-Id: I7ba960cb78b42ff0108a48f00206b6df0c78ce7a
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-12-20 04:28:27 +00:00
Subrata Banik
20629b4e65 mb/google/rex/var/screebo: Configure Acoustic noise mitigation
Enable Acoustic noise mitigation for google/screebo and set slew rate
to 1/8 for IA domain and ignore the slew rate for SA domain.

BUG=b:312405633,
TEST=Able to build and boot google/screebo.

Before:

[SPEW ]   AcousticNoiseMitigation : 0x0
[SPEW ]   FastPkgCRampDisable for Index = 0 : 0x0
[SPEW ]   SlowSlewRate for Index = 0 : 0x0

After:

[SPEW ]   AcousticNoiseMitigation : 0x1
[SPEW ]   FastPkgCRampDisable for Index = 0 : 0x1
[SPEW ]   SlowSlewRate for Index = 0 : 0x2

Change-Id: Ib86939ab48c2c6e7d0491d7c1cb4a2c7c6a1b568
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79323
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
2023-12-20 04:25:29 +00:00
Subrata Banik
26fdb062a7 soc/intel/meteorlake: Add Acoustic Noise Mitigation UPDs
This patch allows to override acoustic noise mitigation FSP UPDs:
- AcousticNoiseMitigation
- FastPkgCRampDisable
- SlowSlewRate

BUG=b:312405633
TEST=Able to override the acoustic noise UPDs.

Change-Id: I5295e6571121c92f363e6fd4bcb3c8335c4fedee
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79302
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-20 04:25:18 +00:00
Subrata Banik
93902072e5 vc/intel/fsp/mtl: Add UPDs for Acoustic Noise Mitigation
Acoustic noise in PCBs is a common problem and be caused by a variety
of factors, including:

Mechanical vibrations, Electromagnetic interference (EMI) and/or Thermal
expansion.

This patch adds the UPDs to FSPM header file for mitigating the acoustic
noise.

FSPM:
1. AcousticNoiseMitigation
2. FastPkgCRampDisable
3. SlowSlewRate

BUG=b:312405633
TEST=Able to build and boot google/rex.

Change-Id: Iea0bfa2f92bb82e722ffc1a0b2f1e374b32e4ebc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79301
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
2023-12-20 04:25:06 +00:00
Martin Roth
372503fba6 treewide: Use show_notices target for warnings
This updates all warnings currently being printed under the files_added
and build_complete targets to the show_notices target.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia14d790dd377f2892f047059b6d24e5b5c5ea823
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79423
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20 04:06:55 +00:00
Martin Roth
0cec2351e2 clang-format: Update configuration for version 16+
As we look at unifying the format of coreboot code (/src, excluding
src/vendorcode), we need a code-beautifier configuration that works
well with the coreboot style. This patch is an attempt to match the
existing code styles as much as possible.

There are going to be some trade-offs in any code formatter. Tables
which have been hand-formatted probably won't look as good. These
can be specifically marked to be excluded from the formatter, however
this should be the exception, not the rule.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I70341d77e167c145f447594b6b0bef628cea83c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78832
Reviewed-by: Zebreus <lennarteichhorn@googlemail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20 03:44:23 +00:00
Angel Pons
b44923969c sb/intel/bd82x6x/pch.c: Extract common functions
PCH identification functions and `pch_iobp_update` are used in multiple
stages. Move them out of `pch.c` to drop some ugly preprocessor usage.
Subsequent commits will use `pch_iobp_update` in romstage as well.

Change-Id: I8d33338a4f74fd03c8f99f8fcece99b63c28adab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79624
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-19 15:47:40 +00:00
Kun Liu
f733703a61 mb/google/rex/var/screebo: Add delay 1ms after Main 3V3
when S0ix returns S0, PERST needs to delay until
Main 3V3 is stable and then pull up

BUG=b:313976507
TEST=emerge-rex coreboot,measurement waveform verify pass

Change-Id: I33a86e52fab3c5c8cba6ebed0cbdd1b88b6538b0
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79320
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-19 13:35:44 +00:00
Weimin Wu
b8fd150da6 mb/google/nissa/var/anraggar: Use GPP_D15 to control AVDD and AFVDD
For EVT SCH:

1. Use GPP_D15 to control AVDD and AFVDD simultaneously for MIPI Camera.
2. Delay reset for 5ms when device power on.

BUG=b:312663347
TEST=1. Google Camera app working
     2. Passed EA verified

Change-Id: I880fb309fcef006090e2849fa6c3a0d472851851
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-19 13:35:18 +00:00
Nico Huber
0f98655b37 device: Drop MULTIPLE_VGA_ADAPTERS Kconfig
This option is nowhere selected and there is only a single case left
where it's used. Guarding the check in pci_rom_load() seems like a
bad idea: As the code would be copying all VGA ROMs to the same
location, it would be only working by chance (if the last encoun-
tered ROM is the right one). Hence, drop the guard and always check
for the correct device.

Change-Id: Ib283bf0a65367b99099a3bfcbd27585d44235eb9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79596
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-19 13:16:08 +00:00
Felix Held
df4955297f nb/amd/pi: drop HW_MEM_HOLE_SIZEK Kconfig option
There's neither need to remove get_hw_mem_hole_info from the code if the
Kconfig option was set to 0 nor the actual value didn't make any
difference in the behavior of the code: When node_id has still its
initial value of -1, domain_read_resources won't use the value of
hole_startk, and when node_id is set to 0, get_hw_mem_hole_info also
sets hole_startk to the actual value that then gets used by
domain_read_resources.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieffab695a3151ed7f6bf9d6c880bbb43eecf7893
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79609
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-19 13:15:39 +00:00
Felix Held
7a83ab7612 nb/amd/pi/00730F01/northbridge: use devicetree device pointers
This APU is always a single-node, so the nodeid parameter of
get_node_pci is always 0. Since this SoC has a chipset devicetree, we
can just use DEV_PTR(ht_X) instead of the pcidev_on_root call.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1bf9d214b4c2e5d995976fb79fef6fe43a6e9fa0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79608
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-19 13:15:21 +00:00
Felix Held
3f234f85e2 nb/amd/pi/00730F01/northbridge: assume that there's DRAM
This APU is always a single-node and since we're in ramstage when
domain_read_resources gets called, there's DRAM on this node, so no need
to check for this. To be extra sure, also initialize basek and limitk
before calling get_dram_base_limit with pointers to those as arguments.
This won't be necessary for the code to work as intended, but will
probably keep the compiler from complaining. Also move the declaration
of basek, limitk and sizek to the beginning of the function.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4ef8011eb57b16218b8f5fea295900b855c3014b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79611
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-19 13:14:49 +00:00
Felix Held
dcbb1e8b61 nb/amd/pi/00730F01/northbridge: rework idx in domain_read_resources
Start with the resource index 0 and increment it after reporting each
resource.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6fb59ff3d371b744b53093d17392d1c3510bef82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-12-19 13:14:27 +00:00
Felix Held
3eaa850c6a nb/amd/pi/00730F01/northbridge: drop nodeid from get_dram_base_limit
This APU is always a single-node and also only has one DRAM controller,
so there is only one valid DRAM base and limit register. It's also worth
mentioning that the assumption made in get_dram_base_limit that the n-th
node is using the n-tn DRAM range register was valid for K8, but not
necessarily on newer generations than that.

TEST=PC Engines APU2 still boots and doesn't show any new problems

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0529c66e8d0e6c8eb42eec2c6d9d2e892287865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79607
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-19 13:14:00 +00:00
Felix Held
a880720ee1 nb/amd/pi/00730F01/northbridge: rework hw_mem_hole_info
This APU is always a single-node and also only has one DRAM controller,
so we don't need to loop over the different nodes to find the memory
hole below 4GB. We also don't need to check for the special case where
the memory hole is non-DRAM address space between the parts of the
address space decoded by different DRAM controllers.

TEST=PC Engines APU2 still boots and doesn't show any new problems

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9793d911d2d496be49168c06d83ceb802bc2b647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-12-19 13:13:46 +00:00
Felix Held
ce8dfc51ec nb/amd/pi/00730F01/northbridge: simplify domain_read_resources
This APU is always a single-node, so domain_read_resources only needs to
handle exactly one node and doesn't need to loop over the nodes.

TEST=PC Engines APU2 still boots and doesn't show any new problems

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4218077cb4e11b762ce0e8694a97bdec33eaa056
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-19 13:13:22 +00:00
Felix Held
606e5636c2 nb/amd/pi/00730F01/northbridge: remove get_fx_devs
This SoC only supports a single-node configuration, so all the code
related to multi-node support can be removed. In this commit only the
get_fx_devs function and related code are removed for better
reviewability. In f1_write_config32 it's no longer needed to loop over
the different devices of the different nodes, so only a single PCI
config space write remains.

TEST=PC Engines APU2 still boots and doesn't show any new problems

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5dc7324d3fcd0d07ac7a3a246a740fd9e91c3840
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79604
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-19 13:12:48 +00:00
Felix Held
aaceeae95a nb/amd/pi/00730F01/northbridge: always return 1 in get_node_nums
This APU is always a single-node system and bits 4..6 of the node ID
register D18F0x60 are also marked as reserved in BKDG #52740 Rev 3.05.
On an APU2 board with quad-core APU, this register reads back 0x00030000
which results in a value of 1 to be returned from get_node_nums, so this
patch doesn't change behavior, but stops using reserved bits.

TEST=PC Engines APU2 still boots and doesn't show any new problems

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I65ed1124c0ca8e7eba54ff53dc626d35cd5e2e58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79603
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-12-19 13:12:32 +00:00
Felix Held
b986e21a6d nb/amd/pi/00730F01/northbridge: drop create_vga_resource
This system only has one northbridge and amd_initcpuio has already set
up the routing of the legacy VGA IO and MMIO ranges to it. Since only
the pci_dev_set_resources call remains in nb_set_resources, use
pci_dev_set_resources directly as set_resources function.

TEST=PC Engines APU2 still boots and doesn't show any new problems

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib3835db9fd83221ac2b8e34d998f938812d24413
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-19 13:12:12 +00:00
Felix Held
dda7793e53 nb/amd/pi/00730F01: assign IOMMU ops in chipset devicetree
Since the IOMMU is always function 2 of device 0 on bus 0, the device
operations can be statically assigned in the devicetree and there's no
need to bind the IOMMU device operations to the PCI device during
runtime via a list of PCI IDs.

TEST=PC Engines APU2 still boots and doesn't show any new problems

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I84e949500ee86e0fcb2d15791502f5e3e7127703
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79105
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-12-19 13:11:53 +00:00
Felix Held
7b9c647217 nb/amd/pi/00730F01: assign northbridge ops in chipset devicetree
Since the northbridge is always function 0 of device 0 on bus 0, the
device operations can be statically assigned in the devicetree and
there's no need to bind the northbridge device operations to the PCI
device during runtime via a list of PCI IDs.

TEST=PC Engines APU2 still boots and doesn't show any new problems

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia7faaa468ff77e05c378c5555622c3584cfe3f81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-12-19 13:11:43 +00:00
Eran Mitrani
83e9f04802 mb/google/hatch/var/jinlon: Increase reset deassert delay to 4 ms
With 1ms delay, reset is de-asserted too soon, before power is fully
up, causing a glitch to the reset signal. The issue is resolved with
4ms delay.

TEST=tested on google/jinlon device and observed the issue is resolved.
BUG=b:260253945

Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I4efe916824cc193a7c2db7599b37f0d4de40bfce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79474
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2023-12-19 04:19:21 +00:00
Maximilian Brune
7bcf4ae4d2 drivers/spi: Add ISSI IS25WP256D flash
datasheet: IS25WP256D Rev A13 (2023-08-03)

tested:
boot SiFive Hifive Unmatched board

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I655776258cbcf464becf38cbb5045cda5bca711c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-18 20:27:52 +00:00
Tyler Wang
b24eadb973 mb/google/rex/var/karis: Enable audio BT offload
BUG=b:312099281
TEST=Build and boot to Karis. Verify the config from serial logs.

w/o this CL -
```
[SPEW ]  ------------------ CNVi Config ------------------
[SPEW ]  CNVi Mode        = 1
[SPEW ]  Wi-Fi Core       = 1
[SPEW ]  BT Core          = 1
[SPEW ]  BT Audio Offload = 0
[SPEW ]  BT Interface     = 1
```

w/ this CL -
```
[SPEW ]  ------------------ CNVi Config ------------------
[SPEW ]  CNVi Mode        = 1
[SPEW ]  Wi-Fi Core       = 1
[SPEW ]  BT Core          = 1
[SPEW ]  BT Audio Offload = 1
[SPEW ]  BT Interface     = 1
```

Change-Id: Icd2c42261fdcfa5aac17be28fde3804348ddf9b4
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-18 09:45:04 +00:00
Subrata Banik
8cf64473cb soc/intel/mtl: Adaptively disable 3-strike error for QS silicon
This patch provides a way to mask the 3-strike error on Intel
Meteor Lake SoC platform across pre-prod and prod SoC.

This patch decouples MSR selection for 3-strike error disablement, ensuring compatibility across SoC types.

Without the correct MSR been programmed the SoC platform is unable to disable 3-strike error.

BUG=b:314883362
TEST=Disable the 3-strike on google/screebo with QS silicon.

Change-Id: I5363102deea67c44c9433a3f66c92badb0d0f182
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79473
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-18 08:23:39 +00:00
Patrick Georgi
ed0647a850 src/lib: Add memory/time saving special case for ramstage caching
When caching the ramstage for suspend/resume, we copy the entire image
as it resides in RAM. The last part of that, CONFIG_HEAP_SIZE bytes, is
the heap that will be reinitialized when the ramstage is started again.

As such, copying doesn't make sense and complicates HEAP_SIZE
configuration (because it needs to fit the space-constrained cache
location) and costs time and space. Therefore, skip the heap.

Side notes:
- When building with ASAN, program.ld indicates that it will allocate
  some more space after the heap. This is not a problem, we just copy
  an ASAN-sized copy of the heap.
- Heap use is managed in src/lib/malloc with statically allocated
  variables. Because ramstage is cached before it's executed, these
  values will be reset to their compile-time default values, too.

Change-Id: I6553dc8b758196f2476af2e692c0421d0fa2b98e
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79525
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-18 08:13:12 +00:00
Kulkarni, Srinivas
520ca9a518 vc/intel/raptorlake: Update header files from 4301_01 to 4435_00
Update header files for FSP for Raptor Lake platform to version 4435_00,
previous version being 4301_01.

FSPM:
1. Options changed for Ppr Enable
2. Add 'Ppr Run Once' and 'Post Package Repair' UPD's

FSPS:
1. Add 'CpuPcieRpTestForceLtrOverride' UPD

MemInfoHob:
1. Structure updated

BUG=b:315234533
Kit: https://www.intel.com/content/www/us/en/secure/design/confidential/
software-kits/kit-details.html?kitId=793230

Cq-Depend: chrome-internal:6786881, chrome-internal:6787635
Cq-Depend: chrome-internal:6719974, chromium:5125983
Change-Id: I65b8a4b6c72f7ae3fff1ee6d073311d154cd6b69
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-17 20:14:45 +00:00
Martin Roth
224098dffd Makefile.inc: Update end-of-build targets
The end-of-build targets weren't very granular previously, so warnings
could be lost instead of being printed at the end of the build.

This separates the end-of-build targets into 4 different groups, in this
order:
- build_complete: The coreboot build itself is done
- files_added: All files have been added to CBFS
- show_coreboot: Display any normal coreboot build messages
- show_notices: Display any warnings or notes

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia67446f164b8e66415a1a8c196999316fdf39f1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79382
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-12-17 19:32:00 +00:00
Felix Held
6a3d64ab1c nb,sb/amd/pi/*/pci_devs: drop unused BUS0 define
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5ce8ac00c015e34375c6b3c70496c97e2fe455bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-12-17 18:51:08 +00:00
Weimin Wu
9b2d96eee2 mb/google/nissa/var/anraggar: Disable SDCard controller
1. Anraggar doesn't support SDCard, so disable SDCard contorller.
2. Not disabling it will cause can't enter S0ix on first suspend.

BUG=b:313585586
TEST=1. check lspci
     2. can enter S0ix on first suspend

Change-Id: Ie4747d9c5d6ae93d29ef78b629855e0dd320c4db
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-17 18:45:18 +00:00
Matt DeVillier
34de4d5c65 mb/google/skyrim: Add and use APCB configuration data
This file is identical to the copy currently found in the blobs
repository; it is simply being relocated for consistency and since it
does not need to be in an external repo.

BUG=none
TEST=build/boot skyrim

Change-Id: I352f58e0d3965356f3282a2653c6c11b44853857
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-12-17 18:44:40 +00:00
Matt DeVillier
eb62c4ba40 mb/google/guybrush: Add and use APCB configuration data
This file is identical to the copy currently found in the blobs
repository; it is simply being relocated for consistency and since it
does not need to be in an external repo.

BUG=none
TEST=build/boot guybrush

Change-Id: Ice4cbaccca13e9c4ae246fdcde5c89aa2086f1e1
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-12-17 18:44:20 +00:00
Matt DeVillier
95d05d8301 mb/google/zork: Add and use APCB configuration data
This file is identical to the copy currently found in the amd_blobs
repository; it is simply being relocated since it is mainboard specific
and does not need to be in an external repo.

BUG=none
TEST=build/boot morphius

Change-Id: Ia78fcd065fbf4d5ba6ec4edc3f8f937badf66ecc
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79591
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-17 18:43:57 +00:00
Matt DeVillier
17092b3646 README.md: Add .apcb files under the uncopyrightable files section
.apcb files are binary configuration data for AMD firmware binaries
created by another tool/script, nothing in them is copyrightable.

Change-Id: I254c12e65b118ef074deea983a853850a8cad77c
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-12-17 18:43:24 +00:00
Matt DeVillier
024c5c908b util/lint: Exclude .apcb files from various checks
.apcb files are binary configuration data and not human readable;
exclude them from license, newline, and whitespace checks.

Change-Id: Idc1ddd5067cb97ef8b5758a0b8bf040d1e421871
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-12-17 18:43:07 +00:00
Shelley Chen
b6053bc1fc mb/google/brox: Disable EC/PD SW Sync
For initial debugging, we want to disable SW syncing.  Will re-enable
in the future.

BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
     run gbb_utility --get --flags <image>
     make sure that it returns 0xa39

Change-Id: I865e9585ab37d1328a0ff54c6343cdad2c02220c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79569
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
2023-12-17 04:28:09 +00:00
Riku Viitanen
5eb95ee391 sio/nuvoton/npcd378: Fix ACPI errors
In commit 0a0945c6a2 (sio/nuvoton/npcd378: Use acpi_device_path_join),
some oversights were made. Instances of "strconcat(scope, ..." should be
replaced with "..._join(dev->bus->dev, ..." instead of "..._join(dev, ...".

On HP 8200 USDT, this fixes ACPI error like this on resume from S3:
    ACPI BIOS Error (bug): Could not resolve symbol [\_SB.PCI0.LPCB.SIO0.L040.RMFG], AE_NOT_FOUND (20230628/psargs-330)
    ACPI Error: Aborting method \_GPE._L08 due to previous error (AE_NOT_FOUND) (20230628/psparse-529)
    ACPI Error: AE_NOT_FOUND, while evaluating GPE method [_L08] (20230628/evgpe-511)

RMFG seems to be a typo of PMFG made in that same commit.

Change-Id: Ifffa7ad72cfdb644c8b5147132a5fd56511ed33b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-12-16 22:58:35 +00:00
Varshit Pandya
b0d0de2ba6 mb/amd/onyx: rename to onyx_poc
Even though this mainboard is called 'Onyx', the openSIL implementation
and the corresponding coreboot integration is only a proof of concept
that isn't fully featured, has known limitations and bugs, and is not
meant for or ready to being productized. Adding the proof of concept
suffix to the name should point this out clearly enough so that no
potential customer could infer that this might be a fully functional
and supported implementation which it is not.

Change-Id: I157a8fffdc2a8543465fe8d444ac87f3f417389f
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77896
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-16 20:15:02 +00:00
Felix Held
9314bb6f0a vc/amd/opensil: add _POC suffix to SOC_AMD_OPENSIL_GENOA
The openSIL code for the Genoa SoC is only a proof of concept, so change
the name of the Kconfig option to include this code in the build from
SOC_AMD_OPENSIL_GENOA to SOC_AMD_OPENSIL_GENOA_POC to clarify that this
is code that isn't intended or ready to be productized.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If91cdaa7c324426964bba2de2109b6c38482fab8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79574
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-16 20:14:47 +00:00
Felix Held
d123f8d871 soc/amd/genoa: rename to genoa_poc
Even though this SoC is called 'Genoa', the openSIL implementation and
the corresponding coreboot integration is only a proof of concept that
isn't fully featured, has known limitations and bugs, and is not meant
for or ready to being productized. Adding the proof of concept suffix to
the name should point this out clearly enough so that no potential
customer could infer that this might be a fully functional and supported
implementation which it is not.

Change-Id: Ia459b1e007dcfd8e8710c12e252b2f9a4ae19b72
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77894
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-16 20:14:34 +00:00
Sukumar Ghorai
1c295092d6 mb/google/{rex,ovis}: Decrease EPP to 45% for MTL performance expectation
The default EPP is set at 50%, which is deemed insufficiently
aggressive for meeting the MTL performance expectations in
balance_performance mode.

    # cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference
    balance_performance
    # iotools rdmsr 0 0x774
    0x0000000080003f06

EPP=45% is giving the required performance in MTL.
    # iotools rdmsr 0 0x774
    0x0000000073003d06

NOTE: Kernel changes are necessary to ensure that the EPP (Energy Performance Preference) configured in the BIOS is not overwritten: https://patchwork.kernel.org/patch/13461932

BUG=b:314275133
TEST=Build and boot.

Change-Id: I1953994cdb4e9363fdd4b4728e3e5236276c06c8
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79386
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-16 15:34:12 +00:00
Dtrain Hsu
0c8d64cc63 mb/google/nissa/var/uldren: Reduce boot time for non-touchscreen sku
Non-touchscreen sku will set related GPIOs to NC. If touchscreen enabled
in overridetree for non-touchscreen sku, the boot time will be 6-7s. Set
touchscreen probed to TOUCHSCREEN_UNKNOWN for reduce boot time from 6-7s
to under 1s.

BUG=b:316434359
BRANCH=firmware-nissa-15217.B
TEST=Boot time (cbmem -t) from 6,460,972 to 922,844

Change-Id: I016ce762f726b7624bd060284f74f0992cb129b6
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-12-16 13:48:31 +00:00
Felix Held
f0c67127a9 soc/amd/genoa/fch: add fch_init_acpi_ports
Make sure that the APMC SMI command IO port is configured to what
coreboot expects and enable the SMI generation for the APMC SMI command
port.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie4fc259dea125a16556a01b80a3d5e6fb476044a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79531
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-16 00:41:25 +00:00
Arthur Heymans
7f19d20594 soc/amd/stoney/northbridge: Remove dead code
All the resource on the host bridge are fixed resources and therefore
have the IORESOURCE_STORED flag set, so the body of this function which
configures IO or MEM ranges is never reached.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I1839f030a4a365e5bc1cdaa3cf37cdf9ca382ff8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79385
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-15 21:57:14 +00:00
Marek Maslanka
017003cbd0 acpi: Add support for WDAT table
This commit lays the groundwork for implementing the ACPI WDAT (Watchdog
Action Table) table specification. The WDAT is a special ACPI table
introduced by Microsoft that describes the watchdog for the OS.

Platforms that need to implement the WDAT table must describe the
hardware watchdog management operations as described in the
specification. See “Links to ACPI-Related Documents”
(http://uefi.org/acpi) under the heading “Watchdog Action Table”.

BUG=b:314260167
TEST=Mock the acpi_soc_fill_wdat function for a specific platform/soc
and enable ACPI_WDAT_WDT in the kconfig. Check if the build passes
successfully.

Change-Id: Ieb82d1f69b2b7fffacfd2928bc71f8ff10498074
Signed-off-by: Marek Maslanka <mmaslanka@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
2023-12-15 19:08:45 +00:00
Bora Guvendik
d9c347fb8b mb/google/brya: Enable FSP UPD LpDdrDqDqsReTraining
FSP default value for LpDdrDqDqsReTraining is 1. For boards
that didn't set LpDdrDqDqsReTraining to any value, 0 was being
assigned and it caused black screen issue.

BUG=b:302465393
TEST=Boot to OS with debug FSP, check LpDdrDqDqsReTraining = 1

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I301a6e43f2944ffbc63431393378ab8b23450032
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-15 17:36:41 +00:00
Subrata Banik
0b7388f050 soc/intel/cmn/cpu: Introduce API to disable signaling 3-strike event
This patch introduces a new API to disable signaling the 3-strike event
on Intel Meteor Lake C0 (QS) stepping and subsequent SoCs. This is
necessary because the existing event handling mechanism is incompatible
with the new hardware design.

Disabling the 3-strike event registration prevents the 3-strike count
from increasing, which addresses bug b:314883362. This issue can potentially lead to system instability.

BUG=b:314883362
TEST=disabling the 3-strike event on a Google Screebo system with QS silicon.

Change-Id: I15bd5a93da34d7f2a127c21c4cd8b5952926bccf
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79472
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-15 13:22:53 +00:00
Terry Cheong
053c901548 mb/google: Reduce DA7219 mic detect threshold to 200ohm
The original DA7219 is designed to use a 500ohm mic detection
threshold. Some headset mics (e.g. Logitech H111) have a lower DC impedance that is lower than the threshold and thus cannot be
detected. Lower the threshold to 200ohm to match the new default
value provided by Renasas as in https://patchwork.kernel.org/project/alsa-devel/patch/20231201042933.26392-1-David.Rau.opensource@dm.renesas.com/ to support such headsets.

BUG=b:314062160,b:308207450

Change-Id: I6415e84a4622e0c61bc74b94536fe734048a043f
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-15 11:27:34 +00:00
Arthur Heymans
77f1062e77 rules.h: Clean up ENV_HAS_HEAP_SECTION
Commit ea2c1d3 "cpu/x86/smm: Remove heap" removed the ability to use
heap in SMM, but the ENV_HAS_HEAP_SECTION macro was not updated
appropriately.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5ae4a63a7bd1b27ae3e9c757aa8557f329aad0f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2023-12-15 09:41:18 +00:00
Felix Held
c7be0781ce vc/amd: use 'openSIL' spelling in comments & help text
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I176182180f508a180726fca60064b16fad80e9d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-15 09:31:36 +00:00
Felix Held
b154949004 soc/amd: drop fill_fadt_extended_pm_regs
Call fill_fadt_extended_pm_io directly from the SoC's acpi_fill_fadt
functions instead of calling fill_fadt_extended_pm_regs that only calls
fill_fadt_extended_pm_io.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I442bc2801cf74c1d836d3b0d88f281bceb5122b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79529
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-15 09:31:22 +00:00
Arthur Heymans
b2ea2f29b8 soc/amd/genoa: Hook up BERT
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ie21bf8d436de19c23ae2176bf8d061564cd5b9cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-15 09:30:51 +00:00
Felix Held
b499c1f014 soc/amd/genoa: Hook up IVRS generation
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I0a6eaf43ab6da4bb4a0cc0bbefb5b75c206348f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-12-15 09:30:20 +00:00
Felix Held
80434a6984 soc/amd/genoa: configure FCH IRQ mapping
Add the code to configure the FCH IRQ mapping registers and provide the
IRQ name strings for each FCH IRQ mapping configuration register.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I282ae35ebc4d7754121ce4544b782e3cbe7e2256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-15 09:30:05 +00:00
Morris Hsu
6a57210686 mb/google/brya/var/dochi: Enable LpDdrDqDqsReTraining
FSP default value for LpDdrDqDqsReTraining is 1. For boards
that didn't set LpDdrDqDqsReTraining to any value, 0 was being
assigned and it caused black screen issue.

BUG=b:302465393,b:315739133
TEST=Boot to OS with debug FSP, check LpDdrDqDqsReTraining = 1

Change-Id: I5d61301fddac6630bb1c48e992dd76e5cf02a272
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79533
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-15 01:59:55 +00:00
Naresh Solanki
933d2b0f13 lib: ramdetect: Add Kconfig PROBE_RAM
Previously ramdetect.c was compiled only for VENDOR_EMULATION.
Hence add Kconfig option PROBE_RAM which allows board outside
the scope of VENDOR_EMULATION to select and utilize  probe_ram
function to runtime detect usable RAM in emulation environment.

PROBE_RAM is default selected if VENDOR_EMULATION is set so
that existing boards under VENDOR_EMULATION scope are not
affected.

Other boards can explicitly select PROBE_RAM to use probe_ram.

TEST=Build mb/arm/rdn2 with PROBE_RAM selected & make sure
there is no any error.
Also checked qemu-aarch64 build to make sure build is success.

Change-Id: Id909ddaee6958cfa8a6c263a11f9a90d94710aa7
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-14 14:21:33 +00:00
Felix Held
18c83e1a94 mb/amd/onyx/mainboard: add FCH IRQ mapping table
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iab640551d6dd246884802ced948ff8c359d922a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79470
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14 13:10:08 +00:00
Kun Liu
d3ff66d1fb mb/google/rex/var/screebo: Change GPP_B14 from UP_20K to NONE
Change GPP_B14 from UP_20K to NONE for compatible
with DVT1 and DVT2 board

BUG=b:272447747
TEST=enable usb OC2 function to ensure USBA work normal

Change-Id: Ib7720980335660f423b3a74199ceedc113ec70df
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79431
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14 13:08:59 +00:00
Jakub Czapiga
2d1b5c21f6 MAINTAINERS: Update Jakub's email address
jacz@semihalf.com is no longer available, czapiga@google.com should be
used instead.

Change-Id: I228b34c961ccf1546103f105276a75409825a432
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79438
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14 13:08:18 +00:00
Weimin Wu
5ba045c715 mb/google/nissa/var/anraggar: Update DTT settings for thermal control
Update DTT settings based on the suggestion of the thermal.

BUG=b:313833488
TEST=emerge-nissa coreboot

Change-Id: I2296990062cadc05202e3d1ab90af04234bda885
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14 13:07:55 +00:00
Weimin Wu
6215ef47cd mb/google/nissa/var/anraggar: Enable USB3 Port3 for WWAN (LTE)
1. Ref to SCH, LTE use USB3 Port3, enable it.
2. Explicitly define the use of USB3 Port1 & USB3 Port2.

BUG=b:315061146
TEST=can pass PCIe Hardware Compliance Test

Change-Id: I03d6925020012fa740bbd0168a2f5b02ea6763b4
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14 13:07:13 +00:00
Weimin Wu
133e3ee661 mb/google/nissa/var/anraggar: Change code style for register usb2_ports
Change code style to be compatible with Nissa's format:

register "option" = "{
    [0] = value /* comment */
    ...
}"

to

register "option[0]" = "value" /* comment */

BUG=none
TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar

Change-Id: I60659bd44813173f9b984216473a0919c5f331b8
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14 13:06:13 +00:00
Felix Held
020d4b605e soc/amd/genoa/domain: generate SSDT entries for domains
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iadc37f2724a9be43cad1f1934403ebabd5cca245
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-14 13:05:41 +00:00
Felix Held
d1065a3e64 soc/amd/genoa: Add basic ACPI support
- DSDT
- MADT
- SSDT CPUs

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0c86694ae83e9e6aa06a50a8a35bf2b24bc8ab65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76530
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14 13:04:28 +00:00
Felix Held
3d3e1cf060 vendorcode/amd/opensil/genoa_poc: add opensil_fill_fadt_io_ports
Add the opensil_fill_fadt_io_ports function to fill in the ACPI I/O
ports in FADT that openSIL configured.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I154a162cc8e048cadab693c0755e96c71a62983c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76529
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14 13:03:17 +00:00
Yi Chou
27f888cda1 Update vboot submodule to upstream main
Updating from commit id db533497:
2023-12-05 20:09:44 +0000 - (host/lib/pkcs11: Remove superfluous 'nss' directory from include paths)

to commit id c0cb4bfa:
2023-12-08 09:14:32 +0000 - (signer: sign_android_image.sh should die when image repacking fails)

This brings in 3 new commits:
c0cb4bfa signer: sign_android_image.sh should die when image repacking fails
30e37712 tlcl: Add `TlclCreatePrimary()` support
12fa13e3 2api: Add firmware & kernel PCR support

Change-Id: I354c1d07c3b506069d5b64bc2fc476dadc36e0e2
Signed-off-by: Yi Chou <yich@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79484
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14 08:29:08 +00:00
Kulkarni, Srinivas
7c6f1d570c vc/intel/raptorlake: Updating the FSP v4301.01 headers to Standard path
Move the existing FSP 4301.01 headers for Raptor Lake out of
subdirectory called 43101.01 to follow standard process.

Change-Id: I710f373acd37e9e0f8b50084a1a7e9fbda816e8c
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-14 03:23:31 +00:00
Felix Held
fa3f1171ef soc/amd/genoa/acpi: update soc.asl
Add the missing parts in soc.asl. Compared to earlier versions of this,
the includes related to S0i3 and DPTC were removed.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I89ecf469e44ca2a3b35c9fcf57c008ff29e7b9bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79468
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13 20:39:24 +00:00
Felix Held
c8dfd6d935 soc/amd/genoa/acpi/soc: add root bridges to DSDT
Add the 4 root bridge devices using the ROOT_BRIDGE macro.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If405a90981e5c1fea51935c520800a245473317e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79467
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13 20:32:11 +00:00
Felix Held
7949a1b73b mb/amd/onyx/dsdt: include acpi/dsdt_top.asl
acpi/dsdt_top.asl provides some common functionality and needs to be
included at the beginning of the DSDT.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia7b5ddce110b35ed65c6df6cc42995abe93a3ffc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79466
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-13 20:31:27 +00:00
Felix Held
bff9823700 soc/amd/genoa/acpi: include globalnvs.asl in SoC code
Instead of including globalnvs.asl in the mainboard's dsdt.asl, include
it in Genoa's soc.asl. This aligns Genoa with Cezanne and newer and also
moves more SoC-common code to the SoC folder.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie0e3299a95e007188a4d9de824cfff8d25a778be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79465
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13 20:30:32 +00:00
Felix Held
dd032e0c41 soc/amd/genoa: set up the non-FCH IOAPICs
Apart from the IOAPIC in the FCH which is handled by amd_lpc_ops,
there's one IOAPIC per PCI root which also needs to be initialized.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I38af5a194062e714827852e95f4e29b45311e517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-13 20:29:17 +00:00
Felix Held
0fe8643465 soc/amd/genoa/domain: fix indentation in genoa_pci_domain_ops
There's no need for the two additional spaces between the tabs and the
'='.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic6824e8c7ee870fc44c5efd70cc05677e9948a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79464
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-13 20:28:10 +00:00
Felix Held
d01826843e soc/amd/genoa/chip: add init & final functions and chip name
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I00a567f417b1e22167923fc3193583138718dbbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79463
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13 20:26:51 +00:00
Felix Held
4e4938bcb9 soc/amd/genoa/include/amd_pci_int_defs: rename PIRQ index 0x60 and 0x61
PIRQ_SCI is already defined as 0x10 and this also brings the definitions
more in line with Phoenix.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib2ab954b379d2edd0167d7fb229557600cbc4e48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-13 20:25:43 +00:00
Patrick Georgi
1d029b40c9 lib/jpeg: Replace decoder with Wuffs' implementation
To quote its repo[0]: Wuffs is a memory-safe programming language (and
a standard library written in that language) for Wrangling Untrusted
File Formats Safely. Wrangling includes parsing, decoding and encoding.

It compiles its library, written in its own language, to a C/C++ source
file that can then be used independently without needing support for
the language. That library is now imported to src/vendorcode/wuffs/.

This change modifies our linters to ignore that directory because
it's supposed to contain the wuffs compiler's result verbatim.

Nigel Tao provided an initial wrapper around wuffs' jpeg decoder
that implements our JPEG API. I further changed it a bit regarding
data placement, dropped stuff from our API that wasn't ever used,
or isn't used anymore, and generally made it fit coreboot a bit
better. Features are Nigel's, bugs are mine.

This commit also adapts our jpeg fuzz test to work with the modified
API. After limiting it to deal only with approximately screen sized
inputs, it fuzzed for 25 hours CPU time without a single hang or
crash. This is a notable improvement over running the test with our
old decoder which crashes within a minute.

Finally, I tried the new parser with a pretty-much-random JPEG file
I got from the internet, and it just showed it (once the resolution
matched), which is also a notable improvement over the old decoder
which is very particular about the subset of JPEG it supports.

In terms of code size, a QEmu build's ramstage increases
from 128060 bytes decompressed (64121 bytes after LZMA)
  to 172304 bytes decompressed (82734 bytes after LZMA).

[0] https://github.com/google/wuffs

Change-Id: If8fa7da69da1ad412f27c2c5e882393c7739bc82
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Based-on-work-by: Nigel Tao <nigeltao@golang.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78271
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13 16:17:34 +00:00
Naresh Solanki
5466261019 drivers/uart/pl011.c Perform basic UART init
Configure UART baud rate, Line Control register as 8n1 with FIFO
enable and enable UART TX and RX.

Change-Id: I090344a20430dc370a0b93ff7fbbae54111fae24
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79406
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-13 14:27:09 +00:00
Martin Roth
3e25f85d68 drivers/ipmi to lib: Fix misspellings & capitalization issues
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I926ec4c1c00339209ef656995031026935e52558
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77637
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13 10:42:30 +00:00
Ivy Jian
3933ed5e5a mb/google/brox: Generate RAM ID for supported memory part
Add the MICRON MT62F1G32D2DS-023 WT:B RAM part for brox:

DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B       0 (0000)
H9JCNNNBK3MLYR-N6E             0 (0000)
MT62F1G32D4DR-031 WT:B         1 (0001)
MT62F1G32D2DS-023 WT:B         2 (0010)

BUG=b:311450057,b:315913909
BRANCH=None
TEST=Run part_id_gen tool without any errors
Change-Id: Id120a5eb311d8299a8e59d2c1658fe0742e93934
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-13 00:24:42 +00:00
Felix Held
919801e5dc soc/amd/genoa/chipset.cb: add missing non-transparent PCI bridges
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d5efa948e8bd993ca4b5af80f664db687b8a766
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-12 18:32:56 +00:00
Felix Held
c3d909dbb7 mb/amd/onyx/devicetree: enable more PCI devices
Early versions of CB:76519 had more devices enabled in the chipset
devicetree which shouldn't necessarily be enabled in the chipset
devicetree. Enable most of those in the Onyx mainboard's devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieeb96755a007a5ca70e4c31df09325835bb8ef47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-12 18:32:01 +00:00
Felix Held
5aaaee3486 soc/amd/genoa/chipset.cb: disable IOMMU devices by default
Disable the IOMMU PCI devices in the chipset devicetree. In order for
the IOMMU devices on the Onyx mainboard still be enabled, enable them in
the mainboard devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8c1bbbf370a3b5566a8484bcfa88dc4efa31222b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79409
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12 18:30:55 +00:00
Felix Held
2f58bbd686 soc/amd/genoa: Parse APOB for DRAM layout
Use the xPRF call to report holes in memory and report those regions as
reserved.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5605499e39931e1a1592318310112666f8a0f144
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-12 18:26:34 +00:00
Arthur Heymans
5f6cf6105c vendorcode/amd/genoa: Parse APOB for DRAM layout
Use the xPRF call to report holes in memory to report those regions as
reserved.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: If89b08a31a9b9f8e7d2959d1bc45e91763fe565b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78922
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12 18:26:09 +00:00
Martin Roth
a31b28cb23 mb/amd/onyx: Add MPIO config
Add the device and chip entries for the various PCIe ports and MPIO
lane configuration. Below each PCIe bridge device with an external PCIe
port on the mainboard, an MPIO chip is added that provides the
corresponding MPIO configuration for this external PCIe port.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8563c5a07eb8fd8ff9dd4e7b63fc9a7d485b1316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78921
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12 18:25:35 +00:00
Arthur Heymans
f1b1412068 soc/amd/genoa: Add opensil MPIO chip files
Add the openSIL MPIO chip driver that allows specifying the MPIO lane
configuration in the mainboard's devicetree instead of having this
configuration in a separate port descriptor C file.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I1d408a7eff22423612bc5eb9bfebaf0d86642829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76520
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12 18:25:09 +00:00
Arthur Heymans
62389ab04a vendorcode/amd/opensil: Add SATA configuration
For now, we'll use a hard-coded SATA controller configuration that
should work in most cases instead of making everything configurable via
devicetree settings.

In the process of scrubbing opensil for public release SATA became non
functional.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ib37a081c0be4fdd2785e1dca70f376b967ce4462
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76518
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12 16:58:08 +00:00
Martin Roth
21be665c9a mb/amd/onyx: Add USB configuration
Drive board specific USB configuration from the coreboot devicetree into
the opensil input block.

In the process of scrubbing opensil for public release USB became non
functional.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I62eefe1061446612168dd27e673a2742903456c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78920
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-12 12:30:24 +00:00
Martin Roth
f643a4d77e vendorcode/amd/opensil: Add USB configuration
Drive board specific USB configuration from the coreboot devicetree into
the opensil input block.

In the process of scrubbing opensil for public release USB became non
functional.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic41f57f3208aebb3a8b42f70cf558de50fa4de24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78919
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12 12:29:51 +00:00
Felix Held
ddc8e5d7bf soc/amd/genoa/chip.h: drop unneeded xhci2_enable
Genoa has no XHCI2 controller, so drop this devicetree option.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5b995bb1c0cf0032be25ab215333bc966427f7ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79454
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12 12:29:19 +00:00
Arthur Heymans
10e60ab49e arch/arm64/armv8/Makefile.inc: Add clang -target for .ld CPP
When preprocessing the linker script the target arch needs to be
specified.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Id18af3da93d2d06a2ebb83eddd03377c9026c8fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-12-12 12:23:53 +00:00
Kun Liu
3914561ef5 mb/google/rex/var/screebo: Increase PL1 max value from 15W to 25W
Adjust PL1 max value from 15W to 25W

BUG=b:314263021
TEST=emerge-rex coreboot

Change-Id: I4122a13d7e33c736299c1a759ec51f7a3b29340f
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79377
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12 12:21:15 +00:00
Martin Roth
b94fb02178 util/abuild: Better identify config string in log
When using the --skip_set and --skip_unset arguments, the config line
looked like a statement that the build was being skipped instead of
abuild just printing the configuration.

This updates those config statements to better show that it's the
config and not stating that this particular build is being skipped.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6cc59f9b33dcda51aeb3640d449037a0aa054e36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76936
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-12 00:43:13 +00:00
Mark Hasemeyer
431ca5eab5 ec/google/chromeec: Provide ec_sync wake option
The ACPI spec defines keywords for the GpioInt and Interrupt resources
to specify whether a given pin is wake capable. Some boards are using
the ec sync interrupt pin to wake the system so the CREC _CRS needs to
be updated accordingly.

Provide a new macro that allows a board to specify whether its ec sync
pin is wake capable.

BUG=b:243700486
TEST=Dump ACPI and verify ExclusiveAndWake share type is set when
     EC_SYNC_IRQ_WAKE_CAPABLE is defined

Change-Id: I483c801ff0fee4d3ce0a3b2fc220e0bd9356a612
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
2023-12-11 14:33:23 +00:00
Felix Held
f3523b4f0d soc/amd/genoa/chipset.cb: add missing '_' in gpp_bridge_3_b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22b9b6781f516b96724b67d1321dd71b98e0e0e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-11 11:57:02 +00:00
Arthur Heymans
663c577311 soc/amd/genoa: Add USB configuration
Drive board specific USB configuration from the coreboot devicetree into
the opensil input block.

Add USB OC pins to chipset.cb

In the process of scrubbing opensil for public release USB became non
functional.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I506547a7abbb643d3e982e44a92f33b45cd739e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-11 11:04:36 +00:00
Felix Held
543c1ee314 soc/amd/genoa/chipset.cb: enable dummy functions
Enable the dummy function 0 that don't have an alias in the chipset
devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I607245c587a544007fd714f64901cbb50014612f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-11 11:02:31 +00:00
Yidi Lin
e78ea98bb2 libpayload/arm64: Round fb_size up to a multiple of GRANULE_SIZE
If a framebuffer is already configured by coreboot, we need to ensure
that the framebuffer size is a multiple of GRANULE_SIZE before passing
to `mmu_add_memrange`. Otherwise, we would fail to allocate memory
region due to `sanity_check`.

Change-Id: Ia6a6400733ca10a61220087e87022f68c28e4789
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79451
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-11 11:00:22 +00:00
Robert Chen
933e50702e mb/google/nissa/var/quandiso: Tune P-sensor
Update proximity sensor tuning value from dedede/kracko tuning.
Remove GPIO override to use the configuration from nissa baseboard:
- GPP_B5  ==>   SOC_I2C_SUB_SDA
- GPP_B6  ==>	SOC_I2C_SUB_SCL

BUG=b:310050220
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I7c687677a797415d80be4c420484d3346a8455f6
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79247
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-11 10:46:32 +00:00
Felix Held
6c00a6afc2 soc/amd/common/data_fabric: pass PCI segment group to domain code
Return the PCI segment group number from data_fabric_get_pci_bus_numbers
via pointer argument so that amd_pci_domain_scan_bus can handle the PCI
segment group numbers once coreboot supports more than one PCI segment
group. For now, just print an error and return if the buses are on a PCI
segment group other than 0.

TEST=Mandolin still boots

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia53cda0ba656201c2197d05bc0d4a8fbbe8ad5d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-11 10:42:50 +00:00
Subrata Banik
7ae510093c soc/intel/meteorlake: Add entries to eventLog on invocation of early SOL
This patch records early signs of user activity during CSE firmware
synchronization or MRC (re)training events in the event
log (ELOG_TYPE_FW_EARLY_SOL).

These can be used to ensure persistence across global reset (e.g. after
CSE sync) so that they can be later retrieved in order to build things
such as test automation ensuring that we went through the SOL
path/display initialized.

BUG=b:279173035
TEST=Verified on google/rex, event shows in eventlog after CSE sync
and/or MRC.

Scenario #1: While performing MRC update

1 | 2023-11-08 | Early Sign of Life | MRC Early SOL Screen Shown
2 | 2023-11-08 | Memory Cache Update | Normal | Success
3 | 2023-11-08 | System boot | 9
4 | 2023-11-08 | ACPI Wake | S5

Scenario #2: While performing CSE update/downgrade

11 | 2023-11-08 | Early Sign of Life | CSE Sync Early SOL Screen Shown
12 | 2023-11-08 | System boot | 13

Scenario #2: While performing both MRC and CSE upgrade

16 | 2023-11-08 | Early Sign of Life | MRC Early SOL Screen Shown
17 | 2023-11-08 | Early Sign of Life | CSE Sync Early SOL Screen Shown
18 | 2023-11-08 | Memory Cache Update | Normal | Success
19 | 2023-11-08 | System boot | 16
20 | 2023-11-08 | ACPI Wake | S5

Change-Id: Idfa6f216194fd311bb1a57dd7c86fe7446a3597c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78983
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-11 05:09:38 +00:00
Jeremy Compostella
79c09ba3b6 soc/intel/mtl: Display Sign-of-Life message using FSP-M
Meteor Lake Firmware Support Package (FSP-M) for ChromeOS includes an
pre-memory graphics driver which can be leveraged to display a text
message thanks to the following FSP-M UPD (Updateable Product Data):

- VgaInitControl (bitfield):

  Bit 0: Turn on graphics, setup VGA text mode and display
         `VgaMessage' text centered on the screen.

  Bit 1: Clear text and tear down VGA text mode and graphics before
         returning from FSP-M.

- VbtPtr (address): Pointer to the VBT (Video BIOS Tables) binary.

- VbtSize (unsigned int): Size of the VBT binary.

- LidStatus (boolean): Due to limited resources at early boot stages,
  the text message is displayed on a single monitor. The lid status
  helps decide which display is the most appropriate.

  0: Lid is closed: show the text message on the external display if
     available, do not display anything otherwise.

  1: Lid is open: show the message on the internal display if
     available, use an external display if available otherwise.

- VgaMessage (string): Text message to display.

If the `SOC_INTEL_METEORLAKE_SIGN_OF_LIFE' flag is set, coreboot
configures the UPDs above to display a text message during memory
training and CSME update. The text message can be configured via the
locale text mechanism using the `memory_training_desc' name.

The `SOC_INTEL_METEORLAKE_SIGN_OF_LIFE' selects the LZ4 compression
algorithm for VBT because LZMA decompression is not available in
romstage by default and adding LZMA support increases the romstage
binary size more than the VBT binary is reduced.

BUG=b:279173035
TEST=Text message is displayed during memory training on a rex board

Change-Id: I8e7772582b1895fa8e38780932346683be998558
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78244
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-11 05:07:23 +00:00
Anil Kumar
e46af3fca4 soc/intel/cse: Add API to check if CSE Firmware update is required
This patch adds a function to check if a CSE FW update is required
during this boot. The function is expected to be used during use
cases like Pre-Memory Sign of Life text display to inform user of
a CSE Firmware update.

Bug=279173035
TEST=build and boot on google/rex board. Call the function in romstage
and confirm it returns True during CSE FW update and False otherwise

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: If5fae95786d28d586566881bc4436812754636ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78243
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-11 05:06:48 +00:00
Kilari Raasi
ebb28c523e soc/intel/meteorlake: Disable MarginLimitCheck and RMC UPDs
By default MarginLimitCheck and RMC UPDs are enabled in FSP
which enables fast and cold boot retraining causing the
boot time increase. So, disabling the same UPDs to fix it.

Change-Id: Ib15d37dbe177f31590f23de4e239a2e82abf1335
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-11 05:06:18 +00:00
Kilari Raasi
b21bc9d9df vc/intel/fsp/mtl: Update header files from 3323_86 to 3424_88
Update header files for FSP for Meteor Lake platform to
version 3424_88, previous version being 3323_86.

FSPM:
1. Add `MarginLimitCheck` UPD
2. Add pre-memory graphics UPDs i.e `LidStatus`,
   `VgaInitControl`,`VbtPtr`,`VbtSize`,`VgaMessage`
3. Address offset changes

FSPS:
1. Add `Usb4CmMode` UPD
2. Address offset changes

BUG=b:310108425
TEST=Able to build and boot google/rex to ChromeOS.

Change-Id: I3f71cd739a607318fda06fa50d4a379d64857458
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78997
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-11 05:05:17 +00:00
Lennart Eichhorn
bf7eba7add arch/riscv/payload: Remove old RISC-V CSR names
LLVM/clang 17 removed support for CSR names that are no longer included
in the RISC-V ISA Manual Privileged Specification since version 1.12.

Related LLVM commit: https://reviews.llvm.org/D149278

Change-Id: I7c8f2a06a109333f95230bf0a3056c8d5c8a9132
Signed-off-by: Lennart Eichhorn <lennarteichhorn@googlemail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-12-09 15:27:36 +00:00
Felix Singer
e06ebcd530 util/docker/alma: Add Dockerfile.base
Following commands were used to test if everything builds:

    * make crossgcc
    * make clang
    * make what-jenkins-does

Change-Id: Iab15fe908aa6ca81724ed7557caf70c38817ad25
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zebreus <lennarteichhorn@googlemail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-08 22:24:33 +00:00
Felix Singer
1bdb6695f4 util/docker/rocky: Add Dockerfile.base
Following commands were used to test if everything builds:

    * make crossgcc
    * make clang
    * make what-jenkins-does

Change-Id: I60e00932332801c0f62d88b7860afb330d9469e4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zebreus <lennarteichhorn@googlemail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-08 22:24:06 +00:00
Felix Singer
57885b4195 util/docker/archlinux: Rename Dockerfile to Dockerfile.base
Rename Dockerfile to Dockerfile.base since additional Dockerfiles basing
on this one will be added later.

Change-Id: I70f2c89f739068749e1017524b6f8ef1b03d6456
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79344
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zebreus <lennarteichhorn@googlemail.com>
2023-12-08 22:23:36 +00:00
Felix Singer
b690ee5951 util/docker/archlinux: Add more packages allowing CI builds
Following commands were used to test if everything builds:

    * make crossgcc
    * make clang
    * make what-jenkins-does

Change-Id: I757e6dbac557bcb640777b819529a978bf54ed93
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zebreus <lennarteichhorn@googlemail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-08 22:23:09 +00:00
Arthur Heymans
81ceea1592 vendorcode/amd/opensil: Set up resource manager input block
Tell the resource manager in openSIL to distribute the available IO and
MMIO ranges across the different PCI root bridges.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0985712bc4e87b4068dea22bde1dfa371a6c47bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-08 22:20:33 +00:00
Julius Werner
a595478428 Makefile: Make vboot_fw.a a .PHONY target
vboot_fw.a is built via a sub-invocation of make, but make is not able
to track dependencies between different invocations. That means the
toplevel make assumes that the vboot_fw.a target depends only on the
dependencies explicitly listed in coreboot's Makefile (only config.h in
this case), and thus assumes that if config.h didn't change it does not
need to rebuild the library. This breaks incremental builds when files
inside the vboot repository change.

This patch marks the target as .PHONY so that it will always be rebuilt.
The vboot Makefile's own dependency tracking will then ensure that on an
incremental build we only rebuild the vboot sources that actually
changed, so if nothing changed this will just add a simple and quick
$(AR) call.

Change-Id: I8bdd4e1589124914ba1e877e04b40ee709ea4140
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79375
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-08 17:44:38 +00:00
Zheng Bao
c7a5c50760 Revert "nipperkin: Fix WLAN to GEN2 speed" & "Disable PSPP for WLAN"
Updated Linux FW works with PCI gen3 speed and PSPP.

This reverts
commit 05c9a850fd ("mb/google/nipperkin: Fix WLAN to GEN2 speed")
https://review.coreboot.org/c/coreboot/+/63593

and
commit 76fddd9639 ("mb/google/nipperkin: Disable PSPP for WLAN")
https://review.coreboot.org/c/coreboot/+/63722

The changes are overlapped and are reverted together.

BUG=b:240426142 & b:228830362

The system is able to ran over 2500 cycles on Nipperkin with command
suspend_stress_test -c 10000 --wake_min 10 --suspend_min 10 \
    --nofw_errors_fatal

The whole variant_update_dxio_descriptors is empty and is pushed back
to weak function.

Change-Id: Id207076542edc8ea0cabc6e02e29856c2b6803c7
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
2023-12-08 16:33:02 +00:00
Arthur Heymans
87837df807 acpi.c: Fix generating pointer to cb_tables located >4G
Use the generic resource_consumer method which works for memory both
above and below 4G.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I1bc553b18d08cee502b765166227810f8e619631
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76181
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-12-08 14:02:45 +00:00
Terry Cheong
03807acfa9 mb/google/rex/var/screebo: set audio GPIO pins based on fw_config
Enable BT offload when I2S option is selected for screebo.

BUG=b:275538390
TEST=Verified audio playback using BT speaker/headset in I2S mode on google/screebo.

Fixes: https://review.coreboot.org/c/coreboot/+/77755
Change-Id: I7ebe8e28d35428ce2fb8129dc145fec9ac60f9da
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79378
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-08 12:56:21 +00:00
Weimin Wu
c6fd32d131 mb/google/nissa/var/anraggar: Fix unrecogniz Type-C USB disk on depthcharge
Due to TCPC0 & TCPC1 exchanged compare to Neried design,
but related USB2 Ports not exchanged, keep mainboard C port to conn0.

BUG=b:312998945
TEST=can boot from external Type-c USB disk

Change-Id: Ib8df4a256bd9cd1b2ca229b09d68f97babc8092e
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-08 12:55:58 +00:00
Ivy Jian
2eeec43379 mb/google/brox: Update configuration for USB ports
Update brox devicetree based on the latest schematics.

- Configure typeC to EC mux ports settings.
- Configure USB2/USB3 ports settings.
- Configure TCSS ports settings.

BUG=b:311450057
BRANCH=None
TEST=emerge-brox coreboot

Change-Id: Iac5a2e8be6cea64f107d267d4cf71529f08bb63d
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79391
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-08 02:05:09 +00:00
Felix Held
4a9ed707c8 acpi: add missing device/device.h include
The device/device.h provides the definition for struct device used in
those files, so include this header file to make sure that it's not only
included indirectly via some other header file.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ff7cdbf0f53ada92adb53cf268e5feee9df4629
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-12-07 13:19:47 +00:00
Felix Singer
1e6134d223 3rdparty/intel-microcode: Update submodule to upstream main
Updating from commit id 6788bb0:
2023-08-08 12:04:21 -0600 - (microcode-20230808 Release)

to commit id ece0d29:
2023-11-14 10:19:09 -0600 - (microcode-20231114 Release)

This brings in 1 new commits:
ece0d29 microcode-20231114 Release

Change-Id: I1d65318015803d5ca11dcf52e4011f49cf3129a1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-07 04:23:18 +00:00
Felix Singer
13634ae7d7 3rdparty/vboot: Update submodule to upstream main
Updating from commit id ba7fd22d:
2023-11-29 01:50:20 +0000 - (Makefile: Always link libdl)

to commit id db533497:
2023-12-05 20:09:44 +0000 - (host/lib/pkcs11: Remove superfluous 'nss' directory from include paths)

This brings in 4 new commits:
db533497 host/lib/pkcs11: Remove superfluous 'nss' directory from include paths
3307f1a7 tlcl: Add `TlclEvictControl()` support
0bd01137 tlcl: Remove the redundant bytes in TlclReadPublic
9afdf0f2 sign_official_build.sh: stop messing with +x

Change-Id: Ib2ded699605dfa4032f4687e1e336297c0af1372
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-07 04:22:56 +00:00
Matt DeVillier
6bb0f8aaa4 soc/amd/common: Move PCIe CLKREQ programming under fsp
CLKREQ programming as currently implemented is completely dependent on
FSP DXIO descriptors, so move under common/fsp/pci and rename the
Kconfig to reflect the move.

TEST=build google/{guybrush, skyrim, myst}

Change-Id: I87b53d092ddc367b134c25949f9da7670a6a1d88
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-06 19:12:59 +00:00
Felix Singer
fca7fd2a73 util/docker: Add build script
Integration for additional container images might be added to the
Makefile at some later point. However, in order to build and test new
images just add a simple script which fulfills that requirement until
then.

Change-Id: Ibd0a6d59f395e074c784452849650d7f03b4f1d8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-06 18:44:38 +00:00
Felix Singer
30138b3361 util/docker/alpine: Rename Dockerfile to Dockerfile.base
Rename Dockerfile to Dockerfile.base since additional Dockerfiles basing
on this one will be added later.

Change-Id: I611feca234ae7600f9c17ae397f9f3903879c057
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-06 18:43:45 +00:00
Arthur Heymans
adee6a6945 vendorcode/amd/opensil: Add initial setup and API calls
- First a console is set up for opensil.
- After that a region in CBMEM is reserved and passed to opensil which
will use it as a buffer for input/output information.
- Finally opensil is called and the return value handled.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4833a5a86034a13e6be102a6b68c3bb54108bc9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-12-06 18:32:58 +00:00
Ivy Jian
76e499319b mb/google/brox: Generate RAM IDs for two modules
Add the support LP5 RAM parts for brox:
1. HYNIX LPDDR5 6400 2GB H9JCNNNBK3MLYR-N6E
2. MICRON LPDDR5 6400 4GB MT62F1G32D4DR-031 WT:B

DRAM Part Name                  ID to assign
H9JCNNNBK3MLYR-N6E              0 (0000)
MT62F1G32D4DR-031 WT:B          1 (0001)

BUG=b:311450057
BRANCH=None
TEST=Run part_id_gen tool without any errors
Change-Id: Ib17f26a310435e37088191594863a645aa751440
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79392
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-12-06 17:22:49 +00:00
Felix Held
903454e7b8 sb/intel/bd82x6x: assign EHCI controller ops in chipset devicetree
Since the EHCI controllers in the PCH are always on the same device
functions, the device operations can be statically assigned in the
devicetree and there's no need to bind the EHCI device operations to the
PCI devices during runtime via a list of PCI IDs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I92ecc3607216fb2f31639db9628898c9ce81770d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79171
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-12-06 16:20:24 +00:00
Felix Held
afebab1ebe sb/intel/bd82x6x: assign PCH XHCI controller ops in chipset devicetree
Since the XHCI controller in the PCH is always on the same device
function, the device operations can be statically assigned in the
devicetree and there's no need to bind the XHCI device operations to the
PCI device during runtime via a list of PCI IDs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8685bec734415346a53330c9bd1aa82986995f1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79170
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-12-06 16:20:08 +00:00
Felix Held
898757fc44 sb/intel/bd82x6x: assign PCH PCI bridge ops in chipset devicetree
Since the PCI bridge in the PCH is always on the same device function,
the device operations can be statically assigned in the devicetree and
there's no need to bind the PCI bridge device operations to the PCI
device during runtime via a list of PCI IDs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic9ca925a12e64c9a5b3bf295653bf032572ff29a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79169
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-12-06 16:19:01 +00:00
Felix Held
1bb327f216 sb/intel/bd82x6x: assign PCH SMBus controller ops in chipset devicetree
Since the SMBus controller in the PCH is always on the same device
function, the device operations can be statically assigned in the
devicetree and there's no need to bind the SMBus device operations to
the PCI device during runtime via a list of PCI IDs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3d3745ba5aefa30efbe705155d216aa7eadd26a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79168
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-06 16:18:31 +00:00
Varshit Pandya
e8f62d1355 commonlib/bsd: Use tabs instead of whitespaces
Change-Id: I05e7ba10e499ea1e824bdd6c87df05fc5a0864f8
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79400
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-06 16:02:44 +00:00
Felix Held
2009b99834 nb/amd/pi/00730F01/chipset.cb: don't call dummy function host bridge
Function 0 of the device that has the bridges to other buses is a dummy
function that can be left enabled to not have to shuffle around the
device function numbers when the first PCI bridge on that device isn't
enabled. That dummy device function is however not a PCI host bridge, so
change the comment from 'Dummy Host Bridge' to 'Dummy device function'.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Nico Huber <nico.h@gmx.de>
Change-Id: I6069205bd2e1cb0f75025e9f330afc50462e742a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79397
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-06 16:02:15 +00:00
Felix Held
f5b09dbe18 soc/amd/*/chipset.cb: don't call dummy device functions host bridges
Function 0 of the devices that have the bridges to other buses are dummy
functions that can be left enabled to not have to shuffle around the
device function numbers when the first PCI bridge on those devices isn't
enabled. Those dummy device functions are however not PCI host bridges,
so change the comments from 'Dummy Host Bridge' to 'Dummy device
function'.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ibddfdf558d84bc44434d718b86f41bd06044b22a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-06 16:01:18 +00:00
Eran Mitrani
3e306d48cd mb/google/rex/variants/deku: Enable CNVi PCI device
BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku

Change-Id: I41a64252f08304ffc66fd782e54720252064ca49
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-06 15:09:39 +00:00
Felix Held
88da16b92d soc/amd/genoa/Kconfig: add CONSOLE_UART_BASE_ADDRESS defaults
Add defaults for the CONSOLE_UART_BASE_ADDRESS Kconfig symbol so that
the SeaBIOS payload will know where the MMIO address of the UART is to
build successfully without any additional user input during the build.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia05c3531cdbf3fd3e2e5f81b9d652f9dfef2111a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79395
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-06 15:09:01 +00:00
Naresh Solanki
1fe1904f38 acpi/acpi_gic: Add GIC ITS subtable
Add support for generating GIC subtable ITS (Interrupt Translator
Service).

Change-Id: I1bcb3ad24de64cbba8aeef7ba7254d3157e0dc43
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-12-06 13:07:27 +00:00
Naresh Solanki
6920c6f232 acpi: Add IO Remapping Table structures
Input Output Remapping Table (IORT) represents the IO topology of an Arm
based system.

Document number: ARM DEN 0049E.e, Sep 2022

Change-Id: I4e8e3323caa714a56882939914cac510bf95d30b
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-12-06 13:06:22 +00:00
Felix Held
67b3c8f278 acpi/acpi: make sure that table_ptr is non-NULL in acpidump_print
While acpidump_print shouldn't be called with a NULL pointer as
table_ptr argument, better add a check to not end up dereferencing the
NULL pointer.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic3cc103c8a47fb8c2fe4262236ea47013af27c4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-12-05 18:36:15 +00:00
Felix Held
372dfe0e20 sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetree
Since the LPC bridge in the PCH is always on the same device function,
the device operations can be statically assigned in the devicetree and
there's no need to bind the LPC bridge device operations to the PCI
device during runtime via a list of PCI IDs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I366226be4aba75b98e45e4832bfe129fac14dbfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-12-05 15:06:03 +00:00
Shelley Chen
1a06631243 mb/google/brox: Fix memory config
Fix up the memory config for brox based on the schematics.  Also,
since memory training needs to happen in romstage, initializing the
MEM_STRAP & MEM_CH_SEL gpios for use in romstage. Also consolidating
the GPIOs needing to be initialized in romstage into the baseboard
gpio.c file.

BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot

Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-12-05 01:51:16 +00:00
Felix Held
b164d7a291 nb/intel/sandybridge/pcie: drop unneeded HAVE_ACPI_TABLES guards
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1e8c8b3e3672d1589a5910753986e4033d2ce766
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-12-04 17:54:36 +00:00
Paul Menzel
8742577548 ec/lenovo/h8/acpi/thermal: Make NameSeg FPWR all upper case
Building the Lenovo T60/T60p, iasl 20230628 shows the remark below:

    dsdt.asl   2099:   PowerResource (FPwR, 0, 0)
    Remark   2182 -                     ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (FPWR)

    dsdt.asl   2118:    Name (_PR0, Package () { FPwR })
    Remark   2182 -                                ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (FPWR)

Address it by making it all upper case.

Change-Id: Ia7924b015e76c43818d2d82da35ce0013d721c26
Fixes: 3ab13a8691 ("ec/lenovo/h8/acpi/thermal: Add support for passive cooling")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79367
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-04 17:53:40 +00:00
Subrata Banik
ffd9dd55af mb/google/rex/var/screebo: Override power limits
This patch allows variants to override the default baseboard PLx
limits.

Additionally, rearrange the include header files alphabetically.

BUG=b:313667378
TEST=Able to boot google/screebo with modified power limits.

Before:

[DEBUG]  WEAK: src/mainboard/google/rex/variants/baseboard/rex/
         ramstage.c/variant_devtree_update called
[INFO ]  Overriding power limits PL1 (mW) (10000, 15000)
         PL2 (mW) (40000, 40000) PL4 (W) (84)

After:

[INFO ]  Overriding power limits PL1 (mW) (10000, 15000)
         PL2 (mW) (40000, 40000) PL4 (W) (84)

Change-Id: Ic66872c530963238a0bf5eebbd5b5a76a7985e5c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-04 17:04:02 +00:00
Nina Wu
5fe04f33ee soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_S
Update BND_NORTH_APB2_S's domain 5 permission to allow the access from
APU. The APU requires certain information saved in BND_NORTH_APB2_S for
voltage tuning. If this information cannot be retrieved, the APU may
operate at a high frequency with low voltage. Consequently, the APU may
not function as expected.

Change-Id: I967b138dc5517e54da7fbf94b9e502e478c991b5
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79348
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-04 16:48:33 +00:00
Michał Żygowski
a87ab39817 security/vboot: Add Kconfig option to clear recovery request
For ChromeOS platform the recovery reason is cleared in
vb2api_kernel_phase2 which is probably not called by any non-ChromeOS
system. It results in the platform being stuck in recovery mode, e.g.
when RW firmware verification fails. Even if the RW partition is
flashed with correctly signed image, the persistent non-zero recovery
reason will prevent vboot from attempting the RW partition check.

Use the newly exposed vb2api_clear_recovery and
VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE Kconfig option to clear the recovery
reason and save it immediately to the VBNV. The idea is to let
non-ChromeOS coreboot platform to clear the recovery reason when
needed.

TEST=Clear the recovery reason in mainboard_final function right
before payload jump when RW partition is corrupted and RW partition is
valid. In case it is corrupted, the platform stays in recovery mode,
when valid the platform boots from RW partition. Tested on MSI PRO
Z690-A DDR4.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I7ffaf3e8f61a28a68c9802c184961b1b9bf9d617
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74343
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-04 15:56:16 +00:00
Patrick Rudolph
7f991b3a90 cpu/intel/model_206ax: Use macro IS_IVY_CPU
Use existing macro instead of open coding magic numbers.
No functionality change.

Change-Id: If45f7f3f2b4226cedde6ff91b9848b9875f45f9f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79148
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-04 15:54:45 +00:00
Eran Mitrani
a8636ae86b mb/google/rex/variants/deku: Complete USB configuration
+-------------+----------------+------------+
| USB 2.0     | Connector Type | OC Mapping |
+-------------+----------------+------------+
|      1      |     Type-C     |    OC_0    |
+-------------+----------------+------------+
|      2      |     Type-C     |    OC_0    |
+-------------+----------------+------------+
|      3      |     Type-C     |    OC-0    |
+-------------+----------------+------------+
|      4      |     Type-A     |    OC_3    |
+-------------+----------------+------------+
|      5      |     Type-C     |    OC_0    |
+-------------+----------------+------------+
|      6      |     Type-A     |    OC_3    |
+-------------+----------------+------------+
|      7      |     Type-A     |    OC_3    |
+-------------+----------------+------------+
|      8      |     Type-A     |    OC_3    |
+-------------+----------------+------------+
|      9      |     Type-A     |    OC_3    |
+-------------+----------------+------------+
|      10     |       BT       |     NA     |
+-------------+----------------+------------+

+---------------------+-------------------+------------+
| USB 3.2 Gen 2x1     | Connector Details | OC Mapping |
+---------------------+-------------------+------------+
|          1          |       Type-A      |    OC_3    |
+---------------------+-------------------+------------+
|          2          |       Type-A      |    OC_3    |
+---------------------+-------------------+------------+

+------+-------------------+------------+
| TCPx | Connector Details | OC Mapping |
+------+-------------------+------------+
|   1  |   Type C port 0   |    OC_0    |
+------+-------------------+------------+
|   2  |   Type C port 1   |    OC_0    |
+------+-------------------+------------+
|   3  |   Type C port 2   |    OC_0    |
+------+-------------------+------------+
|   4  |   Type C port 3   |    OC_0    |
+------+-------------------+------------+

BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku

Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I90d3d984af6d40efb4553cf5675617700161d2d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-04 15:52:46 +00:00
Eran Mitrani
3bad203be1 mb/google/rex/variants/deku: Add basic DTT
Add default Intel DPTF.

BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku

Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id681754fc8e7b418de35f66df097cadd4aad7448
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-04 15:52:31 +00:00
Eran Mitrani
c2aa756ca1 mb/google/rex/var/deku: Enable LAN0, LAN1
google/deku is a Chromebox featuring two LAN ports.
Add overridetree.cb entry to configure the LAN0 LAN1 devices.

BUG=b:305793886
TEST=Built FW image correctly.

Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I8980dabc7f9fc731a2b60c599e1e48c9b11dabb4
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79292
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-04 15:52:12 +00:00
Alexander Couzens
9092d221a1 inteltool: memory: log PCI id of unknown devices
Change-Id: I25396e5480c45729710b16345f997c78e8bcbccb
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-12-04 15:51:41 +00:00
Subrata Banik
ceccd49ecb mb/google/rex/var/ovis: Add power limit support for MCH ID 0x7d14
This patch adds the power limit configuration for MCH ID index 3 aka
0x7d14 DID which is identical to MCH ID 0x7d01 (index 1).

TEST=Able to perform power limit configuration for google/ovis.

[DEBUG]  WEAK: src/mainboard/google/rex/variants/baseboard/ovis/
         ramstage.c/variant_devtree_update called
[INFO ]  Overriding power limits PL1 (mW) (19000, 28000)
         PL2 (mW) (64000, 64000) PL4 (W) (120)

Change-Id: Iff71adb4e26d18970b5947927c258419f751de32
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79332
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-12-04 15:51:14 +00:00
Subrata Banik
70770ebd36 mb/google/rex: Simplify power limit configuration usage
This patch removes the deprecated PL_PERFORMANCE and PL_BASELINE
configurations, relying instead on the refactored power limit flow.

This flow allows for seamless overrides by the baseboard and/or by
the variant board, if necessary.

Specifically, this patch:

- Removes PL_PERFORMANCE and PL_BASELINE configuration options from
  mainboard.c in the google/rex directory.
- Relies on the baseboard_devtree_update() function, which is
  implemented by the respective baseboard, to handle power limit
  configuration.
- Leverages the variant_devtree_update() function, which is a
  __weak implementation, to allow overrides by the variant directory.

This simplification improves code readability and maintainability while
maintaining the flexibility to handle power limit configurations as
needed.

Change-Id: I872e5cb59d7b2789ef517d4a090189785db46b85
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79331
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-04 15:50:55 +00:00
Subrata Banik
72d616c22c soc/intel/alderlake: Update LidStatus UPD dynamically
This patch ensures that the LidStatus UPD is passed a dynamic value,
rather than always passing 1 (CONFIG_RUN_FSP_GOP enabled) for FSP 2.0
devices.

Problem statement:
* FSP-S GFX PEIM initializes the on-board display (eDP) even when the
  LID is physically closed, because LidStatus is always set to 1.
* FSP-S skips external display initialization even when the LID is
  closed.

Solution:
* FSP-S GFX PEIM module understands the presence of an external display
  if LidStatus is not set, and tries to probe the other display
  endpoint.
* Statically passing LidStatus as always enabled (aka 1) does not
  illustrate the exact device scenarios, so this patch updates
  LidStatus dynamically by reading the EC memory map offset.

BUG=b:313886118
TEST=Able to build and boot google/marasov to redirect the display
using external HDMI monitor while LID is closed.

Change-Id: Idb1d71bd54837630f36d43a45effc53d35f9cb70
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79352
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-04 06:15:56 +00:00
David Milosevic
d982274a4e acpi: Add PPTT support
This patch adds code to generate Processor Properties
Topology Tables (PPTT) compliant to the ACPI 6.4 specification.

 - The 'acpi_get_pptt_topology' hook is mandatory once ACPI_PPTT
 is selected. Its purpose is to return a pointer to a topology tree,
 which describes the relationship between CPUs and caches. The hook
 can be provided by, for example, mainboard code.

Background: We are currently working on mainboard code for qemu-sbsa
and Neoverse N2. Both require a valid PPTT table. Patch was tested
against the qemu-sbsa board.

Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10
Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-12-02 19:16:26 +00:00
Subrata Banik
faf2779959 mb/google/rex: Enhance power limit override mechanism
This patch expands the power limit override capability to include
variants directories, enabling them to modify power limit settings
configured by the baseboard.

Previously, only the baseboard could override power limit settings.
For instance, while the google/rex baseboard sets the PL1 max power
limit to 15W, the google/screebo variant couldn't override this value.

This enhancement empowers variants directories to override baseboard-
configured power limit settings, allowing for greater flexibility and
control over power limits.

BUG=b:313667378
TEST=Able to call into _weak implementation of `variant_devtree_update`
unless there is one override.

[DEBUG]  WEAK: src/mainboard/google/rex/variants/baseboard/rex/
         ramstage.c/variant_devtree_update called
[INFO ]  Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW)
         (40000, 40000) PL4 (W) (84)

Change-Id: Ib07691625e075b0fbab42271512322ffc60ba13b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-02 18:03:52 +00:00
Matt DeVillier
73c918c590 Update amd_blobs submodule to upstream main branch
Updating from commit id eb91266f01db (2023-11-29):
  MDN: Update mendocino SMU to 90.43.0

to commit id 64cdd7c8ef19 (2023-12-01):
  Cezanne/PSP: clean up release notes

This brings in 3 new commits:
64cdd7c8ef Cezanne/PSP: clean up release notes
54c45443b8 Stoneyridge: Drop PSP binaries for Bristol Ridge (BR)
bfa3c44c8c Stoneyridge: Tidy up the PSP binaries folder

Change-Id: Ifd2ca49a472c516c69c9f43ed4dc3faefd8729d8
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79365
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-12-02 17:53:11 +00:00
Zheng Bao
3ea3fbe4f2 soc/amd: Add DBG2 ACPI table
Dump the DBG2 table on Linux console.
$> acpidump -s
ACPI: DBG2 0x0000000000000000 000054 (v00 COREv4 COREBOOT 00000000 **)

$> acpidump > acpidump.bin
$> acpixtract -a acpidump.bin
$> iasl -d dbg2.dat
$> cat dbg2.dsl
/*
 * ACPI Data Table [DBG2]
 *
 * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
 */

[000h 0000 4]             Signature : "DBG2" [Debug Port table type 2]
[004h 0004 4]          Table Length : 00000054
[008h 0008 1]              Revision : 00
[009h 0009 1]              Checksum : FA
[00Ah 0010 6]                Oem ID : "COREv4"
[010h 0016 8]          Oem Table ID : "COREBOOT"
[018h 0024 4]          Oem Revision : 00000000
[01Ch 0028 4]       Asl Compiler ID : "CORE"
[020h 0032 4] Asl Compiler Revision : 20220331

[024h 0036 4]           Info Offset : 0000002C
[028h 0040 4]            Info Count : 00000001

[02Ch 0044 1]              Revision : 00
[02Dh 0045 2]                Length : 0028
[02Fh 0047 1]        Register Count : 01
[030h 0048 2]       Namepath Length : 0002
[032h 0050 2]       Namepath Offset : 0026
[034h 0052 2]       OEM Data Length : 0000 [Optional field not present]
[036h 0054 2]       OEM Data Offset : 0000 [Optional field not present]
[038h 0056 2]             Port Type : 8000
[03Ah 0058 2]          Port Subtype : 0012
[03Ch 0060 2]              Reserved : 0000
[03Eh 0062 2]   Base Address Offset : 0016
[040h 0064 2]   Address Size Offset : 0022

[042h 006612] Base Address Register : [Generic Address Structure]
[042h 0066 1]              Space ID : 00 [SystemMemory]
[043h 0067 1]             Bit Width : 00
[044h 0068 1]            Bit Offset : 00
[045h 0069 1]  Encoded Access Width : 03 [DWord Access:32]
[046h 0070 8]               Address : 00000000FEDC9000

[04Eh 0078 4]          Address Size : 00000100

[052h 0082 2]              Namepath : "."

Raw Table Data: Length 84 (0x54)

 00: 44 42 47 32 54 00 00 00 00 FA 43 4F 52 45 76 34 // DBG2T.....COREv4
 10: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE
 20: 31 03 22 20 2C 00 00 00 01 00 00 00 00 28 00 01 // 1." ,........(..
 30: 02 00 26 00 00 00 00 00 00 80 12 00 00 00 16 00 // ..&.............
 40: 22 00 00 00 00 03 00 90 DC FE 00 00 00 00 00 01 // "...............
 50: 00 00 2E 00                                     // ....

BUG=b:303689867

Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79174
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-02 17:51:42 +00:00
Felix Held
2eaebfc4bc acpi/acpi: update ACPI_DBG2_PORT_SERIAL_16550 subtype
The Microsoft Debug Port Table 2 (DBG2) specification says that the
serial port subtype 0x00 should only be used for I/O-mapped 16550
compatible UARTs. The subtype 0x12 is a superset of that, and supports
specifying MMIO vs IO and the register access size via the generic
address structure. Rename the subtype 0x00 definition to
ACPI_DBG2_PORT_SERIAL_16550_IO_ONLY and add the subtype 0x12 definition
as new ACPI_DBG2_PORT_SERIAL_16550, so that the acpi_write_dbg2_uart
function will write the correct subtype for the generic 16550 UART.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I816bb22e6f76e661c8b8e39a2a4cb83b0085acb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79219
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-02 17:51:02 +00:00
Nicholas Chin
d5b0aeab2e inteltool/gpio_names/*.h: Add GPL-2.0-only SPDX license header
Inteltool is GPLv2 licensed so all files that link to it should be GPLv2
by default. In addition, the contents of several of these headers were
originally moved directly from gpio_groups.c, which is explicitly marked
as GPL-2.0-only.

Change-Id: Ie897cb238c0c9e89fe677c999cbf1803f5f4609a
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-12-02 08:13:39 +00:00
Mate Kukri
62c25351c1 superio/smsc: Add support for the SCH555x series
Used by the OptiPlex 3020/7020/9020:
- EMI and Runtime registers work
- UART1 works (including IRQs)
- PS/2 keyboard and mouse untested

Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-01 17:40:11 +00:00
Weimin Wu
b9523a4281 mb/google/nissa/var/anraggar: Trim GPIO comments
Trim all GPIO comments like "origin ==> current".

BUG=b:304920262
TEST=pass building

Change-Id: I05daa4df16b6da3d3f971b75c7c467032e3f854d
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79321
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-01 16:37:05 +00:00
Weimin Wu
64ae9fe2c0 mb/google/nissa/var/anraggar: Fix the GPP_D6 for LTE power.
Fix GPP_D6 configuration for LTE power enable.

BUG=b:304920262
TEST=mmcli -m any

Change-Id: I2996fd35c2897269997bc0290e0ce93bbbaa1bf8
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79166
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
2023-12-01 16:36:32 +00:00
Weimin Wu
7ac0b43671 mb/google/nissa/var/anraggar: Fix Type-C & DP functions
Due to TCPC0 & TCPC1 exchanged compare to Neried design,
but related USB2 Ports not exchanged.

BUG=b:304920262
TEST=Tpye-C & DP functions workable

Change-Id: I9dacf06b1e672575a684856acdb10b6c88360b18
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79165
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-01 16:36:06 +00:00
Weimin Wu
10db713100 mb/google/nissa/var/anraggar: Enable ILITEK touchscreen
For proto PCB:
GPP_C0 for enable power supply which also for sensor subsystem.
GPP_C0 must allways turn power on, so GPP_C6 is not only used
for enable function but also for stop report.

BUG=b:304920262
TEST=1. touchscreen function workable
     2. INT pin no active during suspend

Change-Id: I7dabf205dba616f57ef9717f950eba96282d8e3d
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
2023-12-01 16:35:37 +00:00
Morris Hsu
0cf76cfabe mb/google/brya/var/dochi: Update overridetree for type c1
Update overridetree to correct AUX pin to USB-C port 3

BUG=b:299570339
TEST=emerge-brya coreboot chromeos-bootimage

Change-Id: I3a5a89c6008fbf28c927f83060e6e508d60845ba
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79343
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-01 15:19:08 +00:00
kiwi liu
4bd12361dc soc/mediatek/mt8188: Support loading OP-TEE via an SMC
This patch adds compilation flags to BL31 to support loading
OP-TEE via an SMC from rootfs. This patch also reserves 80MB memory
space for running the OP-TEE image.

BUG=b:246837563
TEST=emerge-geralt coreboot

Change-Id: Ic38c8beb59c090ae56c5be6821dd8625435609e9
Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78801
Reviewed-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-01 02:55:12 +00:00
Yi Chou
32ea2abe3b libpayload: Fix the stack and data labels
We should make sure _stack/_estack and the other labels are consistent.
And _data & _edata is also useful to clean up the sensitive data on the
data section.

BUG=b:248610274
TEST=emerge-cherry libpayload
BRANCH=none

Cq-Depend: chromium:5052462
Change-Id: I589040f4db60b35813ea9f4ba9503244bd7def00
Signed-off-by: Yi Chou <yich@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-12-01 02:20:29 +00:00
Ivy Jian
1397fd3668 mb/google/brox: Update storage settings for SSD and UFS
Brox has SSD and UFS storage per different SKU.
1. Set SSD on CPU PCIe port (PCIEX4_A) and configure related gpio
settings according to the schematic.
2. Enable UFS, also enable ISH since it is PCI function 0, required
for UFS function 7 to be enabled.
3. Set unused SRCCLKREQ signals to NC.
4. Remove unused gpio settings in variant gpio table to prevent
unexpected overrides.

BUG=b:311450057
BRANCH=None
TEST=emerge-brox coreboot

Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79295
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-01 00:12:27 +00:00
Felix Held
2873cc6804 nb/amd/pi/00730F01: drop leftover family10_northbridge PCI driver
This is likely a copy-paste leftover, since this SoC neither has a PCI
device with the device ID 0x1200 nor is family 10h.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7095f208a7503545ea012241d058692a510109f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79094
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-01 00:05:57 +00:00
Eran Mitrani
19b2ea68ab mb/google/rex/variants/deku: Add GPIO configuration
Based on Platform Mapping Document for Deku (go/cros-deku-mapping)
from Nov 8, 2023 (Rev 0.4)

BUG=b:305793886
TEST=WIP, not tested yet

Change-Id: Ib37a7ebf0aca788d14fafea0f97e364beafb4c4d
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78960
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-30 23:45:11 +00:00
Patrick Georgi
1cd374f563 Kconfig: Move rustccfg file to a more benign place
It's put in $(obj) now. Not sure if we'll need it, but there has been
some interest in rust support in coreboot, and removing support for it
would be more work than this, so let's just keep it around.

Change-Id: I532fde9625dbf7463752ef1af525b77d12676c93
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79342
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-30 17:46:15 +00:00
Patrick Georgi
1cc6c54d9f build system: Exempt make *config from strict symbol checks
The "config" targets exist to edit the .config file, and so they
should be more forgiving with invalid configs (that they'll convert
into valid configs on save). They will still emit warnings about
invalid symbols, but not exit with an error.

The regular build process still fails if the .config looks unexpected
(for example when there's an unknown config flag).

Change-Id: If427e075766c68d493dd406609f21b6bb27d1d74
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79298
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-30 17:45:50 +00:00
Matt DeVillier
132783baf8 Update amd_blobs submodule to upstream main branch
Updating from commit id 68ebd4b567f4 (2023-11-27):
  PCO: Update ABL to version CABLRV21080200

to commit id eb91266f01db (2023-11-29):
  MDN: Update mendocino SMU to 90.43.0

This brings in 1 new commit:
eb91266f01 MDN: Update mendocino SMU to 90.43.0

Change-Id: Iebc3d0ffe9874a84cac9cafc7b7b3514d251e4a5
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79315
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30 16:10:28 +00:00
Arthur Heymans
ea2e210548 soc/amd/genoa: Implement romstage
The only thing romstage needs to do is find cbmem_top.

TESTED: reaches ramstage.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic2837c4a2b0ec8dcd9dd99602f9c073999c36139
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76514
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-11-30 15:18:45 +00:00
Arthur Heymans
98a46fb2dd vendorcode/amd/opensil: Implement cbmem_top_chipset
Use an xPRF call to get the top of lower DRAM.

Organize Makefile to keep romstage/ramstage components separate.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I269663414f4d8e39eb218cd6348bfce7989a79f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76513
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-11-30 15:16:47 +00:00
Julius Werner
63ad72db6c Update vboot submodule to upstream main
Updating from commit id f2b01bf0:
2023-10-27 Julius Werner   firmware: Undeprecate VB2_RECOVERY_FW_GET_FW_BODY

to commit id ba7fd22d:
2023-11-27 Julius Werner   Makefile: Always link libdl

This brings in 54 new commits:
ba7fd22d Makefile: Always link libdl
1b30d195 sign_official_build: sign_update_payload with pkcs11
ca7a1427 sign_firmware: support loem key config
a9623573 sign_official_build: add keys to default key config
d41497dc sign_official_build: support loem key config
da2450db sign_official_build: support sign with .vbprik2 files
ee326142 getversion: Make reproducible
8aaf9e32 futility: fix a typo in help message of `read`
9ce505f4 futility: Fix incorrect warning about signing length
23a0ce4e scripts: add lib/keycfg.sh
2e34330b Makefile: Fix firmware build for FIRMWARE_ARCH=arm64
fd5937d1 tests/futility/test_show_and_verify: Add test cases for invalid data key
00aa0626 futility/cmd_vbutil_kernel: Drop --pad option for --verify
c661ab76 futility/cmd_show: Drop --pad option
c70511d7 tests/futility/test_show_and_verify: Add test cases for kernel vblocks
c9100f46 signer: Use compression flags stored in the metadata file
f1f3076f vboot: Add vb_keyb_from_private_key
c39a2fc1 host: support signing with pkcs11 key for vbprik2
c6d44076 vboot: merge reading function of vb2/vb21 private key
6b8e759f vboot: replace custom prefix "pkcs11" to "remote"
481440d0 futility: Prefer to flash over CCD instead of C2D2
1244c06f futility/cmd_dump_fmap: Print an error if FMAP header not found
cab69289 futility/cmd_show: Fix parseable output for kernel preamble flags
71a03dc6 futility/cmd_show: Make preamble parseable output consistent
bdac62a4 futility/cmd_show: Make 'show' return 0 for invalid kernel body
135df2d7 futility/cmd_show: Show parseable "keyblock::valid" for valid keyblock
37f37fcd futility/cmd_show: Fix output for firmware body signature
79c244ff tests/futility/test_show_and_verify: Add test cases for bios_brya_mp.bin
d4b6560f signer: Update mkfs.erofs pcluster value to 32K
f79a2432 futility/cmd_sign: Fix a space in usage text
a307fcb5 futility: updater: rename --ccd to --ccd_without_servod
6b9f66d3 futility: updater: Fix malloc overflow due to broken keyblock
a94a784c updater: update: Support multiple Servos without --servo_port
25875bef tests/futility: Add test cases for VBOOT_CBFS_INTEGRATION
5f8e3973 futility/cmd_show: Fix typo "metatadata"
9d30a01f futility: Trim trailing spaces in kernel config
c59794a6 sign_uefi: Support signing via pkcs11
68d4aa4b sign_uefi: Skip private key check if it's a pkcs11 URI
6b9d624b sign_uefi: Pass each key path separately
483f65e4 sign_official_build.sh: properly show errors on loem issues
516ee7bc sign_uefi: Use named args instead of positional
0eec8e25 vboot_reference-sys: Switch from Command to bindgen::Builder
46f5aab8 image_signing: support multiple release names
f13af139 sign_official_build: Sudo invocation within bits of android signing
3f165374 futility: updater: Add optional serial number argument to --ccd
64379cc6 sign_official_build: add --debug flag
7160bf9f 2lib: Fix relocation issue when compiling locally with musl libc
0e27cdff vboot_reference-sys: Add vboot_host.h
2c82e73c Override use_apksigner FLAGS
b43469c7 futility/cmd_show: Support --publickey FW_VBLOCK
0eb4da96 tests/futility: Update kern_preamble.bin as kernel_part.bin
68a03355 tests/futility: Move test_show_vs_verify.sh into test_show_and_verify.sh
8daf1474 tests/futility: Move 'futility show' tests to a separate file
34190e3d futility: Exit with error when metadata hash verification not supported
967aa462 firmware/2lib: Fix function comment for vb2api_get_firmware_size()

Change-Id: I58b231d53f433a396b1ea8cd4e0ddc49a310e385
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79313
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
2023-11-30 15:08:50 +00:00
Yidi Lin
a9a8b5e36c Update arm-trusted-firmware submodule to upstream master
Updating from commit id 88b2d8134:
2023-09-06 11:26:32 +0200 - (Merge "fix(scmi): add parameter for plat_scmi_clock_rates_array" into integration)

to commit id e7486343d:
2023-11-28 22:48:16 +0100 - (Merge changes from topic "xlnx_fitimage_check" into integration)

This brings in 451 new commits.

Change-Id: I75a89c6f0d60ccccd8ff42954416666dabef717f
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-11-30 15:08:01 +00:00
Yidi Lin
fe73a0e7b1 mb/google/corsola: Use fw_config to differentiate audio amps
Use fw_config to differentiate audio amps instead of the
kconfig option.

BRANCH=corsola
BUG=b:305828247
TEST=Verify devbeep in depthcharge console

Change-Id: I5f887f5e0d16dc14039fb12b636257d01339b2de
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79309
Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30 15:07:16 +00:00
Robert Chen
508296333b mb/google/nissa/var/quandiso: Add LTE only daughterboard support
Quandiso does not use DB_1C, replace the fw_config with LTE only
daughterboard.

BUG=b:312094048
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: Id7129e52d3733f62405f9d766f08563f05016c69
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79297
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Shawn Ku <shawnku@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30 15:06:27 +00:00
Matt DeVillier
22ac6f6b2c mb/google/galdos/var/lars: Implement touchscreen power sequencing
Since lars has two touchscreen options, we need to determine which (if
any) are present on a given device at runtime so that there are not
multiple ACPI touchscreen devices (as it makes Windows unhappy).
Implement power sequencing and runtime detection for both touchscreen
options.

TEST=build/boot Win11/Linux on google/lars, verify touchscreen detected
and functional under both OSes.

Change-Id: I49ccb29ec4589315a4abe3c0ea8fa76f97080bcd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-30 15:05:42 +00:00
Matt DeVillier
0733ee6514 mb/google/glados/var/lars: Add Melfas touchscreen
LARS has a Melfas touchscreen option, so add an entry for it. Adapted
from Chromium branch firmware-glados-7820.315.B, commit a26fe552569f
("Chell: Update DPTF parameters for CPU").

TEST=build/boot Linux on google/lars with Melfas touchscreen, verify
functional.

Change-Id: Idecd572335d7d5d52e4f89e85ebf7f0c90f23751
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79310
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30 15:05:05 +00:00
Werner Zeh
722c0b7b21 mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1
The address space of possible SPD-EEPROMs 0x50..0x53 on the SMBus
interface is per default write-protected in FSP. This avoids that an
SPD-EEPROM on a DRAM module gets overwritten by the host.

On mc_ehl1, memory-down configuration is used and there is no SPD EEPROM
available. Nevertheless, there is a general purpose EEPROM on the same
address available which needs to stay writeable.

This patch disables the default-enabled write protect feature for the
SPD-EEPROM addresses just for mc_ehl1.

Test=Boot into Linux and make sure a write access into the EEPROM is
possible.

Change-Id: I6b0fcdbeb0dbf971cfdceb70d6f4845765a3bdb6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-11-30 15:03:33 +00:00
Weimin Wu
fd1c2f488f mb/google/nissa/var/anraggar: Add OV13B10 MIPI camera device
Enable MIPI camera for anraggar project.

Sensor: OV13B10-GA5A
Driver: DW9714V
EEPROM: GT24P64E

Ref to SCH, use MIPI 4-lane serial output interface.

BUG=b:309518095
TEST=Google Camera app working

Checking log with:
coreboot log:
\_SB.PCI0.I2C2.CAM0: Intel MIPI Camera Device I2C address 036h
\_SB.PCI0.I2C2.VCM0: Intel MIPI Camera Device I2C address 0ch
\_SB.PCI0.I2C2.NVM0: Intel MIPI Camera Device I2C address 050h

kernel log:
kernel: [    6.140429] intel-ipu6-isys intel-ipu6-isys0: bind ov13b10 11-0036 nlanes is 4 port is 1
cros_camera_service[4755]: Read camera eeprom from /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom
cros_camera_service[4755]: Probing media device '/dev/media0'
cros_camera_service[4755]: Probing sensor 'ov13b10 11-0036' (v4l-subdev17)
cros_camera_service[4755]: Found V4L2 sensor subdev on /sys/devices/pci0000:00/0000:00:15.2/i2c_designware.2/i2c-11/i2c-OVTIDB10:00/video4linux/v4l-subdev17

Change-Id: I6a82557c94203f24449588a6005abc53cc29ca76
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79163
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arec Kao <arec.kao@intel.corp-partner.google.com>
2023-11-30 15:02:29 +00:00
Weimin Wu
b667e27952 mb/google/nissa/var/anraggar: Enable CNVi Bluetooth
Intel CNVi WLAN's BT uses USB2 Port 10 inside the SOC,
and the relevant configuration needs to be modified in overridtre.cb.

BUG=b:304920262
TEST=lsusb
     ID 8087:0033 Intel Corp.
     rfkill list
     hci0:Bluetooth

Change-Id: Ibcae800836c17307bc133de5a91658f6dda5985c
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79055
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30 15:02:05 +00:00
Simon Yang
ae2f046484 mb/google/nissa/var/anraggar: Tune eMMC DLL values
Anraggar cannot boot into OS and kernel loading failure.
Update eMMC DLL values to improve initialization reliability

- Sending different speed TX/RX command/data signal to eMMC and check
  the response is success or not.
- Collecting every eMMC that use for the project
- Based on above result to provide a fine tune DLL values

BUG=b:308366637
TEST=Cold reboot stress test over 2500 cycles

Change-Id: I9ec3cc23000301aa72aed96e74b63114623c4fc2
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78851
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-30 15:01:43 +00:00
Arthur Heymans
0832e6790d vendorcode/amd/opensil/genoa: Implement console callback
OpenSIL has an API to call back into the host firmware to print to the
console.

These could be moved to a common directory when there are more openSIL
implementations to see if it is actually common.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I208eea37ffde64a2311cb9f51e2bcd1ac3dbad4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-11-30 15:00:42 +00:00
Daniel Peng
49d1cf9d49 mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values
As customer demand, it is necessary to set MSR Package Power Limit-1 to 17W for the DTT setting to optimize performance.

The PL1 value (17W) suggested by the thermal team which is different from the reference code(PL1=15W).

BUG=b:312321601
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
     Built and booted into OS, and confirm MSR PL1=17W correctly.

Change-Id: If7874d26038118c5605cf0721c30e681b45123fe
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79335
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30 08:14:19 +00:00
Subrata Banik
38ab95ba5a mb/google/brya: Centralize SOC_INTEL_STORE_ISH_FW_VERSION config
This patch moves the SOC_INTEL_STORE_ISH_FW_VERSION config from the
Nissa baseboard to BOARD_GOOGLE_BRYA_COMMON. This allows all baseboards
to retrieve the ISH version and store it into memory.

Ensure SOC_INTEL_STORE_ISH_FW_VERSION is enabled only for platforms
with ISH support (DRIVERS_INTEL_ISH).

Additionally, the dedicated SOC_INTEL_STORE_ISH_FW_VERSION config
selection for the Nissa baseboard is no longer needed.

BUG=b:280722061
TEST=Able to build and boot google/marasov.

Change-Id: I99dab43ae4e13869b7f8797a9c4014f60e38a595
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79338
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-30 05:55:56 +00:00
Kun Liu
f281de82a7 mb/google/rex/var/screebo: Change GPP_B14 from NC to NF
Change GPP_B14 from NC to NF

BUG=b:272447747
TEST=enable usb OC2 function to ensure USBA work normal

Change-Id: Ie0f112bcf183870869d0c1b9a223d4231600a300
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-11-29 15:15:14 +00:00
Shelley Chen
ea9248e9fb mb/google/brox: Fix configuration for TPM
On Brox, TPM is using i2c4 and GPP_E2, so modifying the Kconfig to
reflect this.  Also, fixing up the TPM entry in the device tree.
Making sure that the GPIO for GSC_PCH_INT_ODL is set correctly.

BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot

Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79102
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-11-29 06:54:24 +00:00
Srinivas Hegde
2d589cfc6c arch/x86/Makefile.inc: Do not pass CPPFLAGS to linker
We seem to be passing CPPFLAGS to linker in x86 arch
ramstage. This is superflous as these are only meant
to be compiler flags and should not be passed to the
linker.

Change-Id: Ia3cd51be6be252aa796191cf0d2cd91d393c8878
Signed-off-by: Srinivas Hegde <srinivashegde@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-11-29 00:33:13 +00:00
Karthikeyan Ramasubramanian
892711fd77 soc/amd/cezanne: Move PSP_VERSTAGE_MAP_ENTIRE_SPIROM config
Select PSP_VERSTAGE_MAP_ENTIRE_SPIROM in Cezanne Kconfig instead of
common Kconfig.

BUG=None
TEST=Build BIOS image and boot to OS in dewatt.

Change-Id: I476971700824fed06d17000001afc075105fa1ee
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79306
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-28 16:49:09 +00:00
Karthikeyan Ramasubramanian
b6ab7baa38 soc/amd/common/psp_verstage: Make SPI ROM mapping configurable
Earlier entire SPI ROM was mapped to memory. With limited TLB resources
in PSP, this approach hit the limit on systems using 32 MiB SPI ROM.
Therefore regions in SPI ROM were mapped on need basis. This works well
on Picasso, Mendocino and Phoenix SoCs. But unfortunately this causes
boot hangs in Cezanne SoC. Add a configuration to map the entire SPI ROM
and enable it in Cezanne SoC. For other SoCs, keep the configuration
disabled so that only the required SPI ROM region is mapped.

BUG=b:309690716
TEST=Build and boot to OS in both Dewatt and Skyrim.

Change-Id: I166ac7b50b367c067e1a743fc94686e69dd07844
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-11-28 16:48:49 +00:00
Matt DeVillier
132b5a4262 Update amd_blobs submodule to upstream main branch
Updating from commit id e4519efca746 (2023-11-15):
  Revert "picasso: Update PSP binaries to release 0.8.13.7B"

to commit id 68ebd4b567f4 (2023-11-27):
  PCO: Update ABL to version CABLRV21080200

This brings in 1 new commit:
68ebd4b567 PCO: Update ABL to version CABLRV21080200

Change-Id: I4cf528c2d2489782758d2e16ea9201324c466919
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-28 16:15:13 +00:00
Martin Roth
50a3d6fcd8 soc/amd/genoa: Add openSIL to Genoa Kconfig
Select opensil & opensil_genoa. This enables openSIL for Genoa, allowing
the build to be tested.

Change-Id: I18379f311a56ff3f8b68d3c9a07a4f59de2d90b2
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-11-28 13:17:53 +00:00
Arthur Heymans
791ce58e6e vendorcode/amd: Hook up opensil
OpenSIL has a native buildsystem using meson and configuration mechanism
using kconfiglib.

To be able to use the coreboot toolchain with opensil, meson crossfiles
are used, which get generated by coreboot makefiles.

Configuration of opensil is done in a similar fashion with a template
defconfig after which kconfiglib is called to generate headers.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ide2d181914116119dfd37b1511d89ea965729141
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76511
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-11-28 13:17:13 +00:00
Naresh Solanki
1d6eeff171 acpi: Enable 64bit ECAM resource
Adjust ACPI DSDT to support ECAM resource above 4GB by modifying the PCI
ECAM Resource Consumption settings. The changes include specifying a
QWordMemory resource template, accommodating non-cacheable, read-write
attributes, and adjusting the address range.

Change-Id: Idb049d848f2311e27df5279a10c33f9fab259c08
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-27 21:10:41 +00:00
Leo Chou
16875ec8e3 mb/google/brya/var/taeko: Generate SPD IDs for 2 new memory parts
Add taeko new supported memory parts in mem_parts_used.txt, generate
spd-3.hex for these parts.

1. Samsung       K4UBE3D4AB-MGCL
2. Micron        MT53E1G32D2NP-046 WT:B

BUG=b:312363368
TEST=Use part_id_gen to generate related settings

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I221ad3f490f24b43fe1ccd211014787eab5d1038
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
2023-11-27 14:48:20 +00:00
Keith Hui
b4a8937045 mb/asus/p8z77-m_pro: Drop useless early init code
Drop code that puts Super I/O into config mode, select serial device,
then leave config mode right away having done nothing.

I'll also take this chance to revise its #includes based on
include-what-you-use results.

Change-Id: I304fc1610740375b59121b6b8784122440795838
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73693
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-27 14:41:29 +00:00
Keith Hui
5cf4628f4f mb/asus/p8z77-m: Properly configure early serial
Board was not producing serial output until well into ramstage.

To fix, select SUPERIO_NUVOTON_COMMON_COM_A Kconfig to tell
nuvoton_enable_serial() to route serial port A signals to the outside,
not GPIO8x.

TEST=Full native raminit debug log received over serial by minicom.

Change-Id: I376a79dd76ffa5f4d47e7c0cb53680e173e1ad78
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79222
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-11-27 14:39:23 +00:00
Kapil Porwal
642b789e70 mb/google/rex/var/screebo: Enable BT audio offload config
Enable BT audio offload of ALC1019_ALC5682I_I2S based on fw_config.

BUG=b:299510759
TEST=Build and boot to Screebo. Verify the config from serial logs.

w/o this CL -
```
[SPEW ]  ------------------ CNVi Config ------------------
[SPEW ]  CNVi Mode        = 1
[SPEW ]  Wi-Fi Core       = 1
[SPEW ]  BT Core          = 1
[SPEW ]  BT Audio Offload = 0
[SPEW ]  BT Interface     = 1
```

w/ this CL -
```
[SPEW ]  ------------------ CNVi Config ------------------
[SPEW ]  CNVi Mode        = 1
[SPEW ]  Wi-Fi Core       = 1
[SPEW ]  BT Core          = 1
[SPEW ]  BT Audio Offload = 1
[SPEW ]  BT Interface     = 1
```

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I6c713752f3f0bf58b5ebd78b904e773fdbf16e06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77755
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-27 12:57:47 +00:00
Tyler Wang
64c9520b0c mb/google/nissa/var/craask: Enable PIXA touchpad
Add PIXA touchpad for variants of craask.

BUG=b:310489697
TEST=build craask firmware and test with PIXA touchpad

Change-Id: I7e68a44eb3d639eaadb5b7b9cb5a6955fd059eeb
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-27 02:15:44 +00:00
Patrick Georgi
41419d9c30 util/kconfig: Import some more of Linux's build infra
cmd and cmd_conf_cfg are necessary for `make menuconfig`
and `make nconfig`.

Change-Id: Ie16ef31a8e0137f3fd4129fb73ca6ef4669173cc
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79264
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-27 00:02:09 +00:00
Felix Singer
0b82a2e370 doc/releases/4.22: Replace unicode chars with ASCII
Change-Id: I0b8419a8ad01d711362733e02ace89c48d2893b2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2023-11-26 23:46:18 +00:00
Patrick Georgi
786292a0fc libpayload/unit-tests: Rename ARCH_BIG_ENDIAN to ARCH_MOCK_BIG_ENDIAN
This fixes commit 12ae850dfc which used the wrong symbol, and previous
versions of Kconfig didn't notice.

Change-Id: I7145fd81a30a1455a6dd2c7f24564956a116d180
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79263
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-25 16:00:19 +00:00
Patrick Georgi
0eab62b9cf util/kconfig: Uprev to Linux 6.6's kconfig
Upstream reimplemented KCONFIG_STRICT, just calling it KCONFIG_WERROR.
Therefore, adapt our build system and documentation. Upstream is less
strict at this time, but there's a proposed patch that got imported.

TEST=`util/abuild/abuild -C` output (config.h and
config.build) remains the same. Also, the failure type fixed in
https://review.coreboot.org/c/coreboot/+/11272 can be detected,
which I tested by manually breaking our Kconfig in a similar way.

Change-Id: I322fb08a2f7308b93cff71a5dd4136f1a998773b
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-25 14:51:41 +00:00
Patrick Georgi
47282a90de tree wide: Rename VBOOT_MEASURED_BOOT* to TPM_MEASURED_BOOT
This follows commit c79e96b4eb which did the rename across the tree
except in these places. Remove the flag from CHROMEOS abuild builds
because it never really belonged there.

Change-Id: If98fa27f64d6b676d3edf68ba6fbaacf7ac422e4
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79258
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-25 13:55:22 +00:00
Patrick Georgi
b6954fa16f configs: Drop reference to USE_CANNONLAKE_FSP_CAR
This follows commit 5e8c906 which removed the symbol. Since Kconfig
is going to become more strict about unknown symbols, fix it.

As the config file's name indicates that its sole purpose is to test
integration of FSP's CAR, just drop the configuration altogether.

Change-Id: Idde7bf590c935a83e8f85f7d0a8e4b6954702319
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-11-25 13:55:09 +00:00
Patrick Georgi
37626f2aae configs: Rename UART_DEBUG to INTEL_LPSS_UART_FOR_CONSOLE
This follows commit a96e66a76f which did the rename across the tree
except here. Since Kconfig is going to become more strict about unknown
symbols, fix it.

Change-Id: I3b855085d4be13622e8f38ff651d576e719b682c
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79256
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-25 13:55:01 +00:00
Patrick Georgi
b667ce6382 configs: Drop references to MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
This follows commit 6615c6eaf7 which removed the symbol. Since Kconfig
is going to become more strict about unknown symbols, fix it.

Change-Id: I7b7f2e4c0774919a55083f7c5348f2b5031c8287
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-25 13:54:52 +00:00
Patrick Georgi
bbaa1f00f3 configs: Drop references to CPU_QEMU_X86_SMMLOADERV2
This follows commit 88407bcd which removed the symbol. Since Kconfig
is going to become more strict about unknown symbols, fix it.

Change-Id: I19d26de8003c51437ea62e04083a14c3587a4665
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79254
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-11-25 13:54:43 +00:00
Patrick Georgi
6619afac04 configs: Drop references to CPU_QEMU_X86_PARALLEL_MP
This follows commit e2d291b5 which removed the symbol. Since Kconfig
is going to become more strict about unknown symbols, fix it.

Change-Id: I838f98d07fc0448dda6c02b58d7c5639992c77a2
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79253
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-25 13:54:34 +00:00
Patrick Georgi
06fb738497 configs: Rename PXE_SERIAL_CONSOLE to IPXE_SERIAL_CONSOLE
This follows commit 238ff1e9c which did the rename across the tree
except here. Since Kconfig is going to become more strict about unknown
symbols, fix it.

Change-Id: Ic31b8ae353ec07e8b8adab46b604365be4be44d9
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-11-25 13:54:27 +00:00
Martin Roth
c0461f4a51 Docs/releases: Finalize 4.22/4.22.01 release notes
Now that the 4.22 release tag has been added to git, update the release
notes with the final statistics and wording.

We also decided to add a fix submitted immediately after the 4.22
release was tagged into the release package and do a point release.

This also adds an expected date for the next release

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iae9653a275fcc1d11efbb88e12676f332be0a5dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79147
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-25 03:05:11 +00:00
Elyes Haouas
2731fa619b crossgcc: Upgrade GCC from 11.4.0 to 13.2.0
Changelogs:
  * https://gcc.gnu.org/gcc-12/changes.html
  * https://gcc.gnu.org/gcc-13/changes.html

Porting guides:
  * https://gcc.gnu.org/gcc-12/porting_to.html
  * https://gcc.gnu.org/gcc-13/porting_to.html

Change-Id: I4f2ed4de4811abaa13528906de71eee29a8f2910
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-24 23:31:03 +00:00
Arthur Heymans
5ee1d23bcc soc/amd/genoa: Hook up microcode updating
Also update the regular expression to find the genoa blobs.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Iba0109c049019a22cba1e0358cedbd9c198c6569
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-24 17:01:10 +00:00
Patrick Georgi
0a48cfa3a5 util/kconfig: Uprev to Linux 6.5's kconfig
TEST=`util/abuild/abuild -C` output (config.h and config.build) remains
the same

Change-Id: If717d064d87b0045f276a4ee963db0a62230f5d8
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-24 16:50:27 +00:00
Patrick Georgi
34b149b508 util/kconfig: Uprev to Linux 6.4's kconfig
TEST=`util/abuild/abuild -C` output (config.h and config.build) remains
the same

Change-Id: Idbcd88165271b58ba3697c66df447af0b8b57b1b
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79181
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-24 16:50:18 +00:00
Patrick Georgi
54cec70650 util/kconfig: Uprev to Linux 6.3's kconfig
Minor bugfix, plus stuff that doesn't really affect us.

TEST=`util/abuild/abuild -C` output (config.h and config.build) remains
the same

Change-Id: I0af0c2ae4cb11bb58457830ffcd8bb8c2422a3d1
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79180
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-24 16:50:09 +00:00
Patrick Georgi
7eab8ef8b7 util/kconfig: Uprev to Linux 6.2's kconfig
The upstream build system uses a newly introduced function `read-file`,
so copy that in from Linux 6.2.

TEST=`util/abuild/abuild -C` output (config.h and config.build) remains
the same

Change-Id: Ic100bf189ebd3eaa0eb26904ae8602910329a180
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-24 16:50:00 +00:00
Patrick Georgi
7f93aa4919 util/kconfig: Uprev to Linux 6.1's kconfig
This also cleans up our patch queue.

TEST=`util/abuild/abuild -C` output (config.h and config.build) remains
the same

Change-Id: I79159130ba3515ede59e9fb9fbf087e2ed76257a
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-24 16:49:51 +00:00
Scott Chao
f47e85fc72 mb/google/nissa: make GPP_F17 edge triggered to avoid spamming EC
In nissa platform, we configured GPP_F17 as SCI+APIC to wake the system
and also generate IRQ to the IOAPIC. Currently, we set GPP_F17 to level
triggered and it causes AP (Application Processor) to keep sending
GET_NEXT_EVENT to EC during resume from suspend by connecting AC.

So we change GPP_F17 to edge triggered to avoid this condition.

BUG=b:308716748
TEST=Original failure rate was 7 out of 10 times and it reduced to
0 out of 60 times on six joxer systems.

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I3ceb1dfce46376a6a9a8c6cb6d691d818a0a42ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79244
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-24 08:31:41 +00:00
Felix Singer
59d27ec1c7 util/docker/archlinux: Extend the environment with packages and configs
Add more packages which are useful for a coreboot development and build
environment and also make neovim the default editor.

Change-Id: Ied09a9b9500d85348fc9c3862247bd8b85e50b54
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77724
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-24 04:33:36 +00:00
Yi Chou
1739c99efe libpayload: Move ttb_buffer to a standalone section
When cleaning the sensitive data in the memory, we will want to prevent
zero out the content of tbb_buffer. Move the ttb_buffer to a standalone
section will simplify the problem.

BUG=b:248610274
TEST=emerge-cherry libpayload
BRANCH=none

Change-Id: I610276cbe30552263d791860c15e5ad9a201c744
Signed-off-by: Yi Chou <yich@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79078
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-23 17:53:22 +00:00
Arthur Heymans
f9b6f2d355 arch/riscv/romstage: Start from assembly
Without this it would use the exception handler from the previous
stage.

Change-Id: I79d875aca6cd0cffe482e4ebb5f388af0adf6aed
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68840
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-23 17:50:55 +00:00
Arthur Heymans
62f788e244 acpigen.c: Add resource consumer functions for mmio
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Id9e4adcd976e1f56ef7f502d9df16dbefce95c3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79217
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-23 14:42:59 +00:00
Robert Chen
39b19f270c mb/google/nissa/var/quandiso: Disable un-used C1 port by daughterboard
Probe usb ports by FW_CONFIG setting to disable C1 port on quandiso new daughterboard without C1 port.

BUG=b:312094048
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I6f702f60c772176e80b3452bf957d10625564102
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79173
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-23 13:11:29 +00:00
Keith Hui
e94d7d8264 mb/asus/p8z77-m: Ensure RAM stays powered in ACPI S3 suspend
Enable 3VSBSW# in NCT6779D super I/O like other variants in the family,
needed to maintain power to memory during S3 suspend. Without it
resuming totally fails.

(Enabling it in devicetree is OK; it needs not be done in early
board init.)

TEST=Resuming from S3 works.

Change-Id: Ia8059b2a263ab5c459e54685f046eeb913776473
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78205
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kevin Keijzer <kevin@quietlife.nl>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-22 17:53:56 +00:00
Van Chen
bbb6d5d477 mb/google/nissa/var/craaskov: Add 6W and 15W DPTF parameters
The DPTF parameters were defined by the thermal team.
Based on thermal table in 290705146#comment17.

BUG=b:290705146
BRUNCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I02b4187000eec9990bf10a57875b23007f7bdd12
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79183
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-22 17:53:25 +00:00
Subrata Banik
4b5ab3e734 mb/google/rex: Enable FSP logo rendering for all Rex variants
This patch enables the FSP (Firmware Splash Screen) rendering feature
for all Rex variants, including chromeboxes like Ovis. This will allow
users to see the FSP logo during the boot process.

BUG=b:284799726
TEST=Verify that the FSP logo is displayed during the boot process on
an google/ovis chromebox.

Change-Id: I73d82e16f70ffdc8cb168506c86d9c4e9a92c38d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-22 17:52:49 +00:00
Tyler Wang
b1be5c2fff mb/google/rex/var/karis: Set pen detect pin to NC for non-stylus sku
Set pen detect pin to NC base on fw_config.

BUG=b:304680060
TEST=emerge-rex coreboot pass

Change-Id: Icf9171fca49cfed1a05a67ae7fc8d62b7e9630c9
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79213
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-22 17:52:20 +00:00
Felix Held
d26f5a103f soc/amd/genoa: add I2C support
The Genoa SoC has 6 I2C controllers. In order to support those, select
SOC_AMD_COMMON_BLOCK_I2C and implement the SoC-specific functions and
data structures needed by the common AMD I2C code. Since the common AMD
I2C code also reports if the controller is enabled or not in the SSDT,
change the corresponding DSDT code to use this information. In this
patch the I2C pad control registers don't get configured by coreboot yet
and we rely on ABL already having those set up correctly which seems to
be an assumption that the reference firmware is making too. PPR #55901
Rev 0.26 was used as a reference for the I2C controllers and the GPIO
pins being used.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iebc10de6ea5c6d441cff04e016dcec62405078c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-11-22 15:03:17 +00:00
Julius Werner
943a2c90d8 vboot: Add catchall recovery reason for unspecified phase 4 errors
The code for "phase 4" of firmware verification currently only sets a
recovery reason when there's an actual hash mismatch detected in
vb2api_check_hash_get_digest(). This is the most likely way how this
section of code can fail but not the only one. If any other unexpected
issue occurs, we should still set a recovery reason rather than just
reboot and risk an infinite boot loop.

This patch adds a catchall recovery reason for any error code that falls
out of this block of code. If a more specific recovery reason had
already been set beforehand, we'll continue to use that -- if not, we'll
set VB2_RECOVERY_FW_GET_FW_BODY.

Change-Id: If00f00f00f00aa113e0325aad58d367f244aca49
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78866
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-22 01:50:47 +00:00
Julius Werner
0712851ca3 google/*: Clean up Kconfg board selection for Google MTK boards
This patch tries to standardize and simplify the Kconfig option layout
for Google boards with MediaTek SoCs and align them to the scheme used
with other Arm-based Google boards.

Change-Id: I40880e7609ba703d0053ad01da742871e54d4e7a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79063
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
2023-11-22 01:50:24 +00:00
Julius Werner
53b79bef61 google/*: Clean up Kconfig board selection for non-MTK Google Arm boards
This patch unifies and simplifies the Kconfig selection model for the
Gru, Herobrine, Trogdor and Veyron boards according to the model
discussed in CB:78972.

Also add missing license headers to two Kconfig files while I'm here.

Change-Id: If679a05afd10869afba9c2a33b54862e102b5f40
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79022
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-22 01:49:57 +00:00
Felix Singer
6f74bc6028 mb/hp/280_g2: Restore comments documenting root port devices
While transitioning the devicetree to make use of the chipset
devicetree, commit 3b5b9f4c54 ("mb/hp/280_g2: Make use of the chipset
devicetree") removed useful comments documenting the endpoints of the
root ports. Restore them.

Change-Id: I178cb472a8f40baaccc30514689bda2730dfa9dc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-11-21 21:42:39 +00:00
Martin Roth
8956458bdc Update fsp submodule to upstream master
Updating from commit id 481ea7c:
2023-09-19 15:21:38 -0700 - (Move to RaptorLakeFspBinPkg.dec)

to commit id bb12f17:
2023-10-31 16:00:43 +0800 - (Elkhart Lake MR7 FSP)

This brings in 5 new commits:
bb12f17 Elkhart Lake MR7 FSP
0d6bf96 Elkhart Lake MR7 FSP
88845b6 IoT ADL-S MR6 (4115_09) FSP
8c99965 IoT ADL-P MR5 (4115_09) FSP
6c549ee IoT ADL-N MR2 (4282_00)

Change-Id: I9fe65d830061c93ceac549dc7f41e7a98646a0a3
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-21 14:29:26 +00:00
Yi Chou
582c2a7980 libpayload: Add dma_allocator_range()
Some sensitive data may remain DMA buffer, we will want to zero out
everything on the DMA buffer before we jump into the kernel to
prevent leaking sensitive data into the kernel.

To accomplish that, we will need this function to get the range of
memory that can be allocated by the dma allocator.

BUG=b:248610274
TEST=emerge-cherry libpayload
BRANCH=none

Signed-off-by: Yi Chou <yich@google.com>
Change-Id: I8f3058dfd861ed44f716623967201b8cabe8d166
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-11-21 13:50:53 +00:00
Subrata Banik
cbbfd68481 soc/intel/mtl: Keep SOC_INTEL_COMMON_BASECODE_RAMTOP for non-ChromeOS
This patch guarantees that non-ChromeOS platforms continue to enable
early caching.

ChromeOS devices, on the other hand, control this configuration through
the motherboard configuration based on the underlying SoC.

BUG=b:306677879
TEST=Enable SOC_INTEL_COMMON_BASECODE_RAMTOP for google/rex.

Change-Id: I412b2b6a807dc0f5f2632f0fbd56bd37689dead3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-11-21 13:41:10 +00:00
Subrata Banik
5578d91257 mb/{google,intel}/{rex,mtlrvp}: Enable SOC_INTEL_COMMON_BASECODE_RAMTOP
This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` config
option for select mainboards, as not all board variants may want to
enable this config due to underlying SoC dependencies.

Mainboards that attempt to enable early caching have exhibited soft
hangs while switching between pre-RAM and post-RAM phases. This patch
allows mainboards to choose to enable this option without enabling
it by default (which could cause boot hangs).

Furthermore, it reorganizes the configuration options under
BOARD_GOOGLE_BASEBOARD_REX in alphabetical order for better readability.

BUG=b:306677879
TEST=Enable SOC_INTEL_COMMON_BASECODE_RAMTOP for google/rex and
intel/mtlrvp.

Change-Id: If380c2ecbee4f6437c3d58bfb55be076a4902997
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-11-21 13:40:34 +00:00
Terry Chen
3d9a26e7a9 mb/google/nissa/var/joxer: Add speaker ldo config
Follow thermal validation, add ldo output select for speaker.

BUG=b:297298847
TEST=emerge-nissa and deploy to DUT to verify audio functionality.

Change-Id: Ie68f2b35f024b4dd066d831ae8fd5a662d407753
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-21 13:39:45 +00:00
Matt DeVillier
5b4bbe556a mb/google/byra/var/*: Set LAN device type back to pci
This partially reverts commit f493857c9b ("mb/google/brya/var/*: Set
dGPU/LAN/WLAN device type to generic"). Setting the LAN device type to
generic broke programming the LAN MAC address, so set it back to pci.

TEST=build/boot google/brya (osiris), verify LAN MAC address programmed
correctly.

Change-Id: I4fb43b7212e67b5c38724baad572860bc45b558e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79150
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-21 13:39:14 +00:00
Matt DeVillier
f03b8fc370 mb/google/puff/var/*: Set LAN device type back to pci
This mostly reverts commit 6c705e766f ("mb/google/puff/var/*: Set
LAN/WLAN device type to generic"). Setting the LAN device type to
generic broke programming the LAN MAC address, so set it back to pci.

TEST=build/boot google/puff (wyvern), verify LAN MAC address programmed
correctly.

Change-Id: I558ae6dc1366d5a8a22e0383d7d597d15159df03
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-21 13:38:44 +00:00
Felix Singer
c08461dfd4 util/crossgcc: Update CMake from 3.26.4 to 3.27.7
Change-Id: I4dbe9b7a05171bb244ec1ebe6ce7d390a6373d61
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-21 13:38:14 +00:00
Naresh Solanki
18051b3dd2 acpi: Optimize enum acpi_tables layout
Arrange ACPI table enum in a vertical and alphabetized format.
This change aims to reduce conflicts between patches.

Change-Id: I192339df771d6a3ae67358fe46334fe2b216b974
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79099
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-20 22:09:27 +00:00
Patrick Rudolph
51518e585d nb/intel/sandybridge: Use SA devid to identify PC type
Instead of using MSR IA32_PLATFORM_ID read the SystemAgent device id
to figure out the PC type. This follows the BWG which suggest to not
use MSR IA32_PLATFORM_ID for system identification.

Tested: Lenovo X220 still boots.

Change-Id: Ibddf6c75d15ca7a99758c377ed956d483abe7ec1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78826
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-11-20 14:58:31 +00:00
Patrick Rudolph
8685205ad1 cpu/intel/model_206ax: Lock MSR_PP_CURRENT_CONFIG
Now that those registers are only written once set the lock bit to
protect it from runtime changes.

TEST: Lenovo X220 still boots.

Change-Id: I4c56a3cb322a0e75eb3dd366808068093928e10c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-11-20 14:55:58 +00:00
Patrick Rudolph
ea04a53e69 cpu/intel/model_206ax: Write MSRs in scope package only once
Write MSRs that are in scope package only once by checking for the BSP
bit. While this improves performance a bit it also has the benefit
that registers can be safely locked down without the need for
semaphores.

TEST: Lenovo X220 still boots.

Change-Id: I43f5d62d782466d2796c1df6015d43c0fbf9d031
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-11-20 14:55:20 +00:00
Jeremy Compostella
caa0c0e71a nb/intel/sandybridge: Fix unitialized variable issue
commit 1e9601c5ef ("nb/intel/sandybridge: Standardize MRC vs. native
SPD mapping API") introduced an uninitialized variable issue.

Change-Id: I41b081dc4c961acc04423067e29e0eabe5f17539
Found-by: Coverity CID 1524317
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79093
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-11-20 14:35:48 +00:00
Julius Werner
74905117bd Update vboot submodule to upstream main
Updating from commit id c59794a6:
2023-11-02 Nicholas Bishop sign_uefi: Support signing via pkcs11

to commit id f2b01bf0:
2023-10-27 Julius Werner   firmware: Undeprecate VB2_RECOVERY_FW_GET_FW_BODY

This brings in 66 new commits:
c59794a6 sign_uefi: Support signing via pkcs11
68d4aa4b sign_uefi: Skip private key check if it's a pkcs11 URI
6b9d624b sign_uefi: Pass each key path separately
483f65e4 sign_official_build.sh: properly show errors on loem issues
516ee7bc sign_uefi: Use named args instead of positional
0eec8e25 vboot_reference-sys: Switch from Command to bindgen::Builder
46f5aab8 image_signing: support multiple release names
f13af139 sign_official_build: Sudo invocation within bits of android signing
3f165374 futility: updater: Add optional serial number argument to --ccd
64379cc6 sign_official_build: add --debug flag
7160bf9f 2lib: Fix relocation issue when compiling locally with musl libc
0e27cdff vboot_reference-sys: Add vboot_host.h
2c82e73c Override use_apksigner FLAGS
b43469c7 futility/cmd_show: Support --publickey FW_VBLOCK
0eb4da96 tests/futility: Update kern_preamble.bin as kernel_part.bin
68a03355 tests/futility: Move test_show_vs_verify.sh into test_show_and_verify.sh
8daf1474 tests/futility: Move 'futility show' tests to a separate file
34190e3d futility: Exit with error when metadata hash verification not supported
967aa462 firmware/2lib: Fix function comment for vb2api_get_firmware_size()
f2b01bf0 firmware: Undeprecate VB2_RECOVERY_FW_GET_FW_BODY
ef6d02df futility/vb2_helper: Add missing newline for error messages
886d13d7 PRESUBMIT: switch to cros format
ac2e1a75 host/lib: Decouple openssl headers from HOSTLIB
86ec05f7 futility: updater: Add help info for --quirks
2850244e futility: updater: Abort if the unlock_csme_* is used on a locked device
f1b5c88d devkeys: delete old unused firmware_bmpfv.bin
4444c5fe crossystem: Fix tpm_fwver for fwid < 12935
98ef339f 2lib: Prevent overwriting the value of fw_vboot2
c7517eb4 make_dev_ssd: support ChromeOS Kdump
8e3462cc tlcl: Increase the TPM_BUFFER_SIZE
740a2966 vboot_reference: Drop 'host' usage for 'internal' in flashrom.h
57877a44 vboot: Remove comments about physical dev switch
3401d16c 2lib: Fix typos, comments and formats
fdf52d45 scripts/: Drop deprecated {g,s}et_gbb_flags.sh scripts
bf76e9ee 2lib: Output the correct kernel_version
1ac4663e make_dev_firmware.sh: update pattern for matching wp status
c57ab9f7 2lib: Add recovery reason VB2_RECOVERY_WIDEVINE_PREPARE
e094ba31 tlcl: Reduce the variants of TPM2B
b047600d sign_official_build: support key config for pkcs11
f8712b73 vboot: support signing with pkcs11 private key
17fe786f strip_boot_from_image.sh: sfill fast
6c856cd3 futility/updater: Fix EC software write protection logic
1dc5a421 futility: update: Deprecate --unlock_me by --quirk unlock_csme_nissa
f0d88587 futility: update: Refactor the 'unlock ME' quirk(s)
81429ee9 futility: update: Do not update RO when the AP RO is locked
a3beb737 futility: update: Revise the ordering or quirks
2c1844fa futility: update: Remove unused quirk 'unlock_wilco_me_for_update'
75530d32 tests/futility: Test with new signer_config.csv based firmware updater
cba649fa 2lib: Expose 2hmac
ab015448 2lib: Refactor hmac to vb2_hmac_calculate
3545f8b4 Revert "sign_uefi: Remove exception catching"
55f625a9 dump_fmap: Add offset and size to flash_ec format output
a27ee336 keygeneration: add shellcheck source statements to help linting
055f9aa2 keygeneration: replace_recovery_key.sh: make minios key optional
6cb8ab60 scripts: delete unused values kernel command line
1f76c38b vboot: Drop phone recovery support
ccf6b037 scripts: Legacy fix for set_gbb_flags.sh
8f03069e futility: Add basic README.md
88963df8 utility: Query platform wp status with futility
6c3817d2 utility: Drop cros_alias technical debt in dev_debug_vboot
df85f512 scripts: Drop cros_alias technical debt in make_dev_firmware.sh
7395cd68 futility/updater_utils.c: Match on EC path to prepare for split
52518415 crossystem: Recover corrupted RW_NVRAM on flash writes
81f9ddaf futility/cmd_gbb_utility.md: Add basic GBB subcmd doc
c4995268 futility/: Fix define confusion
69dab5a6 crossystem: Avoid writing duplicate entries to RW_NVRAM
6c37b520 Revert "crossystem: stop supporting legacy chromeos_acpi driver"

Change-Id: Ic7ecdabcdd26df349b8abf1c5a77c806facfe1d8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78865
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-20 14:35:00 +00:00
Nick Vaccaro
0863f7cdb2 mb/goog/brya/var/brya0/skolas: Disable HPS GPIOs if HPS_ABSENT
Check FW_CONFIG and disable gpios for HPS if HPS_ABSENT for skolas
and brya0 variants.

BUG=b:311740746
BRANCH=firmware-brya-14505.B
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas
to kernel and verify via "cbmem -c | grep HPS".

Change-Id: I8cbe4f40c41f1d06e8f511c3e88c05984566d441
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-20 14:34:33 +00:00
Nick Vaccaro
6615c60fd5 mb/goog/brya/var/brya0/skolas: Disable LTE GPIOs if LTE_ABSENT
Check FW_CONFIG and disable gpios for LTE if LTE_ABSENT for skolas
and brya0 variants.

BUG=b:311459627
BRANCH=firmware-brya-14505.B
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas
to kernel and verify LTE gpios are disabled via "cbmem -c | grep LTE".

Change-Id: I3f3bc2b536babf71cc484cce02f96f47707f729c
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79122
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-20 14:34:15 +00:00
Nick Vaccaro
f6113ececc mb/goog/brya/var/skolas: sync slolas overridetree with brya0
Skolas uses brya0 schematic, so override tree should be almost the same
for brya0 and skolas.  This change sync's the skolas overridetree.cb
with brya0's overridetree.cb.

BUG=b:311722825
BRANCH=firmware-brya-14505.B
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to
kernel.

Change-Id: I14a2ed803a8ffb8614018af587c66034fb724b38
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-20 14:33:39 +00:00
Maximilian Brune
b57f87fb9a sbom/Makefile.inc: Change GOPATH
This changes the path where go installs its packages.
Now the packages are not installed in the users home directory anymore.
This solution is not perfect though, since offline build are still not
possible, because go will fetch the packages at build time.

-modcacherw will create the go files with rw permissions, otherwise
coreboot is not able to delete the files afterwards (make distclean).

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I2a35369628454057ea4758cd1225e57f07cb71c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-20 14:32:54 +00:00
Yidi Lin
ec1a880c51 mb/google/geralt: Remove unnecessary delay for MIPI panel
According to eDP panel datasheet[1], the eDP panel needs 0 <= x <=200ms
delay after VDD powering on. The MIPI panel[2] does not need this delay.
Move this delay to eDP path.

[1] NE135FBM-N41 V8.0 Product Spec_P2 20191025.pdf
[2] B5 TV110C9M-LL0 Product Specification Rev.P0

BRANCH=none
BUG=none
TEST=check FW screen
TEST=check timestamp
Before:
  60:device initialization                             696,422 (1)
  15:starting LZMA decompress (ignore for x86)         696,587 (165)
  16:finished LZMA decompress (ignore for x86)         696,675 (88)
  17:starting LZ4 decompress (ignore for x86)          1,340,226 (643,551)

After:
  60:device initialization                             724,259 (1)
  15:starting LZMA decompress (ignore for x86)         724,425 (166)
  16:finished LZMA decompress (ignore for x86)         724,512 (87)
  17:starting LZ4 decompress (ignore for x86)          1,168,176 (443,664)

Change-Id: I92bca5ec8269f4bad4dfab4ee193cdb5665de233
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79109
Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-20 09:22:04 +00:00
Jon Murphy
193e9e8529 cross-repo-cherrypick: Update downstream branch
ChromeOS has switched to using the main branch, update accordingly.

BUG=b:294218930
TEST=None

Change-Id: I31f67ef4fb175a4e4896b5bed81d5ae1cdddb827
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79143
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-20 07:40:11 +00:00
Martin Roth
b558758554 Documentation/releases: Add 24.02 release notes template
In preparation for the upcoming release, add the template for the
24.02 release and update index.md.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I694142c31ba684e7b94640d55302b2440e25619a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79073
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-19 17:39:12 +00:00
Felix Held
a56ff9087b sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetree
Since the HD audio controller in the PCH are always on the same device
functions, the device operations can be statically assigned in the
devicetree and there's no need to bind the host bridge device operations
to the PCI device during runtime via a list of PCI IDs.

TEST=Lenovo X220 still boots to Linux and audio still works

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I9bbbe9f4490dc6fb21174d63d1c8906d69ea3ee0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79118
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-18 16:36:46 +00:00
Felix Held
58a5374d5f sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetree
Since the PCIe root ports in the PCH are always on the same device
functions, the device operations can be statically assigned in the
devicetree and there's no need to bind the host bridge device operations
to the PCI device during runtime via a list of PCI IDs.

TEST=Lenovo X220 still boots to Linux and all PCIe devices on PCH are
visible and working.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I05bfe8db88fd54415f320f32ea147636ca4e0df8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-11-18 16:36:33 +00:00
Felix Held
61f22cff59 nb/intel/sandybridge: assign gma ops in chipset devicetree
Since the integrated GPU is always function 0 of device 2 on bus 0, the
device operations can be statically assigned in the devicetree and
there's no need to bind the host bridge device operations to the PCI
device during runtime via a list of PCI IDs.

TEST=Lenovo X220 still boots to Linux and graphics works in UEFI

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I20e387e626e19dc441aceda18451186d1e86cd5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79114
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-18 15:38:03 +00:00
Felix Held
4c4d1948ef nb/intel/sandybridge: assign host bridge ops in chipset devicetree
Since the host bridge is always function 0 of device 0 on bus 0, the
device operations can be statically assigned in the devicetree and
there's no need to bind the host bridge device operations to the PCI
device during runtime via a list of PCI IDs.

TEST=Lenovo X220 still boots to Linux

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Icf3d9f8cd2be2f8ef71fd9fdb5f005f3b683332e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79113
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-11-18 15:37:50 +00:00
663 changed files with 72665 additions and 9519 deletions

View File

@@ -1,21 +1,228 @@
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# git grep '^#define [^[:space:]]*__.*[^[:space:]]*__attribute__' | grep -v "vendorcode\|payloads\|util" | sed "s|.*:||;s|^#define \([^[:space:]]*__[^([:space:]]*\).*$| - '\1'|" | LC_ALL=C sort -u
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InsertBraces: false
InsertNewlineAtEOF: true
InsertTrailingCommas: None
IntegerLiteralSeparator:
Binary: 0
BinaryMinDigits: 0
Decimal: 0
DecimalMinDigits: 0
Hex: 0
HexMinDigits: 0
JavaScriptQuotes: Leave
JavaScriptWrapImports: true
KeepEmptyLinesAtTheStartOfBlocks: false
LambdaBodyIndentation: Signature
LineEnding: LF
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 1
NamespaceIndentation: None
ObjCBinPackProtocolList: Auto
ObjCBlockIndentWidth: 8
ObjCBreakBeforeNestedBlockParam: true
ObjCSpaceAfterProperty: true
ObjCSpaceBeforeProtocolList: true
PackConstructorInitializers: BinPack
PenaltyBreakAssignment: 10
PenaltyBreakBeforeFirstCallParameter: 30
PenaltyBreakComment: 10
PenaltyBreakFirstLessLess: 0
PenaltyBreakOpenParenthesis: 0
PenaltyBreakString: 10
PenaltyBreakTemplateDeclaration: 10
PenaltyExcessCharacter: 100
PenaltyIndentedWhitespace: 0
PenaltyReturnTypeOnItsOwnLine: 60
PointerAlignment: Right
PPIndentWidth: -1
QualifierAlignment: Left
ReferenceAlignment: Pointer
ReflowComments: false
RemoveBracesLLVM: false
RemoveSemicolon: false
RequiresClausePosition: OwnLine
RequiresExpressionIndentation: OuterScope
SeparateDefinitionBlocks: Leave
ShortNamespaceLines: 1
SortIncludes: Never
SortJavaStaticImport: Before
SortUsingDeclarations: Never
SpaceAfterCStyleCast: false
SpaceAfterLogicalNot: false
SpaceAfterTemplateKeyword: true
SpaceAroundPointerQualifiers: Default
SpaceBeforeAssignmentOperators: true
SpaceBeforeCaseColon: false
SpaceBeforeCpp11BracedList: false
SpaceBeforeCtorInitializerColon: true
SpaceBeforeInheritanceColon: true
SpaceBeforeParens: ControlStatementsExceptControlMacros
SpaceBeforeParensOptions:
AfterControlStatements: true
AfterForeachMacros: false
AfterFunctionDefinitionName: false
AfterFunctionDeclarationName: false
AfterIfMacros: false
AfterOverloadedOperator: false
AfterRequiresInClause: false
AfterRequiresInExpression: false
BeforeNonEmptyParentheses: false
SpaceBeforeRangeBasedForLoopColon: true
SpaceBeforeSquareBrackets: false
SpaceInEmptyBlock: false
SpaceInEmptyParentheses: false
SpacesBeforeTrailingComments: 1
SpacesInAngles: Never
SpacesInConditionalStatement: false
SpacesInContainerLiterals: false
SpacesInCStyleCastParentheses: false
SpacesInLineCommentPrefix:
Minimum: 1
Maximum: 1
SpacesInParentheses: false
SpacesInSquareBrackets: false
Standard: c++17
TabWidth: 8
UseTab: ForContinuationAndIndentation
...

View File

@@ -9,3 +9,7 @@ charset = utf-8
insert_final_newline = true
end_of_line = lf
trim_trailing_whitespace = true
[*.sh]
indent_style = space
indent_size = 2

36
.gitmodules vendored
View File

@@ -1,70 +1,70 @@
[submodule "3rdparty/blobs"]
path = 3rdparty/blobs
url = https://review.coreboot.org/blobs.git
url = ../blobs.git
update = none
ignore = dirty
[submodule "util/nvidia-cbootimage"]
path = util/nvidia/cbootimage
url = https://review.coreboot.org/nvidia-cbootimage.git
url = ../nvidia-cbootimage.git
[submodule "vboot"]
path = 3rdparty/vboot
url = https://review.coreboot.org/vboot.git
url = ../vboot.git
branch = main
[submodule "arm-trusted-firmware"]
path = 3rdparty/arm-trusted-firmware
url = https://review.coreboot.org/arm-trusted-firmware.git
url = ../arm-trusted-firmware.git
[submodule "3rdparty/chromeec"]
path = 3rdparty/chromeec
url = https://review.coreboot.org/chrome-ec.git
url = ../chrome-ec.git
[submodule "libhwbase"]
path = 3rdparty/libhwbase
url = https://review.coreboot.org/libhwbase.git
url = ../libhwbase.git
[submodule "libgfxinit"]
path = 3rdparty/libgfxinit
url = https://review.coreboot.org/libgfxinit.git
url = ../libgfxinit.git
[submodule "3rdparty/fsp"]
path = 3rdparty/fsp
url = https://review.coreboot.org/fsp.git
url = ../fsp.git
update = none
ignore = dirty
[submodule "opensbi"]
path = 3rdparty/opensbi
url = https://review.coreboot.org/opensbi.git
url = ../opensbi.git
[submodule "intel-microcode"]
path = 3rdparty/intel-microcode
url = https://review.coreboot.org/intel-microcode.git
url = ../intel-microcode.git
update = none
ignore = dirty
branch = main
[submodule "3rdparty/ffs"]
path = 3rdparty/ffs
url = https://review.coreboot.org/ffs.git
url = ../ffs.git
[submodule "3rdparty/amd_blobs"]
path = 3rdparty/amd_blobs
url = https://review.coreboot.org/amd_blobs
url = ../amd_blobs
update = none
ignore = dirty
[submodule "3rdparty/cmocka"]
path = 3rdparty/cmocka
url = https://review.coreboot.org/cmocka.git
url = ../cmocka.git
update = none
branch = stable-1.1
[submodule "3rdparty/qc_blobs"]
path = 3rdparty/qc_blobs
url = https://review.coreboot.org/qc_blobs.git
url = ../qc_blobs.git
update = none
ignore = dirty
[submodule "3rdparty/intel-sec-tools"]
path = 3rdparty/intel-sec-tools
url = https://review.coreboot.org/9esec-security-tooling.git
url = ../9esec-security-tooling.git
[submodule "3rdparty/stm"]
path = 3rdparty/stm
url = https://review.coreboot.org/STM
url = ../STM
branch = stmpe
[submodule "util/goswid"]
path = util/goswid
url = https://review.coreboot.org/goswid.git
url = ../goswid
branch = trunk
[submodule "src/vendorcode/amd/opensil/genoa_poc/opensil"]
path = src/vendorcode/amd/opensil/genoa_poc/opensil
url = https://review.coreboot.org/opensil_genoa_poc.git
url = ../opensil_genoa_poc.git

2
3rdparty/fsp vendored

2
3rdparty/vboot vendored

View File

@@ -69,9 +69,6 @@ These variables are typically set in the makefiles or on the make command line.
These variables were added to Kconfig specifically for coreboot and are not
included in the Linux version.
- KCONFIG_STRICT=value. Define to enable warnings as errors. This is enabled
in coreboot, and should not be changed.
- KCONFIG_NEGATIVES=value. Define to show negative values in the autoconf.h file
(build/config.h). This is enabled in coreboot, and should not be changed.
@@ -102,6 +99,9 @@ included in the Linux version.
- KCONFIG_SPLITCONFIG=”directory name for individual SYMBOL.h files”.
coreboot sets this to $(obj)/config.
- KCONFIG_WERROR=value. Define to enable warnings as errors. This is enabled
in coreboot, and should not be changed.
#### Used only for make menuconfig
- MENUCONFIG_MODE=single_menu. Set to "single_menu" to enable. All other
values disable the option. This makes submenus appear below the menu option
@@ -1160,10 +1160,6 @@ saved .config file. As always, a 'select' statement overrides any specified
- coreboot has added the glob operator '*' for the 'source' keyword.
- coreboots Kconfig always defines variables except for strings. In other
Kconfig implementations, bools set to false/0/no are not defined.
- coreboots version of Kconfig adds the KCONFIG_STRICT environment variable to
error out if there are any issues in the Kconfig files. In the Linux kernel,
Kconfig will generate a warning, but will still output an updated .config or
config.h file.
## Kconfig Editor Highlighting

View File

@@ -9,7 +9,7 @@ updates using an A/B partitioning scheme once enabled.
## Enabling vboot
You can enable [vboot] in Kconfig's *Security* section. Besides a verified
boot you can also enable a measured boot by setting
`CONFIG_VBOOT_MEASURED_BOOT`. Both options need a working TPM, which is
`CONFIG_TPM_MEASURED_BOOT`. Both options need a working TPM, which is
present on all recent Lenovo devices.
## Updating and recovery

View File

@@ -0,0 +1,99 @@
Upcoming release - coreboot 24.02
========================================================================
The 24.02 release is scheduled for Mid February, 2024
Update this document with changes that should be in the release notes.
* Please use Markdown.
* See the past few release notes for the general format.
* The chip and board additions and removals will be updated right
before the release, so those do not need to be added.
* Note that all changes before the release are done are marked upcoming.
A final version of the notes are done after the release.
### Release number format update
The previous release was the last to use the incrementing 4.xx release
name scheme. For this and future releases, coreboot has switched to a
Year.Month.Sub-version naming scheme. As such, the next release,
scheduled for May of 2024 will be numbered 24.05, with the sub-version
of 00 implied. If we need to do a fix or incremental release, well
append the values .01, .02 and so on to the initial release value.
Significant or interesting changes
----------------------------------
* Add changes that need a full description here
* This section should have full descriptions and can or should have
a link to the referenced commits.
Additional coreboot changes
---------------------------
The following are changes across a number of patches, or changes worth
noting, but not needing a full description.
* Changes that only need a line or two of description go here.
Changes to external resources
-----------------------------
### Toolchain updates
### Git submodule pointers
### External payloads
Platform Updates
----------------
### Added mainboards:
* To be filled in immediately before the release by the release team
### Removed Mainboards
* To be filled in immediately before the release by the release team
### Updated SoCs
* To be filled in immediately before the release by the release team
Plans to move platform support to a branch
------------------------------------------
* To be filled in immediately before the release by the release team
Statistics from the 4.22 to the 24.02 release
--------------------------------------------
* To be filled in immediately before the release by the release team
Significant Known and Open Issues
---------------------------------
Issues from the coreboot bugtracker: https://ticket.coreboot.org/
* To be filled in immediately before the release by the release team
coreboot Links and Contact Information
--------------------------------------
* Main Web site: https://www.coreboot.org
* Downloads: https://coreboot.org/downloads.html
* Source control: https://review.coreboot.org
* Documentation: https://doc.coreboot.org
* Issue tracker: https://ticket.coreboot.org/projects/coreboot
* Donations: https://coreboot.org/donate.html

View File

@@ -1,7 +1,7 @@
Upcoming release - coreboot 4.22
coreboot 4.22 & 4.22.01 releases
========================================================================
The next release is planned for mid-February, 2024
The next release is planned for the 19th of February, 2024
These notes cover the latest updates and improvements to coreboot over
the past three months. A big thank you to the returning contributors as
@@ -11,6 +11,17 @@ releases, this one reflects a commitment to open source innovation,
security enhancements, and expanding hardware support.
### 4.22.01 release
The week between tagging a release and announcing it publicly is used
to test the tagged version and make sure everything is working as we
expect. This is done instead of freezing the tree and doing release
candidates before the release.
For the 4.22 release cycle we found an uninitialized variable error on
the sandybridge/ivybridge platforms and rolled that into the 4.22.01
release package.
### coreboot version naming update
This release is the last release to use the incrementing 4.xx release
@@ -18,14 +29,14 @@ name scheme. For future releases, coreboot is switching to a
Year.Month.Sub-version naming scheme. As such, the next release,
scheduled for February of 2024 will be numbered 24.02, with the
sub-version of 00 implied. If we need to do a fix or future release of
the 24.02 release, well append the values .01, .02 and so on to the
the 24.02 release, we'll append the values .01, .02 and so on to the
initial release value.
### coreboot default branch update
Immediately after the 4.21 release, the coreboot project changed the
default git branch from master to main. For the first couple of
default git branch from 'master' to 'main'. For the first couple of
months after the change, The master branch was synced with the main
branch several times a day, allowing people time to update any scripts.
As of 2023-11-01, the sync rate has slowed to once a week. This will
@@ -155,7 +166,7 @@ GPU drivers will fail to load with a code 43 error in Device Manager.
Additional coreboot changes
---------------------------
* Move all select statements from Kconfig.name files to Kconfig
* Move all 'select' statements from Kconfig.name files to Kconfig
* acpigen now generates variable-length PkgLength fields instead of a
fixed 3-byte size to improve compatibility and to bring it in line
with IASL
@@ -235,15 +246,15 @@ Platform Updates
Statistics from the 4.21 to the 4.22 release
--------------------------------------------
* Total Commits: 885
* Average Commits per day: 10.72
* Total lines added: 58276
* Average lines added per commit: 65.85
* Number of patches adding more than 100 lines: 54
* Average lines added per small commit: 37.77
* Total lines removed: 27790
* Average lines removed per commit: 31.40
* Total difference between added and removed: 30486
* Total Commits: 977
* Average Commits per day: 10.98
* Total lines added: 62993
* Average lines added per commit: 64.48
* Number of patches adding more than 100 lines: 60
* Average lines added per small commit: 37.55
* Total lines removed: 30042
* Average lines removed per commit: 30.75
* Total difference between added and removed: 32951
* Total authors: 135
* New authors: 14

View File

@@ -3,7 +3,7 @@
## Upcoming release
Please add to the release notes as changes are added:
* [4.22 - November 2023](coreboot-4.22-relnotes.md)
* [24.02 - February 2024](coreboot-24.02-relnotes.md)
The [checklist] contains instructions to ensure that a release covers all
important things and provides a reliable format for tarballs, branch
@@ -15,6 +15,7 @@ important is taken care of.
## Previous releases
* [4.22 - November 2023](coreboot-4.22-relnotes.md)
* [4.21 - August 2023](coreboot-4.21-relnotes.md)
* [4.20.1 - May 2023](coreboot-4.20.1-relnotes.md)
* [4.19 - January 2023](coreboot-4.19-relnotes.md)

View File

@@ -68,7 +68,7 @@ specific IBB measurements without hard-coding them.
#### Runtime Data
* CBFS data which changes by external input dynamically. Never stays the same.
* It is identified by VBOOT_MEASURED_BOOT_RUNTIME_DATA kconfig option and
* It is identified by TPM_MEASURED_BOOT_RUNTIME_DATA kconfig option and
measured into a different PCR (PCR_RUNTIME_DATA kconfig option, 3 by default)
in order to avoid PCR pre-calculation issues.

View File

@@ -349,7 +349,7 @@ GOOGLE REX MAINBOARDS
M: Subrata Banik <subratabanik@google.com>
M: Tarun Tuli <tstuli@gmail.com>
M: Kapil Porwal <kapilporwal@google.com>
M: Jakub Czapiga <jacz@semihalf.com>
M: Jakub Czapiga <czapiga@google.com>
M: Eran Mitrani <mitrani@google.com>
M: Dinesh Gehlot <digehlot@google.com>
S: Maintained
@@ -886,7 +886,7 @@ INTEL METEORLAKE SOC
M: Subrata Banik <subratabanik@google.com>
M: Tarun Tuli <tstuli@gmail.com>
M: Kapil Porwal <kapilporwal@google.com>
M: Jakub Czapiga <jacz@semihalf.com>
M: Jakub Czapiga <czapiga@google.com>
M: Eran Mitrani <mitrani@google.com>
M: Dinesh Gehlot <digehlot@google.com>
S: Maintained
@@ -1180,7 +1180,7 @@ S: Maintained
F: src/drivers/i2c/tas5825m/
TESTS
M: Jakub Czapiga <jacz@semihalf.com>
M: Jakub Czapiga <czapiga@google.com>
S: Maintained
F: tests/
F: payloads/libpayload/tests/

View File

@@ -23,20 +23,27 @@ COREBOOT_EXPORTS += top src srck obj objutil objk
DOTCONFIG ?= $(top)/.config
KCONFIG_CONFIG = $(DOTCONFIG)
KCONFIG_AUTOADS := $(obj)/cb-config.ads
KCONFIG_RUSTCCFG := $(obj)/cb-config.rustcfg
KCONFIG_AUTOHEADER := $(obj)/config.h
KCONFIG_AUTOCONFIG := $(obj)/auto.conf
KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd
KCONFIG_SPLITCONFIG := $(obj)/config/
KCONFIG_TRISTATE := $(obj)/tristate.conf
KCONFIG_NEGATIVES := 1
KCONFIG_STRICT := 1
KCONFIG_WERROR := 1
KCONFIG_WARN_UNKNOWN_SYMBOLS := 1
KCONFIG_PACKAGE := CB.Config
KCONFIG_MAKEFILE_REAL ?= $(objk)/Makefile.real
COREBOOT_EXPORTS += KCONFIG_CONFIG KCONFIG_AUTOHEADER KCONFIG_AUTOCONFIG
COREBOOT_EXPORTS += KCONFIG_DEPENDENCIES KCONFIG_SPLITCONFIG KCONFIG_TRISTATE
COREBOOT_EXPORTS += KCONFIG_NEGATIVES KCONFIG_STRICT
COREBOOT_EXPORTS += KCONFIG_NEGATIVES
ifeq ($(filter %config,$(MAKECMDGOALS)),)
COREBOOT_EXPORTS += KCONFIG_WERROR
endif
COREBOOT_EXPORTS += KCONFIG_WARN_UNKNOWN_SYMBOLS
COREBOOT_EXPORTS += KCONFIG_AUTOADS KCONFIG_PACKAGE
COREBOOT_EXPORTS += KCONFIG_RUSTCCFG
# Make does not offer a recursive wildcard function, so here's one:
rwildcard=$(wildcard $1$2) $(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2))

View File

@@ -59,22 +59,36 @@ COREBOOT_EXPORTS += CCACHE_EXTRAFILES
#######################################################################
# root rule to resolve if in build mode (ie. configuration exists)
real-target: $(obj)/config.h coreboot files_added
real-target: $(obj)/config.h coreboot files_added show_coreboot show_notices
coreboot: $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool $(obj)/ifwitool $(obj)/cse_fpt $(obj)/cse_serger
# This target can be used in site local to run scripts or additional
# targets after the build completes by creating a Makefile.inc in the
# site-local directory with a target named 'build_complete::'
build_complete:: coreboot
# This target can be used to run scripts or additional targets
# after the build completes by creating a target named 'build_complete::'
.PHONY: build_complete
build_complete:: | coreboot
# This target can be used to run rules after all files were added to CBFS,
# for example to process FMAP regions or the entire image.
.PHONY: files_added
files_added:: | build_complete
# This target should come just before the show_notices target. If there
# are no notices, the build should finish with the text of what was just
# built.
.PHONY: show_coreboot
show_coreboot: | files_added
$(CBFSTOOL) $(obj)/coreboot.rom print -r $(subst $(spc),$(comma),$(all-regions))
printf "\nBuilt %s (%s)\n" $(MAINBOARDDIR) $(CONFIG_MAINBOARD_PART_NUMBER)
if [ -f "$(CCACHE_STATSLOG)" ]; then \
printf "\nccache statistics\n"; \
$(CCACHE) --show-log-stats -v; \
fi
# This target can be used to run rules after all files were added to CBFS,
# for example to process FMAP regions or the entire image.
files_added:: build_complete
# This is intended to run at the *very end* of the build to show warnings
# notices and the like. If another target needs to be added, add it
# BEFORE this target.
.PHONY: show_notices
show_notices:: | show_coreboot
#######################################################################
# our phony targets
@@ -1241,7 +1255,6 @@ endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE
@printf " CBFSLAYOUT $(subst $(obj)/,,$(@))\n\n"
$(CBFSTOOL) $@ layout
@printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n"
$(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions))
ifeq ($(CONFIG_CBFS_VERIFICATION),y)
line=$$($(CBFSTOOL) $@ print -kv 2>/dev/null | grep -F '[CBFS VERIFICATION (COREBOOT)]') ;\
if ! printf "$$line" | grep -q 'fully valid'; then \

View File

@@ -140,9 +140,10 @@ These uncopyrightable files include:
These may be required to exist as part of the build process but are
not needed for the particular project.
- Configuration files either in binary or text form. Examples would be
files such as .vbt files describing graphics configuration, spd files
as binary .spd or text \*spd\*.hex representing memory chip
configuration.
files such as .vbt files describing graphics configuration, .apcb
files containing configuration parameters for AMD firmware binaries,
and spd files as binary .spd or text \*spd\*.hex representing memory
chip configuration.
- Machine-generated files containing version numbers, dates, hash
values or other "non-creative" content.

View File

@@ -8,4 +8,3 @@ CONFIG_DEBUG_PIRQ=y
CONFIG_DEBUG_MALLOC=y
CONFIG_DEBUG_BOOT_STATE=y
CONFIG_DEBUG_ADA_CODE=y
CONFIG_CPU_QEMU_X86_PARALLEL_MP=y

View File

@@ -1,5 +1,3 @@
CONFIG_VENDOR_EMULATION=y
CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y
CONFIG_CPU_QEMU_X86_PARALLEL_MP=y
CONFIG_CPU_QEMU_X86_TSEG_SMM=y
CONFIG_CPU_QEMU_X86_SMMLOADERV2=y

View File

@@ -10,7 +10,6 @@ CONFIG_ANY_TOOLCHAIN=y
# ChromeOS
CONFIG_CHROMEOS=y
CONFIG_HAS_RECOVERY_MRC_CACHE=y
CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN=y
# Event Logging
CONFIG_CMOS_POST=y
@@ -34,5 +33,5 @@ CONFIG_CONSOLE_SERIAL=y
CONFIG_CONSOLE_SERIAL_115200=y
# CONFIG_DRIVERS_UART_8250IO is not set
# GLK specific setting to auto select all the correct settings.
CONFIG_UART_DEBUG=y
CONFIG_INTEL_LPSS_UART_FOR_CONSOLE=y
CONFIG_NO_BOOTBLOCK_CONSOLE=y

View File

@@ -1,4 +1,4 @@
CONFIG_VENDOR_GOOGLE=y
CONFIG_BOARD_GOOGLE_OCTOPUS=y
CONFIG_CONSOLE_SPI_FLASH=y
# CONFIG_VBOOT_MEASURED_BOOT is not set
# CONFIG_TPM_MEASURED_BOOT is not set

View File

@@ -1,7 +0,0 @@
CONFIG_USE_BLOBS=y
CONFIG_VENDOR_INTEL=y
CONFIG_INTEL_GMA_VBT_FILE="3rdparty/fsp/CoffeeLakeFspBinPkg/SampleCode/Vbt/Vbt.bin"
CONFIG_BOARD_INTEL_COFFEELAKE_RVP11=y
CONFIG_USE_CANNONLAKE_FSP_CAR=y
CONFIG_RUN_FSP_GOP=y
CONFIG_PAYLOAD_NONE=y

View File

@@ -6,5 +6,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_PXE=y
CONFIG_BUILD_IPXE=y
CONFIG_PXE_ROM_ID="10ec,8168"
# CONFIG_PXE_SERIAL_CONSOLE is not set
# CONFIG_IPXE_SERIAL_CONSOLE is not set
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

View File

@@ -8,5 +8,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_PXE=y
CONFIG_BUILD_IPXE=y
CONFIG_PXE_ROM_ID="8086,157b"
# CONFIG_PXE_SERIAL_CONSOLE is not set
# CONFIG_IPXE_SERIAL_CONSOLE is not set
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

View File

@@ -8,5 +8,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_PXE=y
CONFIG_BUILD_IPXE=y
CONFIG_PXE_ROM_ID="8086,1539"
# CONFIG_PXE_SERIAL_CONSOLE is not set
# CONFIG_IPXE_SERIAL_CONSOLE is not set
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

View File

@@ -8,5 +8,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_PXE=y
CONFIG_BUILD_IPXE=y
CONFIG_PXE_ROM_ID="8086,1539"
# CONFIG_PXE_SERIAL_CONSOLE is not set
# CONFIG_IPXE_SERIAL_CONSOLE is not set
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

View File

@@ -8,5 +8,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_PXE=y
CONFIG_BUILD_IPXE=y
CONFIG_PXE_ROM_ID="8086,1539"
# CONFIG_PXE_SERIAL_CONSOLE is not set
# CONFIG_IPXE_SERIAL_CONSOLE is not set
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

View File

@@ -50,7 +50,7 @@ print-repo-info-payloads:
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
ifeq ($(CONFIG_PAYLOAD_NONE),y)
files_added:: warn_no_payload
show_notices:: warn_no_payload
endif
warn_no_payload:

View File

@@ -56,4 +56,4 @@ ENDPROC(_entry)
1:
.word cb_header_ptr
2:
.word _stack
.word _estack

View File

@@ -40,29 +40,35 @@ SECTIONS
_start = .;
.text : {
_text = .;
*(.text._entry)
*(.text)
*(.text.*)
_etext = .;
}
.rodata : {
_rodata = .;
*(.rodata)
*(.rodata.*)
_erodata = .;
}
.data : {
_data = .;
*(.data)
*(.data.*)
_edata = .;
}
_edata = .;
.bss : {
_bss = .;
*(.sbss)
*(.sbss.*)
*(.bss)
*(.bss.*)
*(COMMON)
_ebss = .;
/* Stack and heap */
@@ -72,10 +78,10 @@ SECTIONS
. = ALIGN(16);
_eheap = .;
_estack = .;
_stack = .;
. += CONFIG_LP_STACK_SIZE;
. = ALIGN(16);
_stack = .;
_estack = .;
}
_end = .;

View File

@@ -55,4 +55,4 @@ ENDPROC(_entry)
1:
.quad cb_header_ptr
2:
.quad _stack
.quad _estack

View File

@@ -40,29 +40,37 @@ SECTIONS
_start = .;
.text : {
_text = .;
*(.text._entry)
*(.text)
*(.text.*)
_etext = .;
}
.rodata : {
_rodata = .;
*(.rodata)
*(.rodata.*)
_erodata = .;
}
.data : {
_data = .;
*(.data)
*(.data.*)
_edata = .;
}
_edata = .;
.bss : {
*(.ttb_buffer)
_bss = .;
*(.sbss)
*(.sbss.*)
*(.bss)
*(.bss.*)
*(COMMON)
_ebss = .;
/* Stack and heap */
@@ -72,10 +80,10 @@ SECTIONS
. = ALIGN(16);
_eheap = .;
_estack = .;
_stack = .;
. += CONFIG_LP_STACK_SIZE;
. = ALIGN(16);
_stack = .;
_estack = .;
}
_end = .;

View File

@@ -41,7 +41,8 @@ static unsigned int max_tables;
static uint64_t *xlat_addr;
static int free_idx;
static uint8_t ttb_buffer[TTB_DEFAULT_SIZE] __attribute__((aligned(GRANULE_SIZE)));
static uint8_t ttb_buffer[TTB_DEFAULT_SIZE] __aligned(GRANULE_SIZE)
__attribute__((__section__(".ttb_buffer")));
static const char * const tag_to_string[] = {
[TYPE_NORMAL_MEM] = "normal",
@@ -574,8 +575,6 @@ static struct mmu_memrange *_mmu_add_fb_range(
prop.type = TYPE_DMA_MEM;
/* make sure to allocate a size of multiple of GRANULE_SIZE */
size = ALIGN_UP(size, GRANULE_SIZE);
prop.size = size;
prop.lim_excl = MIN_64_BIT_ADDR;
prop.align = MB_SIZE;
@@ -633,6 +632,9 @@ static void mmu_add_fb_range(struct mmu_ranges *mmu_ranges)
if (!fb_size)
return;
/* make sure to allocate a size of multiple of GRANULE_SIZE */
fb_size = ALIGN_UP(fb_size, GRANULE_SIZE);
/* framebuffer address has been set already, so just add it as DMA */
if (framebuffer->physical_address) {
if (mmu_add_memrange(mmu_ranges,

View File

@@ -73,7 +73,7 @@ _init:
/* Store current stack pointer and set up new stack. */
movl %esp, %eax
movl $_stack, %esp
movl $_estack, %esp
pushl %eax
/* Enable special x86 functions if present. */

View File

@@ -39,29 +39,35 @@ SECTIONS
_start = .;
.text : {
_text = .;
*(.text._entry)
*(.text)
*(.text.*)
_etext = .;
}
.rodata : {
_rodata = .;
*(.rodata)
*(.rodata.*)
_erodata = .;
}
.data : {
_data = .;
*(.data)
*(.data.*)
_edata = .;
}
_edata = .;
.bss : {
_bss = .;
*(.sbss)
*(.sbss.*)
*(.bss)
*(.bss.*)
*(COMMON)
_ebss = .;
/* Stack and heap */
@@ -71,10 +77,10 @@ SECTIONS
. = ALIGN(16);
_eheap = .;
_estack = .;
_stack = .;
. += CONFIG_LP_STACK_SIZE;
. = ALIGN(16);
_stack = .;
_estack = .;
}
_end = .;

View File

@@ -1,2 +1,2 @@
CONFIG_LP_ARCH_MOCK=y
CONFIG_LP_ARCH_BIG_ENDIAN=n
CONFIG_LP_ARCH_MOCK_BIG_ENDIAN=n

View File

@@ -137,6 +137,7 @@ void print_malloc_map(void);
void init_dma_memory(void *start, u32 size);
int dma_initialized(void);
int dma_coherent(const void *ptr);
void dma_allocator_range(void **start_out, size_t *size_out);
static inline void *xmalloc_work(size_t size, const char *file,
const char *func, int line)

View File

@@ -123,6 +123,18 @@ int dma_coherent(const void *ptr)
return !dma_initialized() || (dma->start <= ptr && dma->end > ptr);
}
/* Get the range of memory that can be allocated by the dma allocator. */
void dma_allocator_range(void **start_out, size_t *size_out)
{
if (dma_initialized()) {
*start_out = dma->start;
*size_out = dma->end - dma->start;
} else {
*start_out = NULL;
*size_out = 0;
}
}
/* Find free block of size >= len */
static hdrtype_t volatile *find_free_block(int len, struct memory_type *type)
{

View File

@@ -86,8 +86,36 @@ config ACPI_GTDT
help
Selected by platforms that implement ARM generic timers
config ACPI_IORT
def_bool n
depends on ARCH_ARM64 && HAVE_ACPI_TABLES
help
Selected by platforms that implement ARM IO Remap table.
config MAX_ACPI_TABLE_SIZE_KB
int
default 144
help
Set the maximum size of all ACPI tables in KiB.
config ACPI_PPTT
bool
depends on HAVE_ACPI_TABLES
help
Selected to build an ACPI Processor Properties Topology Table.
config ACPI_PPTT_MAX_CACHES
int
depends on ACPI_PPTT
default 4
help
This variable sets the maximum number of distinct caches per
topology level. Increasing this option also increases stack usage.
config ACPI_WDAT_WDT
bool
default n
depends on HAVE_ACPI_TABLES
help
Selected by platforms that support and fill ACPI Watchdog Action Table
(WDAT).

View File

@@ -8,6 +8,7 @@ ramstage-y += acpi_apic.c
ramstage-y += acpi_dmar.c
ramstage-y += acpi_hpet.c
endif
ramstage-$(CONFIG_ACPI_PPTT) += acpi_pptt.c
ramstage-y += acpigen.c
ramstage-y += acpigen_dptf.c
ramstage-y += acpigen_dsm.c

View File

@@ -14,6 +14,7 @@
*/
#include <acpi/acpi.h>
#include <acpi/acpi_iort.h>
#include <acpi/acpi_ivrs.h>
#include <acpi/acpigen.h>
#include <cbfs.h>
@@ -21,6 +22,7 @@
#include <commonlib/helpers.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <device/device.h>
#include <device/mmio.h>
#include <device/pci.h>
#include <drivers/uart/pl011.h>
@@ -298,7 +300,9 @@ static void acpi_ssdt_write_cbtable(void)
acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
acpigen_write_name("_CRS");
acpigen_write_resourcetemplate_header();
acpigen_write_mem32fixed(0, base, size);
acpigen_resource_consumer_mmio(base, base + size - 1,
MEM_RSRC_FLAG_MEM_READ_ONLY
| MEM_RSRC_FLAG_MEM_ATTR_CACHE);
acpigen_write_resourcetemplate_footer();
acpigen_pop_len();
}
@@ -896,6 +900,14 @@ unsigned long acpi_pl011_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long curren
name);
}
unsigned long acpi_16550_mmio32_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long current,
uint64_t base, const char *name)
{
return acpi_write_dbg2_uart(rsdp, current, ACPI_ADDRESS_SPACE_MEMORY, base,
0x100, ACPI_ACCESS_SIZE_DWORD_ACCESS,
name);
}
static void acpi_create_facs(void *header)
{
acpi_facs_t *facs = header;
@@ -1186,6 +1198,45 @@ unsigned long acpi_gtdt_add_watchdog(unsigned long current, uint64_t refresh_fra
return current + sizeof(struct acpi_gtdt_watchdog);
}
static void acpi_create_iort(acpi_header_t *header, void *unused)
{
if (!CONFIG(ACPI_IORT))
return;
acpi_iort_t *iort = (acpi_iort_t *)header;
unsigned long current = (unsigned long)iort + sizeof(acpi_iort_t);
if (acpi_fill_header(header, "IORT", IORT, sizeof(acpi_iort_t)) != CB_SUCCESS)
return;
iort->node_count = 0;
iort->node_offset = current - (unsigned long)iort;
current = acpi_soc_fill_iort(iort, current);
/* (Re)calculate length */
header->length = current - (unsigned long)iort;
}
static void acpi_create_wdat(acpi_header_t *header, void *unused)
{
if (!CONFIG(ACPI_WDAT_WDT))
return;
acpi_wdat_t *wdat = (acpi_wdat_t *)header;
unsigned long current = (unsigned long)wdat + sizeof(acpi_wdat_t);
memset((void *)wdat, 0, sizeof(acpi_wdat_t));
if (acpi_fill_header(header, "WDAT", WDAT, sizeof(acpi_wdat_t)) != CB_SUCCESS)
return;
current = acpi_soc_fill_wdat(wdat, current);
/* (Re)calculate length. */
header->length = current - (unsigned long)wdat;
}
unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid)
{
memset(lpi_desc, 0, sizeof(acpi_lpi_desc_ncst_t));
@@ -1196,6 +1247,18 @@ unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t
return lpi_desc->header.length;
}
static void acpi_create_pptt(acpi_header_t *header, void *unused)
{
if (!CONFIG(ACPI_PPTT))
return;
if (acpi_fill_header(header, "PPTT", PPTT, sizeof(acpi_pptt_t)) != CB_SUCCESS)
return;
acpi_pptt_t *pptt = (acpi_pptt_t *)header;
acpi_create_pptt_body(pptt);
}
static uint8_t acpi_spcr_type(void)
{
/* 16550-compatible with parameters defined in Generic Address Structure */
@@ -1347,6 +1410,8 @@ static void acpixtract_compatible_hexdump(const void *memory, size_t length)
static void acpidump_print(void *table_ptr)
{
if (table_ptr == NULL)
return;
const acpi_header_t *header = (acpi_header_t *)table_ptr;
const size_t table_size = header->length;
printk(BIOS_SPEW, "%.4s @ 0x0000000000000000\n", header->signature);
@@ -1386,6 +1451,9 @@ unsigned long write_acpi_tables(const unsigned long start)
{ acpi_create_bert, NULL, sizeof(acpi_bert_t) },
{ acpi_create_spcr, NULL, sizeof(acpi_spcr_t) },
{ acpi_create_gtdt, NULL, sizeof(acpi_gtdt_t) },
{ acpi_create_pptt, NULL, sizeof(acpi_pptt_t) },
{ acpi_create_iort, NULL, sizeof(acpi_iort_t) },
{ acpi_create_wdat, NULL, sizeof(acpi_wdat_t) },
};
current = start;
@@ -1735,6 +1803,12 @@ int get_acpi_table_revision(enum acpi_tables table)
return 4;
case GTDT:
return 3;
case PPTT: /* ACPI 6.4 */
return 3;
case IORT: /* IO Remapping Table E.e */
return 6;
case WDAT:
return 1;
default:
return -1;
}

View File

@@ -5,6 +5,7 @@
#include <arch/smp/mpspec.h>
#include <commonlib/sort.h>
#include <cpu/cpu.h>
#include <device/device.h>
static int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic)
{

View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <device/device.h>
static int acpi_create_madt_one_gicc_v3(acpi_madt_gicc_t *gicc, u32 acpi_uid, u32 pi_gsiv,
uint32_t vgic_mi, uint64_t mpidr)
@@ -79,11 +80,37 @@ static unsigned long acpi_create_madt_gicr_v3(unsigned long current)
return current + gicr->length;
}
__weak int platform_get_gic_its(uintptr_t **base)
{
return 0;
}
static unsigned long acpi_create_madt_gic_its_v3(unsigned long current)
{
int i, its_count;
uintptr_t *its_base;
its_count = platform_get_gic_its(&its_base);
for (i = 0; i < its_count; i++) {
acpi_madt_gic_its_t *gic_its = (acpi_madt_gic_its_t *)current;
memset(gic_its, 0, sizeof(acpi_madt_gic_its_t));
gic_its->type = GIC_ITS;
gic_its->gic_its_id = i;
gic_its->physical_base_address = its_base[i];
gic_its->length = sizeof(acpi_madt_gic_its_t);
current = current + gic_its->length;
}
return current;
}
unsigned long acpi_arch_fill_madt(acpi_madt_t *madt, unsigned long current)
{
current = acpi_create_madt_giccs_v3(current);
current = acpi_create_madt_gicd_v3(current);
current = acpi_create_madt_gicr_v3(current);
current = acpi_create_madt_gic_its_v3(current);
return current;
}

View File

@@ -3,6 +3,7 @@
#include <acpi/acpi.h>
#include <arch/hpet.h>
#include <console/console.h>
#include <device/device.h>
#include <device/mmio.h>
#include <version.h>

186
src/acpi/acpi_pptt.c Normal file
View File

@@ -0,0 +1,186 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <include/assert.h>
#include <console/console.h>
/*
* A structure to hold a cache pointer
* and its corresponding reference within
* the PPTT table.
*/
struct cache_reference {
struct pptt_cache *cache; // cache pointer
u32 ref; // and its reference within PPTT
};
/*
* A list of 'struct cache_reference', used
* to keep track of generated caches per topology level.
*/
struct cache_list {
u32 n_caches; // number of caches in list
struct cache_reference cache_refs[CONFIG_ACPI_PPTT_MAX_CACHES]; // cache reference list
};
/*
* Start of the PPTT table. Constant
* value as soon as we enter acpi_create_pptt_body.
*/
static uintptr_t pptt_start;
/* --- Helper Functions (non exposed) --- */
static inline u32 node_to_reference(const void *node)
{
/*
* References are the offset from the start
* of the PPTT table.
*
* PPTT
* +---------+ <- pptt_start (acpi_pptt_t) <---+
* | | | node - pptt_start
* | | |
* +---------+ <- node (cpu or cache) <--------+
* | |
* | |
* | |
* +---------+
*/
return ((uintptr_t)node - pptt_start);
}
static u32 count_resources(struct pptt_cpu_resources *res)
{
u32 n_resources = 0;
while (res != NULL) {
n_resources += 1;
res = res->next;
}
return n_resources;
}
static u32 cache_list_ref_of(struct cache_list *cache_list, const struct pptt_cache *cache)
{
/*
* Lookup the PPTT reference of 'cache'.
* Return 0, if no PPTT structure exists for 'cache'.
*/
for (int i = 0; i < cache_list->n_caches; i++) {
if (cache_list->cache_refs[i].cache == cache)
return cache_list->cache_refs[i].ref;
}
/* no cache reference found */
return 0;
}
static inline void cache_list_append(struct cache_list *cache_list, struct pptt_cache *cache, const u32 ref)
{
printk(BIOS_DEBUG, "acpi: pptt: cache=%p ref=%u\n", cache, ref);
cache_list->cache_refs[cache_list->n_caches].cache = cache;
cache_list->cache_refs[cache_list->n_caches].ref = ref;
cache_list->n_caches += 1;
}
static u32 new_pptt_cache(unsigned long *current, struct pptt_cache *cache, struct cache_list *cache_list)
{
static u32 unique_cache_id = 1;
u32 current_reference = 0;
if ((current_reference = cache_list_ref_of(cache_list, cache)) != 0)
return current_reference;
if (cache_list->n_caches >= CONFIG_ACPI_PPTT_MAX_CACHES) {
printk(BIOS_WARNING, "acpi: pptt: Too many distinct caches! PPTT incomplete.\n");
return 0;
}
acpi_pptt_cache_node_t *cache_node = (acpi_pptt_cache_node_t *)*current;
memset(cache_node, 0x0, sizeof(acpi_pptt_cache_node_t));
cache_node->type = PPTT_NODE_TYPE_CACHE;
cache_node->length = sizeof(acpi_pptt_cache_node_t);
cache_node->flags = cache->flags.raw;
cache_node->size = cache->size;
cache_node->n_sets = cache->numsets;
cache_node->associativity = cache->associativity;
cache_node->attributes = cache->attributes;
cache_node->line_size = cache->line_size;
cache_node->cache_id = unique_cache_id++;
*current += cache_node->length;
current_reference = node_to_reference(cache_node);
cache_list_append(cache_list, cache, current_reference);
if (cache->next_level != NULL)
cache_node->next_level = new_pptt_cache(current, cache->next_level, cache_list);
return current_reference;
}
static u32 new_pptt_cpu(unsigned long *current, const struct pptt_topology *cpu, const u32 parent_ref, struct cache_list *cache_list)
{
acpi_pptt_cpu_node_t *cpu_node = (acpi_pptt_cpu_node_t *)*current;
const u32 n_resources = count_resources(cpu->resources);
const u32 structure_length = sizeof(acpi_pptt_cpu_node_t) + (n_resources * sizeof(u32));
memset(cpu_node, 0x0, structure_length);
cpu_node->type = PPTT_NODE_TYPE_CPU;
cpu_node->length = structure_length;
cpu_node->flags = cpu->flags.raw;
cpu_node->processor_id = cpu->processor_id;
cpu_node->parent = parent_ref;
*current += cpu_node->length;
for (struct pptt_cpu_resources *it = cpu->resources; it != NULL; it = it->next)
cpu_node->resources[cpu_node->n_resources++] = new_pptt_cache(current, it->cache, cache_list);
return node_to_reference(cpu_node);
}
static void setup_topology(const struct pptt_topology *node, const u32 parent_ref, unsigned long *current)
{
struct cache_list cache_list = {
.cache_refs = { },
.n_caches = 0
};
while (node != NULL) {
const u32 cpu_ref = new_pptt_cpu(current, node, parent_ref, &cache_list);
setup_topology(node->child, cpu_ref, current);
node = node->sibling;
}
}
/* --- PPTT generation helper functions (exposed) --- */
void acpi_create_pptt_body(acpi_pptt_t *pptt)
{
/* set start of pptt table */
pptt_start = (uintptr_t)pptt;
/* locate start of pptt body */
unsigned long current = (unsigned long)(pptt->body);
/* retrieve processor topology */
const struct pptt_topology *topology_tree = acpi_get_pptt_topology();
/* write processor properties topology table to memory */
setup_topology(topology_tree, 0, &current);
/* update length field in pptt header */
pptt->header.length = current - (unsigned long)pptt;
}

View File

@@ -2296,42 +2296,54 @@ void acpigen_resource_producer_io(u16 io_base, u16 io_limit)
io_limit - io_base + 1); /* length */
}
static void acpigen_resource_producer_mmio32(u32 mmio_base, u32 mmio_limit, u16 type_flags)
static void acpigen_resource_mmio32(u32 mmio_base, u32 mmio_limit, u16 gen_flags,
u16 type_flags)
{
acpigen_resource_dword(RSRC_TYPE_MEM, /* res_type */
ADDR_SPACE_GENERAL_FLAG_MAX_FIXED
| ADDR_SPACE_GENERAL_FLAG_MIN_FIXED
| ADDR_SPACE_GENERAL_FLAG_DEC_POS
| ADDR_SPACE_GENERAL_FLAG_PRODUCER, /* gen_flags */
type_flags, /* type_flags */
0, /* gran */
mmio_base, /* range_min */
mmio_limit, /* range_max */
0x0, /* translation */
mmio_limit - mmio_base + 1); /* length */
gen_flags, /* gen_flags */
type_flags, /* type_flags */
0, /* gran */
mmio_base, /* range_min */
mmio_limit, /* range_max */
0x0, /* translation */
mmio_limit - mmio_base + 1); /* length */
}
static void acpigen_resource_producer_mmio64(u64 mmio_base, u64 mmio_limit, u16 type_flags)
static void acpigen_resource_mmio64(u64 mmio_base, u64 mmio_limit, u16 gen_flags,
u16 type_flags)
{
acpigen_resource_qword(RSRC_TYPE_MEM, /* res_type */
ADDR_SPACE_GENERAL_FLAG_MAX_FIXED
| ADDR_SPACE_GENERAL_FLAG_MIN_FIXED
| ADDR_SPACE_GENERAL_FLAG_DEC_POS
| ADDR_SPACE_GENERAL_FLAG_PRODUCER, /* gen_flags */
type_flags, /* type_flags */
0, /* gran */
mmio_base, /* range_min */
mmio_limit, /* range_max */
0x0, /* translation */
mmio_limit - mmio_base + 1); /* length */
gen_flags, /* gen_flags */
type_flags, /* type_flags */
0, /* gran */
mmio_base, /* range_min */
mmio_limit, /* range_max */
0x0, /* translation */
mmio_limit - mmio_base + 1); /* length */
}
static void acpigen_resource_mmio(u64 mmio_base, u64 mmio_limit, bool is_producer, u16 type_flags)
{
const u16 gen_flags = ADDR_SPACE_GENERAL_FLAG_MAX_FIXED
| ADDR_SPACE_GENERAL_FLAG_MIN_FIXED
| ADDR_SPACE_GENERAL_FLAG_DEC_POS
| (is_producer ? ADDR_SPACE_GENERAL_FLAG_PRODUCER
: ADDR_SPACE_GENERAL_FLAG_CONSUMER);
if (mmio_base < 4ULL * GiB && mmio_limit < 4ULL * GiB)
acpigen_resource_mmio32(mmio_base, mmio_limit, gen_flags, type_flags);
else
acpigen_resource_mmio64(mmio_base, mmio_limit, gen_flags, type_flags);
}
void acpigen_resource_producer_mmio(u64 mmio_base, u64 mmio_limit, u16 type_flags)
{
if (mmio_base < 4ULL * GiB && mmio_limit < 4ULL * GiB)
acpigen_resource_producer_mmio32(mmio_base, mmio_limit, type_flags);
else
acpigen_resource_producer_mmio64(mmio_base, mmio_limit, type_flags);
acpigen_resource_mmio(mmio_base, mmio_limit, true, type_flags);
}
void acpigen_resource_consumer_mmio(u64 mmio_base, u64 mmio_limit, u16 type_flags)
{
acpigen_resource_mmio(mmio_base, mmio_limit, false, type_flags);
}
void acpigen_write_ADR(uint64_t adr)
@@ -2447,10 +2459,10 @@ void acpigen_write_delay_until_namestr_int(uint32_t wait_ms, const char *name, u
uint32_t wait_ms_segment = 1;
uint32_t segments = wait_ms;
/* Sleep in 16ms segments if delay is more than 32ms. */
if (wait_ms > 32) {
wait_ms_segment = 16;
segments = wait_ms / 16;
/* Sleep in 2ms segments if delay is more than 2ms. */
if (wait_ms > 2) {
wait_ms_segment = 2;
segments = wait_ms / wait_ms_segment;
}
acpigen_write_store_int_to_op(segments, LOCAL7_OP);

View File

@@ -4,6 +4,7 @@
#include <acpi/acpi_pld.h>
#include <acpi/acpigen.h>
#include <acpi/acpigen_usb.h>
#include <device/device.h>
static const char *power_role_to_str(enum usb_typec_power_role power_role)
{

View File

@@ -57,11 +57,27 @@ Scope(\_SB) {
Device (PERC) // PCI ECAM Resource Consumption
{
Name (_HID, EisaId("PNP0C02"))
Name (_CRS, ResourceTemplate()
Method (_CRS, 0, Serialized)
{
Memory32Fixed (ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS,
CONFIG_ECAM_MMCONF_LENGTH)
})
Name (RBUF, ResourceTemplate ()
{
QWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed,
NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000000000000, // _MIN
0x0000000000000001, // _MAX
0x0000000000000000, // Translation
0x0000000000000002, // _Len
,, _Y00, AddressRangeMemory, TypeStatic)
})
CreateQWordField (RBUF, \_SB.PERC._CRS._Y00._MIN, MIN1)
CreateQWordField (RBUF, \_SB.PERC._CRS._Y00._MAX, MAX1)
CreateQWordField (RBUF, \_SB.PERC._CRS._Y00._LEN, LEN1)
MIN1 = CONFIG_ECAM_MMCONF_BASE_ADDRESS
MAX1 = (MIN1 + CONFIG_ECAM_MMCONF_LENGTH -1)
LEN1 = CONFIG_ECAM_MMCONF_LENGTH
Return (RBUF)
}
}
}
#endif

View File

@@ -13,6 +13,11 @@ armv8_flags = -march=$(march) -I$(src)/arch/arm64/include/armv8/ -D__COREBOOT_AR
################################################################################
ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV8_64),y)
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
decompressor-ld-ccopts += -target arm64-elf
bootblock-ld-ccopts += -target arm64-elf
endif
ifneq ($(CONFIG_BOOTBLOCK_CUSTOM),y)
decompressor-y += bootblock.S
ifneq ($(CONFIG_COMPRESS_BOOTBLOCK),y)
@@ -44,6 +49,10 @@ endif
################################################################################
ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV8_64),y)
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
verstage-ld-ccopts += -target arm64-elf
endif
verstage-y += cache.c
verstage-y += cpu.S
verstage-y += exception.c
@@ -57,6 +66,10 @@ endif
################################################################################
ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y)
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
romstage-ld-ccopts += -target arm64-elf
endif
romstage-y += cache.c
romstage-y += cpu.S
romstage-y += exception.c
@@ -73,6 +86,10 @@ endif
################################################################################
ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV8_64),y)
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
ramstage-ld-ccopts += -target arm64-elf
endif
ramstage-y += cache.c
ramstage-y += cpu.S
ramstage-y += exception.c

View File

@@ -96,7 +96,7 @@ endif #CONFIG_ARCH_BOOTBLOCK_RISCV
################################################################################
ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y)
romstage-y += romstage.c
romstage-y += romstage.S
# Build the romstage

View File

@@ -8,8 +8,4 @@ PHDRS
to_load PT_LOAD;
}
#if ENV_BOOTBLOCK || ENV_RAMSTAGE
ENTRY(_start)
#else
ENTRY(stage_entry)
#endif

View File

@@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __ARCH_STAGES_H
#define __ARCH_STAGES_H
#include <main_decl.h>
void stage_entry(int hart_id, void *fdt)
__attribute__((section(".text.stage_entry")));
#endif

View File

@@ -39,13 +39,6 @@ void run_payload(struct prog *prog, void *fdt, int payload_mode)
status = INSERT_FIELD(status, MSTATUS_MPIE, 0);
switch (payload_mode) {
case RISCV_PAYLOAD_MODE_U:
status = INSERT_FIELD(status, MSTATUS_MPP, PRV_U);
/* Trap vector base address point to the payload */
write_csr(utvec, doit);
/* disable U-Mode interrupt */
write_csr(uie, 0);
break;
case RISCV_PAYLOAD_MODE_S:
status = INSERT_FIELD(status, MSTATUS_MPP, PRV_S);
/* Trap vector base address point to the payload */

38
src/arch/riscv/romstage.S Normal file
View File

@@ -0,0 +1,38 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/encoding.h>
#include <bits.h>
#include <mcall.h>
.section ".text._start", "ax", %progbits
.globl _start
_start:
# initialize stack point for each hart
# and the stack must be page-aligned.
# 0xDEADBEEF used to check stack overflow
csrr a0, mhartid
la t0, _stack
slli t1, a0, RISCV_PGSHIFT
add t0, t0, t1
li t1, 0xDEADBEEF
STORE t1, 0(t0)
li t1, RISCV_PGSIZE - HLS_SIZE
add sp, t0, t1
# initialize hart-local storage
csrr a0, mhartid
call hls_init
li a0, CONFIG_RISCV_WORKING_HARTID
call smp_pause
# initialize entry of interrupt/exception
la t0, trap_entry
csrw mtvec, t0
# clear any pending interrupts
csrwi mip, 0
# set up the mstatus register
call mstatus_init
tail main

View File

@@ -1,21 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Entry points must be placed at the location the previous stage jumps
* to (the lowest address in the stage image). This is done by giving
* stage_entry() its own section in .text and placing it first in the
* linker script.
*/
#include <arch/stages.h>
#include <arch/smp/smp.h>
#include <mcall.h>
void stage_entry(int hart_id, void *fdt)
{
HLS()->hart_id = hart_id;
HLS()->fdt = fdt;
smp_pause(CONFIG_RISCV_WORKING_HARTID);
main();
}

View File

@@ -33,10 +33,10 @@ static const char *const exception_names[] = {
static const char *mstatus_to_previous_mode(uintptr_t ms)
{
switch (ms & MSTATUS_MPP) {
case 0x00000000: return "user";
case 0x00000800: return "supervisor";
case 0x00001000: return "hypervisor";
case 0x00001800: return "machine";
case 0x00000000: return "user";
case 0x00000800: return "supervisor";
case 0x00001000: return "hypervisor";
case 0x00001800: return "machine";
}
return "unknown";
@@ -117,31 +117,31 @@ void trap_handler(trapframe *tf)
}
switch (tf->cause) {
case CAUSE_MISALIGNED_FETCH:
case CAUSE_FETCH_ACCESS:
case CAUSE_ILLEGAL_INSTRUCTION:
case CAUSE_BREAKPOINT:
case CAUSE_LOAD_ACCESS:
case CAUSE_STORE_ACCESS:
case CAUSE_USER_ECALL:
case CAUSE_HYPERVISOR_ECALL:
case CAUSE_MACHINE_ECALL:
print_trap_information(tf);
break;
case CAUSE_SUPERVISOR_ECALL:
handle_sbi(tf);
return;
case CAUSE_MISALIGNED_LOAD:
case CAUSE_MISALIGNED_STORE:
print_trap_information(tf);
handle_misaligned(tf);
return;
default:
printk(BIOS_EMERG, "================================\n");
printk(BIOS_EMERG, "coreboot: can not handle a trap:\n");
printk(BIOS_EMERG, "================================\n");
print_trap_information(tf);
break;
case CAUSE_MISALIGNED_FETCH:
case CAUSE_FETCH_ACCESS:
case CAUSE_ILLEGAL_INSTRUCTION:
case CAUSE_BREAKPOINT:
case CAUSE_LOAD_ACCESS:
case CAUSE_STORE_ACCESS:
case CAUSE_USER_ECALL:
case CAUSE_HYPERVISOR_ECALL:
case CAUSE_MACHINE_ECALL:
print_trap_information(tf);
break;
case CAUSE_SUPERVISOR_ECALL:
handle_sbi(tf);
return;
case CAUSE_MISALIGNED_LOAD:
case CAUSE_MISALIGNED_STORE:
print_trap_information(tf);
handle_misaligned(tf);
return;
default:
printk(BIOS_EMERG, "================================\n");
printk(BIOS_EMERG, "coreboot: can not handle a trap:\n");
printk(BIOS_EMERG, "================================\n");
print_trap_information(tf);
break;
}
die("Can't recover from trap. Halting.\n");

View File

@@ -317,7 +317,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE))
@printf " CC $(subst $(obj)/,,$(@))\n"
$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE))
$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE))
$(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs)
@printf " CC $(subst $(obj)/,,$(@))\n"

View File

@@ -4,7 +4,7 @@
#define _CBMEM_ID_H_
#define CBMEM_ID_ACPI 0x41435049
#define CBMEM_ID_ACPI_BERT 0x42455254
#define CBMEM_ID_ACPI_BERT 0x42455254
#define CBMEM_ID_ACPI_CNVS 0x434e5653
#define CBMEM_ID_ACPI_GNVS 0x474e5653
#define CBMEM_ID_ACPI_HEST 0x48455354
@@ -56,7 +56,7 @@
#define CBMEM_ID_ROMSTAGE_INFO 0x47545352
#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
#define CBMEM_ID_ROOT 0xff4007ff
#define CBMEM_ID_SMBIOS 0x534d4254
#define CBMEM_ID_SMBIOS 0x534d4254
#define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee
#define CBMEM_ID_STAGEx_META 0x57a9e000
#define CBMEM_ID_STAGEx_CACHE 0x57a9e100
@@ -89,6 +89,7 @@
#define CBMEM_ID_AMD_MP2 0x5f32504d
#define CBMEM_ID_CSE_INFO 0x4553435F
#define CBMEM_ID_CSE_BP_INFO 0x42455343
#define CBMEM_ID_AMD_OPENSIL 0x4153494C
#define CBMEM_ID_TO_NAME_TABLE \
{ CBMEM_ID_ACPI, "ACPI " }, \
@@ -107,7 +108,7 @@
{ CBMEM_ID_CB_EARLY_DRAM, "EARLY DRAM USAGE" }, \
{ CBMEM_ID_CONSOLE, "CONSOLE " }, \
{ CBMEM_ID_COVERAGE, "COVERAGE " }, \
{ CBMEM_ID_CPU_CRASHLOG, "CPU CRASHLOG"}, \
{ CBMEM_ID_CPU_CRASHLOG, "CPU CRASHLOG (deprecated)"}, \
{ CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, \
{ CBMEM_ID_ELOG, "ELOG " }, \
{ CBMEM_ID_FREESPACE, "FREE SPACE " }, \
@@ -126,7 +127,7 @@
{ CBMEM_ID_MMC_STATUS, "MMC STATUS " }, \
{ CBMEM_ID_MPTABLE, "SMP TABLE " }, \
{ CBMEM_ID_MRCDATA, "MRC DATA " }, \
{ CBMEM_ID_PMC_CRASHLOG, "PMC CRASHLOG"}, \
{ CBMEM_ID_PMC_CRASHLOG, "PMC CRASHLOG (deprecated)"}, \
{ CBMEM_ID_VAR_MRCDATA, "VARMRC DATA" }, \
{ CBMEM_ID_MTC, "MTC " }, \
{ CBMEM_ID_PIRQ, "IRQ TABLE " }, \
@@ -166,9 +167,10 @@
{ CBMEM_ID_FSP_LOGO, "FSP LOGO "}, \
{ CBMEM_ID_SMM_COMBUFFER, "SMM COMBUFFER"}, \
{ CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"},\
{ CBMEM_ID_MEM_CHIP_INFO, "MEM CHIP INFO"},\
{ CBMEM_ID_MEM_CHIP_INFO, "MEM CHIP INFO"},\
{ CBMEM_ID_AMD_STB, "AMD STB"},\
{ CBMEM_ID_AMD_MP2, "AMD MP2 BUFFER"},\
{ CBMEM_ID_CSE_INFO, "CSE SPECIFIC INFO"},\
{ CBMEM_ID_CSE_BP_INFO, "CSE BP INFO"}
{ CBMEM_ID_CSE_BP_INFO, "CSE BP INFO"}, \
{ CBMEM_ID_AMD_OPENSIL, "OPENSIL DATA"}
#endif /* _CBMEM_ID_H_ */

View File

@@ -9,10 +9,6 @@ subdirs-y += ../turbo
ramstage-y += acpi.c
ramstage-y += common.c
romstage-y += common.c
smm-y += common.c
smm-y += finalize.c
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*)

View File

@@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cpu/x86/msr.h>
#include "model_206ax.h"
int get_platform_id(void)
{
msr_t msr;
msr = rdmsr(IA32_PLATFORM_ID);
/* Read Platform Id Bits 52:50 */
return (msr.hi >> 18) & 0x7;
}

View File

@@ -73,8 +73,10 @@
#define PKG_POWER_LIMIT_TIME_MASK 0x7f
#define MSR_PP0_CURRENT_CONFIG 0x601
#define PP0_CURRENT_LIMIT_LOCK (1U << 31)
#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */
#define MSR_PP1_CURRENT_CONFIG 0x602
#define PP1_CURRENT_LIMIT_LOCK (1U << 31)
#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */
#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */
#define MSR_PKG_POWER_SKU_UNIT 0x606
@@ -129,7 +131,6 @@ void intel_model_206ax_finalize_smm(void);
/* Configure power limits for turbo mode */
void set_power_limits(u8 power_limit_1_time);
int cpu_config_tdp_levels(void);
int get_platform_id(void);
static inline u8 cpu_stepping(void)
{

View File

@@ -16,6 +16,7 @@
#include <cpu/intel/smm_reloc.h>
#include <cpu/intel/common/common.h>
#include <smbios.h>
#include <smp/node.h>
#include <types.h>
/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
@@ -170,45 +171,54 @@ static void configure_c_states(void)
msr.lo |= (1 << 15); // Lock C-State MSR
wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
msr = rdmsr(MSR_MISC_PWR_MGMT);
msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination
wrmsr(MSR_MISC_PWR_MGMT, msr);
if (boot_cpu()) {
/*
* The following MSRs are in scope 'Package', thus it's sufficient
* to write them once on one core.
*/
msr = rdmsr(MSR_POWER_CTL);
msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0
msr.lo |= (1 << 1); // C1E Enable
msr.lo |= (1 << 0); // Bi-directional PROCHOT#
wrmsr(MSR_POWER_CTL, msr);
msr = rdmsr(MSR_MISC_PWR_MGMT);
msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination
wrmsr(MSR_MISC_PWR_MGMT, msr);
/* C3 Interrupt Response Time Limit */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
wrmsr(MSR_PKGC3_IRTL, msr);
msr = rdmsr(MSR_POWER_CTL);
msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0
msr.lo |= (1 << 1); // C1E Enable
msr.lo |= (1 << 0); // Bi-directional PROCHOT#
wrmsr(MSR_POWER_CTL, msr);
/* C6 Interrupt Response Time Limit */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
wrmsr(MSR_PKGC6_IRTL, msr);
/* C3 Interrupt Response Time Limit */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
wrmsr(MSR_PKGC3_IRTL, msr);
/* C7 Interrupt Response Time Limit */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
wrmsr(MSR_PKGC7_IRTL, msr);
/* C6 Interrupt Response Time Limit */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
wrmsr(MSR_PKGC6_IRTL, msr);
/* Primary Plane Current Limit */
msr = rdmsr(MSR_PP0_CURRENT_CONFIG);
msr.lo &= ~0x1fff;
msr.lo |= PP0_CURRENT_LIMIT;
wrmsr(MSR_PP0_CURRENT_CONFIG, msr);
/* C7 Interrupt Response Time Limit */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
wrmsr(MSR_PKGC7_IRTL, msr);
/* Secondary Plane Current Limit */
msr = rdmsr(MSR_PP1_CURRENT_CONFIG);
msr.lo &= ~0x1fff;
if (cpuid_eax(1) >= 0x30600)
msr.lo |= PP1_CURRENT_LIMIT_IVB;
else
msr.lo |= PP1_CURRENT_LIMIT_SNB;
wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
/* Primary Plane Current Limit */
msr = rdmsr(MSR_PP0_CURRENT_CONFIG);
msr.lo &= ~0x1fff;
msr.lo |= PP0_CURRENT_LIMIT;
msr.lo |= PP0_CURRENT_LIMIT_LOCK;
wrmsr(MSR_PP0_CURRENT_CONFIG, msr);
/* Secondary Plane Current Limit */
msr = rdmsr(MSR_PP1_CURRENT_CONFIG);
msr.lo &= ~0x1fff;
if (IS_IVY_CPU(cpu_get_cpuid()))
msr.lo |= PP1_CURRENT_LIMIT_IVB;
else
msr.lo |= PP1_CURRENT_LIMIT_SNB;
msr.lo |= PP1_CURRENT_LIMIT_LOCK;
wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
}
}
static void configure_thermal_target(struct device *dev)
@@ -216,13 +226,20 @@ static void configure_thermal_target(struct device *dev)
struct cpu_intel_model_206ax_config *conf = dev->bus->dev->chip_info;
msr_t msr;
/* Set TCC activation offset if supported */
msr = rdmsr(MSR_PLATFORM_INFO);
if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
msr = rdmsr(MSR_TEMPERATURE_TARGET);
msr.lo &= ~(0xf << 24); /* Bits 27:24 */
msr.lo |= (conf->tcc_offset & 0xf) << 24;
wrmsr(MSR_TEMPERATURE_TARGET, msr);
if (boot_cpu()) {
/*
* The following MSR is in scope 'Package', thus it's sufficient
* to write it once on one core.
*/
/* Set TCC activation offset if supported */
msr = rdmsr(MSR_PLATFORM_INFO);
if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
msr = rdmsr(MSR_TEMPERATURE_TARGET);
msr.lo &= ~(0xf << 24); /* Bits 27:24 */
msr.lo |= (conf->tcc_offset & 0xf) << 24;
wrmsr(MSR_TEMPERATURE_TARGET, msr);
}
}
}
@@ -241,10 +258,17 @@ static void configure_misc(void)
msr.hi = 0;
wrmsr(IA32_THERM_INTERRUPT, msr);
/* Enable package critical interrupt only */
msr.lo = 1 << 4;
msr.hi = 0;
wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
if (boot_cpu()) {
/*
* The following MSR is in scope 'Package', thus it's sufficient
* to write it once on one core.
*/
/* Enable package critical interrupt only */
msr.lo = 1 << 4;
msr.hi = 0;
wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
}
}
static void set_max_ratio(void)
@@ -299,9 +323,6 @@ static void model_206ax_report(void)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
/* Print platform ID */
printk(BIOS_INFO, "CPU: platform id %x\n", get_platform_id());
/* CPUID and features */
cpu_id = cpu_get_cpuid();
printk(BIOS_INFO, "CPU: cpuid(1) 0x%x\n", cpu_id);

View File

@@ -297,10 +297,6 @@ config YABEL_DIRECTHW
they can still access all devices in the system.
Enable this option for a good compromise between security and speed.
config MULTIPLE_VGA_ADAPTERS
bool
default n
menu "Display"
depends on HAVE_VGA_TEXT_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER

View File

@@ -11,6 +11,8 @@
bool i2c_dev_detect(struct device *dev, unsigned int addr)
{
struct i2c_msg seg = { .flags = 0, .slave = addr, .buf = NULL, .len = 0 };
if (!dev)
return false;
return dev->ops->ops_i2c_bus->transfer(dev, &seg, 1) == 0;
}

View File

@@ -169,10 +169,8 @@ struct rom_header *pci_rom_load(struct device *dev,
* devices have a mismatch between the hardware and the ROM.
*/
if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
#if !CONFIG(MULTIPLE_VGA_ADAPTERS)
extern struct device *vga_pri; /* Primary VGA device (device.c). */
if (dev != vga_pri) return NULL; /* Only one VGA supported. */
#endif
if ((void *)PCI_VGA_RAM_IMAGE_START != rom_header) {
printk(BIOS_DEBUG,
"Copying VGA ROM Image from %p to 0x%x, 0x%x bytes\n",

View File

@@ -1,38 +0,0 @@
config DRIVERS_GFX_NVIDIA
bool
default n
help
Support for NVIDIA Optimus graphics
config DRIVERS_GFX_NVIDIA_BRIDGE
hex "PCI bridge for the GPU device"
default 0x01
depends on DRIVERS_GFX_NVIDIA
config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
depends on DRIVERS_GFX_NVIDIA
bool
default n
help
Support for NVIDIA Dynamic Boost
config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
int "Total processor power offset from default TGP in watts"
default 45
depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
help
This identifies the available power for the CPU or GPU boost
config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN
int "Minimum TGP offset from default TGP in watts"
default 0
depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
help
This is used to transfer power from the GPU to the CPU
config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
int "Maximum TGP offset from default TGP in watts"
default 0
depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
help
This is used to transfer power from the CPU to the GPU

View File

@@ -1,5 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c

View File

@@ -1,96 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* NVIDIA GC6 on CFL and CML CPU PCIe ports */
// Memory mapped PCI express config space
OperationRegion (PCIC, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + (CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15), 0x1000)
Field (PCIC, ByteAcc, NoLock, Preserve) {
PVID, 16,
PDID, 16,
Offset (0x248),
, 7,
L23E, 1, /* L23_Rdy Entry Request */
L23R, 1, /* L23_Rdy to Detect Transition */
Offset (0xC20),
, 4,
P0AP, 2, /* Additional power savings */
Offset (0xC38),
, 3,
P0RM, 1, /* Robust squelch mechanism */
}
// Enter L23
Method (DL23, 0, Serialized) {
Printf(" GPU PORT DL23 START")
L23E = 1
Sleep (16)
Local0 = 0
While (L23E) {
If ((Local0 > 4)) {
Break
}
Sleep (16)
Local0++
}
P0RM = 1
P0AP = 3
Printf(" GPU PORT DL23 FINISH")
}
// Exit L23
Method (L23D, 0, Serialized) {
Printf(" GPU PORT L23D START")
L23R = 1
Sleep (16)
Local0 = 0
While (L23R) {
If ((Local0 > 4)) {
Break
}
Sleep (16)
Local0++
}
P0RM = 0
P0AP = 0
Printf(" GPU PORT L23D FINISH")
}
// Main power resource
PowerResource (PWRR, 0, 0) {
Name (_STA, 1)
Method (_ON, 0, Serialized) {
Printf("GPU PORT PWRR._ON")
^^DEV0._ON()
_STA = 1
}
Method (_OFF, 0, Serialized) {
Printf("GPU PORT PWRR._OFF")
^^DEV0._OFF()
_STA = 0
}
}
// Power resources for entering D0
Name (_PR0, Package () { PWRR })
// Power resources for entering D3
Name (_PR3, Package () { PWRR })
#include "common/gpu.asl"

View File

@@ -1,30 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#define NV_ERROR_SUCCESS 0x0
#define NV_ERROR_UNSPECIFIED 0x80000001
#define NV_ERROR_UNSUPPORTED 0x80000002
#include "gps.asl"
#include "nvjt.asl"
Method (_DSM, 4, Serialized) {
Printf("GPU _DSM")
If (Arg0 == ToUUID (JT_DSM_GUID)) {
If (ToInteger(Arg1) >= JT_REVISION_ID_MIN) {
Return (NVJT(Arg2, Arg3))
} Else {
Printf(" Unsupported JT revision: %o", SFST(Arg1))
Return (NV_ERROR_UNSUPPORTED)
}
} ElseIf (Arg0 == ToUUID (GPS_DSM_GUID)) {
If (ToInteger(Arg1) == GPS_REVISION_ID) {
Return (GPS(Arg2, Arg3))
} Else {
Printf(" Unsupported GPS revision: %o", SFST(Arg1))
Return (NV_ERROR_UNSUPPORTED)
}
} Else {
Printf(" Unsupported GUID: %o", IDST(Arg0))
Return (NV_ERROR_UNSPECIFIED)
}
}

View File

@@ -1,66 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#define GPS_DSM_GUID "A3132D01-8CDA-49BA-A52E-BC9D46DF6B81"
#define GPS_REVISION_ID 0x00000200
#define GPS_FUNC_SUPPORT 0x00000000
#define GPS_FUNC_PSHARESTATUS 0x00000020
#define GPS_FUNC_PSHAREPARAMS 0x0000002A
Method(GPS, 2, Serialized) {
Printf(" GPU GPS")
Switch(ToInteger(Arg0)) {
Case(GPS_FUNC_SUPPORT) {
Printf(" Supported Functions")
Return(ITOB(
(1 << GPS_FUNC_SUPPORT) |
(1 << GPS_FUNC_PSHARESTATUS) |
(1 << GPS_FUNC_PSHAREPARAMS)
))
}
Case(GPS_FUNC_PSHARESTATUS) {
Printf(" Power Share Status")
Return(ITOB(0))
}
Case(GPS_FUNC_PSHAREPARAMS) {
Printf(" Power Share Parameters")
CreateField(Arg1, 0, 4, QTYP) // Query type
Name(GPSP, Buffer(36) { 0x00 })
CreateDWordField(GPSP, 0, RSTS) // Response status
CreateDWordField(GPSP, 4, VERS) // Version
// Set query type of response
RSTS = QTYP
// Set version of response
VERS = 0x00010000
Switch(ToInteger(QTYP)) {
Case(0) {
Printf(" Request Current Information")
// No required information
Return(GPSP)
}
Case(1) {
Printf(" Request Supported Fields")
// Support GPU temperature field
RSTS |= (1 << 8)
Return(GPSP)
}
Case(2) {
Printf(" Request Current Limits")
// No required limits
Return(GPSP)
}
Default {
Printf(" Unknown Query: %o", SFST(QTYP))
Return(NV_ERROR_UNSUPPORTED)
}
}
}
Default {
Printf(" Unsupported function: %o", SFST(Arg0))
Return(NV_ERROR_UNSUPPORTED)
}
}
}

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@@ -1,18 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Device (DEV0) {
Name(_ADR, 0x00000000)
#include "utility.asl"
#include "dsm.asl"
#include "power.asl"
}
#if CONFIG(DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST)
Scope (\_SB) {
Device(NPCF) {
#include "utility.asl"
#include "nvpcf.asl"
}
}
#endif

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@@ -1,152 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#define JT_DSM_GUID "CBECA351-067B-4924-9CBD-B46B00B86F34"
#define JT_REVISION_ID_MIN 0x00000100
#define JT_REVISION_ID_MAX 0x00000200
#define JT_FUNC_SUPPORT 0x00000000
#define JT_FUNC_CAPS 0x00000001
#define JT_FUNC_POWERCONTROL 0x00000003
//TODO: SMI traps and EGIN/XCLM
#define JT_GPC_GSS 0 // Get current GPU GCx sleep status
#define JT_GPC_EGNS 1 // Enter GC6 without self-refresh
#define JT_GPC_EGIS 2 // Enter GC6 with self-refresh
#define JT_GPC_XGXS 3 // Exit GC6 and stop self-refresh
#define JT_GPC_XGIS 4 // Exit GC6 for self-refresh update
#define JT_DFGC_NONE 0 // Handle request immediately
#define JT_DFGC_DEFER 1 // Defer GPC and GPCX
//TODO #define JT_DFGC_CLEAR 2 // Clear pending requests
// Deferred GC6 enter/exit until D3-cold (saved DFGC)
Name(DFEN, 0)
// Deferred GC6 enter control (saved GPC)
Name(DFCI, 0)
// Deferred GC6 exit control (saved GPCX)
Name(DFCO, 0)
Method (NVJT, 2, Serialized) {
Printf(" GPU NVJT")
Switch (ToInteger(Arg0)) {
Case (JT_FUNC_SUPPORT) {
Printf(" Supported Functions")
Return(ITOB(
(1 << JT_FUNC_SUPPORT) |
(1 << JT_FUNC_CAPS) |
(1 << JT_FUNC_POWERCONTROL)
))
}
Case (JT_FUNC_CAPS) {
Printf(" Capabilities")
Return(ITOB(
(1 << 0) | // G-SYNC NSVR power-saving features are enabled
(1 << 1) | // NVSR disabled
(2 << 3) | // Panel power and backlight are on the suspend rail
(0 << 5) | // self-refresh controller remains powered while panel is powered
(0 << 6) | // FB is not on the suspend rail but is powered on in GC6
(0 << 8) | // Combined power rail for all GPUs
(0 << 10) | // External SPI ROM
(1 << 11) | // No SMI handler for kernel panic exit while in GC6
(0 << 12) | // Supports notify on GC6 state done
(1 << 13) | // Support deferred GC6
(1 << 14) | // Support fine-grained root port control
(2 << 15) | // GC6 version is GC6-R
(0 << 17) | // GC6 exit ISR is not supported
(0 << 18) | // GC6 self wakeup not supported
(JT_REVISION_ID_MAX << 20) // Highest revision supported
))
}
Case (JT_FUNC_POWERCONTROL) {
Printf(" Power Control: %o", SFST(Arg1))
CreateField (Arg1, 0, 3, GPC) // GPU power control
CreateField (Arg1, 4, 1, PPC) // Panel power control
CreateField (Arg1, 14, 2, DFGC) // Defer GC6 enter/exit until D3 cold
CreateField (Arg1, 16, 3, GPCX) // Deferred GC6 exit control
// Save deferred GC6 request
If ((ToInteger(GPC) != 0) || (ToInteger(DFGC) != 0)) {
DFEN = DFGC
DFCI = GPC
DFCO = GPCX
}
// Buffer to cache current state
Name (JTBF, Buffer (4) { 0, 0, 0, 0 })
CreateField (JTBF, 0, 3, CGCS) // Current GC state
CreateField (JTBF, 3, 1, CGPS) // Current GPU power status
CreateField (JTBF, 7, 1, CPSS) // Current panel and SRC state (0 when on)
// If doing deferred GC6 request, return now
If (ToInteger(DFGC) != 0) {
CGCS = 1
CGPS = 1
Return (JTBF)
}
// Apply requested state
Switch (ToInteger(GPC)) {
Case (JT_GPC_GSS) {
Printf(" Get current GPU GCx sleep status")
//TODO: include transitions!
If (GTXS(DGPU_RST_N)) {
// GPU powered on
CGCS = 1
CGPS = 1
} ElseIf (GTXS(DGPU_PWR_EN)) {
// GPU powered off, GC6
CGCS = 3
CGPS = 0
} Else {
// GPU powered off, D3 cold
CGCS = 2
CGPS = 0
}
}
Case (JT_GPC_EGNS) {
Printf(" Enter GC6 without self-refresh")
GC6I()
CPSS = 1
}
Case (JT_GPC_EGIS) {
Printf(" Enter GC6 with self-refresh")
GC6I()
If (ToInteger(PPC) == 0) {
CPSS = 0
}
}
Case (JT_GPC_XGXS) {
Printf(" Exit GC6 and stop self-refresh")
GC6O()
CGCS = 1
CGPS = 1
If (ToInteger(PPC) != 0) {
CPSS = 0
}
}
Case (JT_GPC_XGIS) {
Printf(" Exit GC6 for self-refresh update")
GC6O()
CGCS = 1
CGPS = 1
If (ToInteger(PPC) != 0) {
CPSS = 0
}
}
Default {
Printf(" Unsupported GPU power control: %o", SFST(GPC))
}
}
Return (JTBF)
}
Default {
Printf(" Unsupported function: %o", SFST(Arg0))
Return (NV_ERROR_UNSUPPORTED)
}
}
}

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@@ -1,113 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#define NVPCF_DSM_GUID "36b49710-2483-11e7-9598-0800200c9a66"
#define NVPCF_REVISION_ID 0x00000200
#define NVPCF_ERROR_SUCCESS 0x0
#define NVPCF_ERROR_GENERIC 0x80000001
#define NVPCF_ERROR_UNSUPPORTED 0x80000002
#define NVPCF_FUNC_GET_SUPPORTED 0x00000000
#define NVPCF_FUNC_GET_STATIC_CONFIG_TABLES 0x00000001
#define NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS 0x00000002
Name(_HID, "NVDA0820")
Name(_UID, "NPCF")
Method(_DSM, 4, Serialized) {
Printf("NVPCF _DSM")
If (Arg0 == ToUUID(NVPCF_DSM_GUID)) {
If (ToInteger(Arg1) == NVPCF_REVISION_ID) {
Return(NPCF(Arg2, Arg3))
} Else {
Printf(" Unsupported NVPCF revision: %o", SFST(Arg1))
Return(NVPCF_ERROR_GENERIC)
}
} Else {
Printf(" Unsupported GUID: %o", IDST(Arg0))
Return(NVPCF_ERROR_GENERIC)
}
}
Method(NPCF, 2, Serialized) {
Printf(" NVPCF NPCF")
Switch(ToInteger(Arg0)) {
Case(NVPCF_FUNC_GET_SUPPORTED) {
Printf(" Supported Functions")
Return(ITOB(
(1 << NVPCF_FUNC_GET_SUPPORTED) |
(1 << NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) |
(1 << NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS)
))
}
Case(NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) {
Printf(" Get Static Config")
Return(Buffer(14) {
// Device table header
0x20, 0x03, 0x01,
// Intel + NVIDIA
0x00,
// Controller table header
0x23, 0x04, 0x05, 0x01,
// Dynamic boost controller
0x01,
// Supports DC
0x01,
// Reserved
0x00, 0x00, 0x00,
// Checksum
0xAD
})
}
Case(NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS) {
Printf(" Update Dynamic Boost")
CreateField(Arg1, 0x28, 2, ICMD) // Input command
Name(PCFP, Buffer(49) {
// Table version
0x23,
// Table header size
0x05,
// Size of common status in bytes
0x10,
// Size of controller entry in bytes
0x1C,
// Other fields filled in later
})
CreateByteField(PCFP, 0x04, CCNT) // Controller count
CreateWordField(PCFP, 0x19, ATPP) // AC TPP offset
CreateWordField(PCFP, 0x1D, AMXP) // AC maximum TGP offset
CreateWordField(PCFP, 0x21, AMNP) // AC minimum TGP offset
Switch(ToInteger(ICMD)) {
Case(0) {
Printf(" Get Controller Params")
// Number of controllers
CCNT = 1
// AC total processor power offset from default TGP in 1/8 watt units
ATPP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP << 3)
// AC maximum TGP offset from default TGP in 1/8 watt units
AMXP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX << 3)
// AC minimum TGP offset from default TGP in 1/8 watt units
AMNP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN << 3)
Printf("PCFP: %o", SFST(PCFP))
Return(PCFP)
}
Case(1) {
Printf(" Set Controller Status")
//TODO
Printf("PCFP: %o", SFST(PCFP))
Return(PCFP)
}
Default {
Printf(" Unknown Input Command: %o", SFST(ICMD))
Return(NV_ERROR_UNSUPPORTED)
}
}
}
Default {
Printf(" Unsupported function: %o", SFST(Arg0))
Return(NVPCF_ERROR_UNSUPPORTED)
}
}
}

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@@ -1,120 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
//TODO: evaluate sleeps
OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
Field (PCIC, DwordAcc, NoLock, Preserve) {
Offset (0x40),
SSID, 32, // Subsystem vendor and product ID
}
// Enter GC6
Method(GC6I, 0, Serialized) {
Printf(" GPU GC6I START")
// Enter L23
^^DL23()
Sleep(5)
// Put GPU into reset
Printf(" Put GPU into reset")
CTXS(DGPU_RST_N)
Sleep(5)
Printf(" GPU GC6I FINISH")
}
// Exit GC6
Method(GC6O, 0, Serialized) {
Printf(" GPU GC6O START")
// Bring GPU out of reset
Printf(" Bring GPU out of reset")
STXS(DGPU_RST_N)
Sleep(5)
// Exit L23
^^L23D()
Sleep(5)
Printf(" GPU GC6O FINISH")
}
Method (_ON, 0, Serialized) {
Printf(" GPU _ON START")
If (DFEN == JT_DFGC_DEFER) {
Switch (ToInteger(DFCO)) {
Case (JT_GPC_XGXS) {
Printf(" Exit GC6 and stop self-refresh")
GC6O()
}
Default {
Printf(" Unsupported DFCO: %o", SFST(DFCO))
}
}
DFEN = JT_DFGC_NONE
} Else {
Printf(" Standard RTD3 power on")
STXS(DGPU_PWR_EN)
Sleep(5)
GC6O()
}
Printf(" GPU _ON FINISH")
}
Method (_OFF, 0, Serialized) {
Printf(" GPU _OFF START")
If (DFEN == JT_DFGC_DEFER) {
Switch (ToInteger(DFCI)) {
Case (JT_GPC_EGNS) {
Printf(" Enter GC6 without self-refresh")
GC6I()
}
Case (JT_GPC_EGIS) {
Printf(" Enter GC6 with self-refresh")
GC6I()
}
Default {
Printf(" Unsupported DFCI: %o", SFST(DFCI))
}
}
DFEN = JT_DFGC_NONE
} Else {
Printf(" Standard RTD3 power off")
GC6I()
CTXS(DGPU_PWR_EN)
Sleep(5)
}
Printf(" GPU _OFF FINISH")
}
// Main power resource
PowerResource (PWRR, 0, 0) {
Name (_STA, 1)
Method (_ON, 0, Serialized) {
Printf("GPU PWRR._ON")
// Restore SSID
^^SSID = DGPU_SSID
Printf(" Restore SSID: %o", SFST(^^SSID))
_STA = 1
}
Method (_OFF, 0, Serialized) {
Printf("GPU PWRR._OFF")
_STA = 0
}
}
// Power resources for entering D0
Name (_PR0, Package () { PWRR })
// Power resources for entering D3
Name (_PR3, Package () { PWRR })

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@@ -1,63 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
// Convert a byte to a hex string, trimming extra parts
Method (BHEX, 1) {
Local0 = ToHexString(Arg0)
Return (Mid(Local0, SizeOf(Local0) - 2, 2))
}
// UUID to string
Method (IDST, 1) {
Local0 = ""
Fprintf(
Local0,
"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
BHEX(DerefOf(Arg0[3])),
BHEX(DerefOf(Arg0[2])),
BHEX(DerefOf(Arg0[1])),
BHEX(DerefOf(Arg0[0])),
BHEX(DerefOf(Arg0[5])),
BHEX(DerefOf(Arg0[4])),
BHEX(DerefOf(Arg0[7])),
BHEX(DerefOf(Arg0[6])),
BHEX(DerefOf(Arg0[8])),
BHEX(DerefOf(Arg0[9])),
BHEX(DerefOf(Arg0[10])),
BHEX(DerefOf(Arg0[11])),
BHEX(DerefOf(Arg0[12])),
BHEX(DerefOf(Arg0[13])),
BHEX(DerefOf(Arg0[14])),
BHEX(DerefOf(Arg0[15]))
)
Return (Local0)
}
// Safe hex conversion, checks type first
Method (SFST, 1) {
Local0 = ObjectType(Arg0)
If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
Return (ToHexString(Arg0))
} Else {
Return (Concatenate("Type: ", Arg0))
}
}
// Convert from 4-byte buffer to 32-bit integer
Method (BTOI, 1) {
Return(
DerefOf(Arg0[0]) |
(DerefOf(Arg0[1]) << 8) |
(DerefOf(Arg0[2]) << 16) |
(DerefOf(Arg0[3]) << 24)
)
}
// Convert from 32-bit integer to 4-byte buffer
Method (ITOB, 1) {
Local0 = Buffer(4) { 0, 0, 0, 0 }
Local0[0] = Arg0 & 0xFF
Local0[1] = (Arg0 >> 8) & 0xFF
Local0[2] = (Arg0 >> 16) & 0xFF
Local0[3] = (Arg0 >> 24) & 0xFF
Return (Local0)
}

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@@ -1,140 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* NVIDIA GC6 on (TGL and ADL) (CPU and PCH) PCIe ports */
// Port mapped PCI express config space
OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
Field (PCIC, AnyAcc, NoLock, Preserve) {
Offset(0x52), /* LSTS - Link Status Register */
, 13,
LASX, 1, /* 0, Link Active Status */
Offset(0x60), /* RSTS - Root Status Register */
, 16,
PSPX, 1, /* 16, PME Status */
Offset(0xD8), /* 0xD8, MPC - Miscellaneous Port Configuration Register */
, 30,
HPEX, 1, /* 30, Hot Plug SCI Enable */
PMEX, 1, /* 31, Power Management SCI Enable */
Offset (0xE0), /* 0xE0, SPR - Scratch Pad Register */
SCB0, 1, /* Scratch bit 0 */
Offset(0xE2), /* 0xE2, RPPGEN - Root Port Power Gating Enable */
, 2,
L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */
L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */
}
Field (PCIC, AnyAcc, NoLock, WriteAsZeros) {
Offset(0xDC), /* 0xDC, SMSCS - SMI/SCI Status Register */
, 30,
HPSX, 1, /* 30, Hot Plug SCI Status */
PMSX, 1 /* 31, Power Management SCI Status */
}
// Enter L23
Method (DL23, 0, Serialized) {
Printf(" GPU PORT DL23 START")
L23E = 1
Sleep (16)
Local0 = 0
While (L23E) {
If ((Local0 > 4)) {
Break
}
Sleep (16)
Local0++
}
SCB0 = 1
Printf(" GPU PORT DL23 FINISH")
}
// Exit L23
Method (L23D, 0, Serialized) {
Printf(" GPU PORT L23D START")
If ((SCB0 == 1)) {
L23R = 1
Local0 = 0
While (L23R) {
If ((Local0 > 4)) {
Break
}
Sleep (16)
Local0++
}
SCB0 = 0
Local0 = 0
While ((LASX == 0)) {
If ((Local0 > 8)) {
Break
}
Sleep (16)
Local0++
}
}
Printf(" GPU PORT L23D FINISH")
}
Method (HPME, 0, Serialized) {
Printf(" GPU PORT HPME START")
If (PMSX == 1) {
Printf(" Notify GPU driver of PME SCI")
Notify(DEV0, 0x2)
Printf(" Clear PME SCI")
PMSX = 1
Printf(" Consume PME notification")
PSPX = 1
}
Printf(" GPU PORT HPME FINISH")
}
// Main power resource
PowerResource (PWRR, 0, 0) {
Name (_STA, 1)
Method (_ON, 0, Serialized) {
Printf("GPU PORT PWRR._ON")
HPME();
If (PMEX == 1) {
Printf(" Disable power management SCI")
PMEX = 0
}
^^DEV0._ON()
_STA = 1
}
Method (_OFF, 0, Serialized) {
Printf("GPU PORT PWRR._OFF")
^^DEV0._OFF()
If (PMEX == 0) {
Printf(" Enable power management SCI")
PMEX = 1
HPME()
}
_STA = 0
}
}
// Power resources for entering D0
Name (_PR0, Package () { PWRR })
// Power resources for entering D3
Name (_PR3, Package () { PWRR })
#include "common/gpu.asl"

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@@ -1,10 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_
#define _DRIVERS_GFX_NVIDIA_CHIP_H_
struct drivers_gfx_nvidia_config {
/* TODO: Set GPIOs in devicetree? */
};
#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */

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@@ -1,19 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_
#define _DRIVERS_GFX_NVIDIA_GPU_H_
#include <stdbool.h>
struct nvidia_gpu_config {
/* GPIO for GPU_PWR_EN */
unsigned int power_gpio;
/* GPIO for GPU_RST# */
unsigned int reset_gpio;
/* Enable or disable GPU power */
bool enable;
};
void nvidia_set_power(const struct nvidia_gpu_config *config);
#endif /* _DRIVERS_NVIDIA_GPU_H_ */

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@@ -1,71 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include "chip.h"
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40
static void nvidia_read_resources(struct device *dev)
{
printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev));
pci_dev_read_resources(dev);
// Find all BARs on GPU, mark them above 4g if prefetchable
for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
struct resource *res = probe_resource(dev, bar);
if (res) {
if (res->flags & IORESOURCE_PREFETCH) {
printk(BIOS_INFO, " BAR at 0x%02x marked above 4g\n", bar);
res->flags |= IORESOURCE_ABOVE_4G;
} else {
printk(BIOS_DEBUG, " BAR at 0x%02x not prefetch\n", bar);
}
} else {
printk(BIOS_DEBUG, " BAR at 0x%02x not found\n", bar);
}
}
}
static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
{
pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations nvidia_device_ops_pci = {
.set_subsystem = nvidia_set_subsystem,
};
static struct device_operations nvidia_device_ops = {
.read_resources = nvidia_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = pci_rom_write_acpi_tables,
.acpi_fill_ssdt = pci_rom_ssdt,
#endif
.init = pci_dev_init,
.ops_pci = &nvidia_device_ops_pci,
};
static void nvidia_enable(struct device *dev)
{
if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
return;
if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_NVIDIA)
return;
dev->ops = &nvidia_device_ops;
}
struct chip_operations drivers_gfx_nvidia_ops = {
CHIP_NAME("NVIDIA Optimus Graphics Device")
.enable_dev = nvidia_enable
};

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@@ -1,33 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <gpio.h>
#include "chip.h"
#include "gpu.h"
void nvidia_set_power(const struct nvidia_gpu_config *config)
{
if (!config->power_gpio || !config->reset_gpio) {
printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__);
return;
}
printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio);
printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio);
gpio_set(config->reset_gpio, 0);
mdelay(10);
if (config->enable) {
gpio_set(config->power_gpio, 1);
mdelay(25);
gpio_set(config->reset_gpio, 1);
} else {
gpio_set(config->power_gpio, 0);
}
mdelay(10);
}

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@@ -1,5 +0,0 @@
config DRIVERS_INTEL_DTBT
bool
default n
help
Support for discrete Thunderbolt controllers

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@@ -1,3 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
ramstage-$(CONFIG_DRIVERS_INTEL_DTBT) += dtbt.c

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _DRIVERS_INTEL_DTBT_CHIP_H_
#define _DRIVERS_INTEL_DTBT_CHIP_H_
struct drivers_intel_dtbt_config {};
#endif /* _DRIVERS_INTEL_DTBT_CHIP_H_ */

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@@ -1,215 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include "chip.h"
#include <acpi/acpigen.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
#define PCIE2TBT 0x54C
#define PCIE2TBT_GO2SX ((0x02 << 1) | 1)
#define PCIE2TBT_GO2SX_NO_WAKE ((0x03 << 1) | 1)
#define PCIE2TBT_SX_EXIT_TBT_CONNECTED ((0x04 << 1) | 1)
#define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED ((0x05 << 1) | 1)
#define PCIE2TBT_SET_SECURITY_LEVEL ((0x08 << 1) | 1)
#define PCIE2TBT_GET_SECURITY_LEVEL ((0x09 << 1) | 1)
#define PCIE2TBT_BOOT_ON ((0x18 << 1) | 1)
#define TBT2PCIE 0x548
static void dtbt_cmd(struct device *dev, u32 command)
{
printk(BIOS_DEBUG, "DTBT send command %08x\n", command);
pci_write_config32(dev, PCIE2TBT, command);
u32 timeout;
u32 status;
for (timeout = 1000000; timeout > 0; timeout--) {
status = pci_read_config32(dev, TBT2PCIE);
if (status & 1) {
break;
}
udelay(1);
}
if (timeout == 0) {
printk(BIOS_ERR, "DTBT command %08x timeout on status %08x\n", command, status);
}
printk(BIOS_DEBUG, "DTBT command %08x status %08x\n", command, status);
pci_write_config32(dev, PCIE2TBT, 0);
u32 status_clear;
for (timeout = 1000000; timeout > 0; timeout--) {
status_clear = pci_read_config32(dev, TBT2PCIE);
if (!(status_clear & 1)) {
break;
}
udelay(1);
}
if (timeout == 0) {
printk(BIOS_ERR, "DTBT command %08x timeout on status clear %08x\n", command, status_clear);
}
}
static void dtbt_fill_ssdt(const struct device *dev)
{
printk(BIOS_DEBUG, "DTBT fill SSDT\n");
if (!dev) {
printk(BIOS_ERR, "DTBT device invalid\n");
}
printk(BIOS_DEBUG, " Dev %s\n", dev_path(dev));
struct bus *bus = dev->bus;
if (!bus) {
printk(BIOS_ERR, "DTBT bus invalid\n");
}
printk(BIOS_DEBUG, " Bus %s\n", bus_path(bus));
struct device *parent = bus->dev;
if (!parent || parent->path.type != DEVICE_PATH_PCI) {
printk(BIOS_ERR, "DTBT parent invalid\n");
return;
}
printk(BIOS_DEBUG, " Parent %s\n", dev_path(parent));
const char *parent_scope = acpi_device_path(parent);
if (!parent_scope) {
printk(BIOS_ERR, "DTBT parent scope not valid\n");
return;
}
{ /* Scope */
printk(BIOS_DEBUG, " Scope %s\n", parent_scope);
acpigen_write_scope(parent_scope);
struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
/* Indicate that device supports hotplug in D3. */
acpi_device_add_hotplug_support_in_d3(dsd);
/* Indicate that port is external. */
acpi_device_add_external_facing_port(dsd);
acpi_dp_write(dsd);
{ /* Device */
const char *dev_name = acpi_device_name(dev);
printk(BIOS_DEBUG, " Device %s\n", dev_name);
acpigen_write_device(dev_name);
acpigen_write_name_integer("_ADR", 0);
uintptr_t mmconf_base = (uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS
+ (((uintptr_t)(bus->secondary)) << 20);
printk(BIOS_DEBUG, " MMCONF base %08lx\n", mmconf_base);
const struct opregion opregion = OPREGION("PXCS", SYSTEMMEMORY, mmconf_base, 0x1000);
const struct fieldlist fieldlist[] = {
FIELDLIST_OFFSET(TBT2PCIE),
FIELDLIST_NAMESTR("TB2P", 32),
FIELDLIST_OFFSET(PCIE2TBT),
FIELDLIST_NAMESTR("P2TB", 32),
};
acpigen_write_opregion(&opregion);
acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist),
FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE);
{ /* Method */
acpigen_write_method_serialized("PTS", 0);
acpigen_write_debug_string("DTBT prepare to sleep");
acpigen_write_store_int_to_namestr(PCIE2TBT_GO2SX_NO_WAKE, "P2TB");
acpigen_write_delay_until_namestr_int(600, "TB2P", PCIE2TBT_GO2SX_NO_WAKE);
acpigen_write_debug_namestr("TB2P");
acpigen_write_store_int_to_namestr(0, "P2TB");
acpigen_write_delay_until_namestr_int(600, "TB2P", 0);
acpigen_write_debug_namestr("TB2P");
acpigen_write_method_end();
}
acpigen_write_device_end();
}
acpigen_write_scope_end();
}
{ /* Scope */
acpigen_write_scope("\\");
{ /* Method */
acpigen_write_method("TBTS", 0);
acpigen_emit_namestring(acpi_device_path_join(dev, "PTS"));
acpigen_write_method_end();
}
acpigen_write_scope_end();
}
}
static const char *dtbt_acpi_name(const struct device *dev)
{
return "DTBT";
}
static struct pci_operations dtbt_device_ops_pci = {
.set_subsystem = 0,
};
static struct device_operations dtbt_device_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.acpi_fill_ssdt = dtbt_fill_ssdt,
.acpi_name = dtbt_acpi_name,
.scan_bus = pciexp_scan_bridge,
.reset_bus = pci_bus_reset,
.ops_pci = &dtbt_device_ops_pci,
};
static void dtbt_enable(struct device *dev)
{
if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
return;
if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_INTEL)
return;
// TODO: check device ID
dev->ops = &dtbt_device_ops;
printk(BIOS_INFO, "DTBT controller found at %s\n", dev_path(dev));
printk(BIOS_DEBUG, "DTBT get security level\n");
dtbt_cmd(dev, PCIE2TBT_GET_SECURITY_LEVEL);
printk(BIOS_DEBUG, "DTBT set security level SL0\n");
dtbt_cmd(dev, PCIE2TBT_SET_SECURITY_LEVEL);
printk(BIOS_DEBUG, "DTBT get security level\n");
dtbt_cmd(dev, PCIE2TBT_GET_SECURITY_LEVEL);
if (acpi_is_wakeup_s3()) {
printk(BIOS_INFO, "DTBT SX exit\n");
dtbt_cmd(dev, PCIE2TBT_SX_EXIT_TBT_CONNECTED);
} else {
printk(BIOS_INFO, "DTBT boot on\n");
dtbt_cmd(dev, PCIE2TBT_BOOT_ON);
}
}
struct chip_operations drivers_intel_dtbt_ops = {
CHIP_NAME("Intel Discrete Thunderbolt Device")
.enable_dev = dtbt_enable
};

View File

@@ -162,7 +162,7 @@ $(error No second FSP-S binary file specified.)
endif # CONFIG_FSP_S_FILE_2
endif # CONFIG_PLATFORM_USES_SECOND_FSP
else # CONFIG_ADD_FSP_BINARIES
build_complete:: warn_no_fsp_binaries
show_notices:: warn_no_fsp_binaries
endif # CONFIG_ADD_FSP_BINARIES
PHONY+=warn_no_fsp_binaries

View File

@@ -77,8 +77,8 @@ enum {
};
enum {
MAX77686_MV = 0, /* mili volt */
MAX77686_UV /* micro volt */
MAX77686_MV = 0, /* millivolt */
MAX77686_UV /* microvolt */
};
/**

View File

@@ -199,7 +199,7 @@ enum {
#define MAX77802_BUCK_TYPE2_ON (1 << 4)
#define MAX77802_BUCK_TYPE2_IGNORE_PWRREQ (1 << 5)
/* LDO35 1.2 volt value for bridge ic */
/* LDO35 1.2 volt value for bridge IC */
#define MAX77802_LDO35CTRL1_1_2V (1 << 4)
#define MAX77802_LOD35CTRL1_ON (1 << 6)

View File

@@ -21,7 +21,7 @@ struct panel_serializable_data P097PFG_SSD2858 = {
.init = {
PANEL_GENERIC(0xff, 0x00),
/* LOCKCNT=0x1f4, MRX=0, POSTDIV=1 (/2} }, MULT=0x49
* 27 Mhz => 985.5 Mhz */
* 27 MHz => 985.5 MHz */
PANEL_GENERIC(0x00, 0x08, 0x01, 0xf4, 0x01, 0x49),
/* MTXDIV=1, SYSDIV=3 (=> 4) */
PANEL_GENERIC(0x00, 0x0c, 0x00, 0x00, 0x00, 0x03),
@@ -34,7 +34,7 @@ struct panel_serializable_data P097PFG_SSD2858 = {
PANEL_GENERIC(0x10, 0x08, 0x01, 0x20, 0x08, 0x45),
PANEL_GENERIC(0x10, 0x1c, 0x00, 0x00, 0x00, 0x00),
PANEL_GENERIC(0x20, 0x0c, 0x00, 0x00, 0x00, 0x04),
/* Pixel clock 985.5 Mhz * 0x49/0x4b = 959 Mhz */
/* Pixel clock 985.5 MHz * 0x49/0x4b = 959 MHz */
PANEL_GENERIC(0x20, 0x10, 0x00, 0x4b, 0x00, 0x49),
PANEL_GENERIC(0x20, 0xa0, 0x00, 0x00, 0x00, 0x00),
/* EOT=1, LPE = 0, LSOUT=4 lanes, LPD=25 */

View File

@@ -431,7 +431,7 @@ static void log_event_cache_update(uint8_t slot, enum result res)
/* During ramstage this code purposefully uses incoherent transactions between
* read and write. The read assumes a memory-mapped boot device that can be used
* to quickly locate and compare the up-to-date data. However, when an update
* is required it uses the writeable region access to perform the update. */
* is required it uses the writable region access to perform the update. */
static void update_mrc_cache_by_type(int type,
struct mrc_metadata *new_md,
const void *new_data,

View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This driver sets the macaddress of a Atheros AR8121/AR8113/AR8114
* This driver sets the MAC address of an Atheros AR8121/AR8113/AR8114
*/
#include <device/mmio.h>

View File

@@ -64,7 +64,7 @@ enum cxl_memory_mode {
#define DISABLE_BOOTDRIVE "disable_bootdrive"
#define DISABLE_BOOTDRIVE_DEFAULT 0 /* By default don't disable */
/* Skip Global reset so that information in Previous Boot Error Hob won't be cleared */
/* Skip Global reset so that information in Previous Boot Error HOB won't be cleared */
#define SKIP_GLOBAL_RESET "skip_global_reset"
#define SKIP_GLOBAL_RESET_DEFAULT 1

View File

@@ -8,7 +8,6 @@
#include <smmstore.h>
#include <types.h>
#include <cbmem.h>
#include <delay.h>
static struct smmstore_params_info info;
@@ -40,7 +39,6 @@ static void init_store(void *unused)
struct smmstore_params_init args;
uint32_t eax = ~0;
uint32_t ebx;
uint8_t retry = 5;
if (smmstore_get_info(&info) < 0) {
printk(BIOS_INFO, "SMMSTORE: Failed to get meta data\n");
@@ -59,24 +57,14 @@ static void init_store(void *unused)
printk(BIOS_INFO, "SMMSTORE: Setting up SMI handler\n");
/*
* Issue SMI using APM to update the com buffer and to lock the SMMSTORE.
* Retry 5 times in case the SMI isn't triggered immediately.
*/
do {
__asm__ __volatile__ (
"outb %%al, %%dx"
: "=a" (eax)
: "a" ((SMMSTORE_CMD_INIT << 8) | APM_CNT_SMMSTORE),
"b" (ebx),
"d" (APM_CNT)
: "memory");
if (eax == SMMSTORE_RET_SUCCESS)
break;
mdelay(1);
} while (retry--);
/* Issue SMI using APM to update the com buffer and to lock the SMMSTORE */
__asm__ __volatile__ (
"outb %%al, %%dx"
: "=a" (eax)
: "a" ((SMMSTORE_CMD_INIT << 8) | APM_CNT_SMMSTORE),
"b" (ebx),
"d" (APM_CNT)
: "memory");
if (eax != SMMSTORE_RET_SUCCESS) {
printk(BIOS_ERR, "SMMSTORE: Failed to install com buffer\n");

View File

@@ -185,7 +185,7 @@ static enum cb_err scan_end(struct region_device *store)
if (k_sz != 0xffffffff) {
printk(BIOS_WARNING,
"eof of data marker looks invalid: 0x%x\n", k_sz);
"EOF of data marker looks invalid: 0x%x\n", k_sz);
return CB_ERR;
}

View File

@@ -155,6 +155,13 @@ config SPI_FLASH_WINBOND
Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by Winbond.
config SPI_FLASH_ISSI
bool
default y if SPI_FLASH_INCLUDE_ALL_DRIVERS
help
Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by ISSI.
config SPI_FLASH_HAS_VOLATILE_GROUP
bool
default n

View File

@@ -30,6 +30,7 @@ $(1)-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c
$(1)-$(CONFIG_SPI_FLASH_SST) += sst.c
$(1)-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c
$(1)-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c
$(1)-$(CONFIG_SPI_FLASH_ISSI) += issi.c
endef
$(eval $(call add_spi_stage,bootblock,_EARLY))

29
src/drivers/spi/issi.c Normal file
View File

@@ -0,0 +1,29 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <console/console.h>
#include <commonlib/helpers.h>
#include <spi_flash.h>
#include <spi-generic.h>
#include <delay.h>
#include <lib.h>
#include "spi_flash_internal.h"
static const struct spi_flash_part_id flash_table[] = {
{
/* IS25WP256D */
.id[0] = 0x7019,
.nr_sectors_shift = 13,
},
};
const struct spi_flash_vendor_info spi_flash_issi_vi = {
.id = VENDOR_ID_ISSI,
.page_size_shift = 8, // 256 byte page size
.sector_size_kib_shift = 2, // 4 Kbyte sector size
.match_id_mask[0] = 0xffff,
.ids = flash_table,
.nr_part_ids = ARRAY_SIZE(flash_table),
.desc = &spi_flash_pp_0x20_sector_desc,
.prot_ops = NULL,
};

View File

@@ -101,7 +101,7 @@ unsigned int spi_crop_chunk(const struct spi_slave *slave, unsigned int cmd_len,
/* Subtract command length from usable buffer size. If
deduct_opcode_len is set, only subtract the number command bytes
after the opcode. If the adjusted cmd_len is larger than ctrlr_max
return 0 to inidicate an error. */
return 0 to indicate an error. */
if (deduct_cmd_len) {
if (ctrlr_max >= cmd_len) {
ctrlr_max -= cmd_len;

View File

@@ -397,6 +397,9 @@ static const struct spi_flash_vendor_info *spi_flash_vendors[] = {
#if CONFIG(SPI_FLASH_WINBOND)
&spi_flash_winbond_vi,
#endif
#if CONFIG(SPI_FLASH_ISSI)
&spi_flash_issi_vi,
#endif
};
#define IDCODE_LEN 5

View File

@@ -112,7 +112,7 @@ extern const struct spi_flash_vendor_info spi_flash_atmel_vi;
extern const struct spi_flash_vendor_info spi_flash_eon_vi;
extern const struct spi_flash_vendor_info spi_flash_gigadevice_vi;
extern const struct spi_flash_vendor_info spi_flash_macronix_vi;
/* Probing order matters between the spansion sequence. */
/* Probing order matters between the Spansion sequence. */
extern const struct spi_flash_vendor_info spi_flash_spansion_ext1_vi;
extern const struct spi_flash_vendor_info spi_flash_spansion_ext2_vi;
extern const struct spi_flash_vendor_info spi_flash_spansion_vi;
@@ -123,6 +123,7 @@ extern const struct spi_flash_vendor_info spi_flash_stmicro2_vi;
extern const struct spi_flash_vendor_info spi_flash_stmicro3_vi;
extern const struct spi_flash_vendor_info spi_flash_stmicro4_vi;
extern const struct spi_flash_vendor_info spi_flash_winbond_vi;
extern const struct spi_flash_vendor_info spi_flash_issi_vi;
/* Page Programming Command Set with 0x20 Sector Erase command. */
extern const struct spi_flash_ops_descriptor spi_flash_pp_0x20_sector_desc;

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