mb/system76/rpl: darp9: Add SSD RTD3 configs

Some drives block the CPU from reaching C10 on suspend without the RTD3
config.

Fixes suspend with the following drives:

- Kingston KC3000 (SKC3000D/4096G)
- Kingston HyperX (SHPM2280P2H/240G)
- Solidigm P44 Pro (SSDPFKKW010X7)

The following drives continue to work:

- Samsung 970 Evo (MZVLB250HAHQ)
- WD Black SN770 (WDS250G3X0E)
- WD Green SN350 (WDS240G2G0C-00AJM0)
- WD Blue SN570 (WDS100T3B0C)

Change-Id: I205d78377fa2b0db8d37542cdb94ba86ded1d66e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Tested-by: Levi Portenier <levi@system76.com>

.clang-format

@@ -1,228 +1,21 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# clang-format configuration file. Intended for clang-format >= 16.
-#
-# For more information, see:
-#
-#   https://clang.llvm.org/docs/ClangFormat.html
-#   https://clang.llvm.org/docs/ClangFormatStyleOptions.html
-#   https://clang-format-configurator.site/
-#
-
----
-Language:        Cpp
-AccessModifierOffset: -4
-AlignAfterOpenBracket: Align
-AlignArrayOfStructures: Left
-AlignConsecutiveAssignments:
-  Enabled:         false
-  AcrossEmptyLines: false
-  AcrossComments:  true
-  AlignCompound:   false
-  PadOperators:    true
-AlignConsecutiveBitFields:
-  Enabled:         true
-  AcrossEmptyLines: false
-  AcrossComments:  false
-  AlignCompound:   false
-  PadOperators:    true
-AlignConsecutiveDeclarations:
-  Enabled:         false
-  AcrossEmptyLines: false
-  AcrossComments:  false
-  AlignCompound:   false
-  PadOperators:    true
-AlignConsecutiveMacros:
-  Enabled:         true
-  AcrossEmptyLines: false
-  AcrossComments:  false
-  AlignCompound:   false
-  PadOperators:    true
-AlignEscapedNewlines: Left
-AlignOperands:   Align
-AlignTrailingComments:
-  Kind:            Always
-  OverEmptyLines:  0
-AllowAllArgumentsOnNextLine: true
-AllowAllParametersOfDeclarationOnNextLine: false
-AllowShortBlocksOnASingleLine: Never
-AllowShortCaseLabelsOnASingleLine: false
-AllowShortEnumsOnASingleLine: true
-AllowShortFunctionsOnASingleLine: None
-AllowShortIfStatementsOnASingleLine: Never
-AllowShortLambdasOnASingleLine: All
-AllowShortLoopsOnASingleLine: false
-AlwaysBreakAfterDefinitionReturnType: None
-AlwaysBreakAfterReturnType: None
-AlwaysBreakBeforeMultilineStrings: false
-AlwaysBreakTemplateDeclarations: MultiLine
-
-# git grep '^#define [^[:space:]]*__.*[^[:space:]]*__attribute__' | grep -v "vendorcode\|payloads\|util" | sed "s|.*:||;s|^#define \([^[:space:]]*__[^([:space:]]*\).*$|  - '\1'|" | LC_ALL=C sort -u
-AttributeMacros:
-  - '__aligned'
-  - '__always_inline'
-  - '__always_unused'
-  - '__cpu_driver'
-  - '__fallthrough'
-  - '__maybe_unused'
-  - '__must_check'
-  - '__noreturn'
-  - '__packed'
-  - '__pci_driver'
-  - '__printf'
-  - '__weak'
-BinPackArguments: true
-BinPackParameters: true
-BitFieldColonSpacing: Both
-BraceWrapping:
-  AfterCaseLabel:  false
-  AfterClass:      false
-  AfterControlStatement: Never
-  AfterEnum:       false
-  AfterExternBlock: false
-  AfterFunction:   true
-  AfterNamespace:  true
-  AfterObjCDeclaration: false
-  AfterStruct:     false
-  AfterUnion:      false
-  BeforeCatch:     false
-  BeforeElse:      false
-  BeforeLambdaBody: false
-  BeforeWhile:     false
-  IndentBraces:    false
-  SplitEmptyFunction: true
-  SplitEmptyRecord: true
-  SplitEmptyNamespace: true
-BreakAfterAttributes: Never
-BreakAfterJavaFieldAnnotations: false
-BreakArrays:     false
-BreakBeforeBinaryOperators: None
-BreakBeforeConceptDeclarations: Always
-BreakBeforeBraces: Custom
-BreakBeforeInlineASMColon: OnlyMultiline
-BreakBeforeTernaryOperators: false
-BreakConstructorInitializers: AfterColon
-BreakInheritanceList: AfterColon
-BreakStringLiterals: false
-ColumnLimit:     96
-CommentPragmas:  '^ IWYU pragma:'
-CompactNamespaces: false
-ConstructorInitializerIndentWidth: 8
-ContinuationIndentWidth: 8
-Cpp11BracedListStyle: true
-DerivePointerAlignment: false
-DisableFormat:   false
-EmptyLineAfterAccessModifier: Never
-EmptyLineBeforeAccessModifier: LogicalBlock
-ExperimentalAutoDetectBinPacking: false
-FixNamespaceComments: false
-
-# git grep '^#define [^[:space:]]*for_each[^[:space:]]*(' | grep -v "vendorcode\|payloads\|util" | sed "s|.*:||;s|^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$|  - '\1'|" | LC_ALL=C sort -u
-ForEachMacros:
-  - 'list_for_each'
-
-# git grep -i '^#define \+if[^[:space:]]*(' | grep -v "vendorcode\|payloads\|util" | sed "s|.*:||;s|^#define \([^[:space:]]*if[^[:space:]]*\)(.*$|  - '\1'|I" | grep -v IFIX | LC_ALL=C sort -u
-IfMacros:
-  - 'IF_CHANNEL_POPULATED'
-  - 'IF_DIMM_POPULATED'
-  - 'IF_RANK_POPULATED'
-  - 'IfBit0'
-IncludeBlocks:   Preserve
-IncludeIsMainSourceRegex: ''
-IndentAccessModifiers: false
-IndentCaseBlocks: false
-IndentCaseLabels: false
-IndentExternBlock: AfterExternBlock
-IndentGotoLabels: false
-IndentPPDirectives: None
-IndentRequiresClause: true
-IndentWidth:     8
-IndentWrappedFunctionNames: false
-InsertBraces:    false
-InsertNewlineAtEOF: true
-InsertTrailingCommas: None
-IntegerLiteralSeparator:
-  Binary:          0
-  BinaryMinDigits: 0
-  Decimal:         0
-  DecimalMinDigits: 0
-  Hex:             0
-  HexMinDigits:    0
-JavaScriptQuotes: Leave
-JavaScriptWrapImports: true
-KeepEmptyLinesAtTheStartOfBlocks: false
-LambdaBodyIndentation: Signature
-LineEnding:      LF
-MacroBlockBegin: ''
-MacroBlockEnd:   ''
-MaxEmptyLinesToKeep: 1
-NamespaceIndentation: None
-ObjCBinPackProtocolList: Auto
-ObjCBlockIndentWidth: 8
-ObjCBreakBeforeNestedBlockParam: true
-ObjCSpaceAfterProperty: true
-ObjCSpaceBeforeProtocolList: true
-PackConstructorInitializers: BinPack
-PenaltyBreakAssignment: 10
-PenaltyBreakBeforeFirstCallParameter: 30
-PenaltyBreakComment: 10
-PenaltyBreakFirstLessLess: 0
-PenaltyBreakOpenParenthesis: 0
-PenaltyBreakString: 10
-PenaltyBreakTemplateDeclaration: 10
-PenaltyExcessCharacter: 100
-PenaltyIndentedWhitespace: 0
-PenaltyReturnTypeOnItsOwnLine: 60
-PointerAlignment: Right
-PPIndentWidth:   -1
-QualifierAlignment: Left
-ReferenceAlignment: Pointer
-ReflowComments:  false
-RemoveBracesLLVM: false
-RemoveSemicolon: false
-RequiresClausePosition: OwnLine
-RequiresExpressionIndentation: OuterScope
-SeparateDefinitionBlocks: Leave
-ShortNamespaceLines: 1
-SortIncludes:    Never
-SortJavaStaticImport: Before
-SortUsingDeclarations: Never
-SpaceAfterCStyleCast: false
-SpaceAfterLogicalNot: false
-SpaceAfterTemplateKeyword: true
-SpaceAroundPointerQualifiers: Default
-SpaceBeforeAssignmentOperators: true
-SpaceBeforeCaseColon: false
-SpaceBeforeCpp11BracedList: false
-SpaceBeforeCtorInitializerColon: true
-SpaceBeforeInheritanceColon: true
-SpaceBeforeParens: ControlStatementsExceptControlMacros
-SpaceBeforeParensOptions:
-  AfterControlStatements: true
-  AfterForeachMacros: false
-  AfterFunctionDefinitionName: false
-  AfterFunctionDeclarationName: false
-  AfterIfMacros:   false
-  AfterOverloadedOperator: false
-  AfterRequiresInClause: false
-  AfterRequiresInExpression: false
-  BeforeNonEmptyParentheses: false
-SpaceBeforeRangeBasedForLoopColon: true
-SpaceBeforeSquareBrackets: false
-SpaceInEmptyBlock: false
-SpaceInEmptyParentheses: false
-SpacesBeforeTrailingComments: 1
-SpacesInAngles:  Never
-SpacesInConditionalStatement: false
-SpacesInContainerLiterals: false
-SpacesInCStyleCastParentheses: false
-SpacesInLineCommentPrefix:
-  Minimum:         1
-  Maximum:         1
-SpacesInParentheses: false
-SpacesInSquareBrackets: false
-Standard:        c++17
-TabWidth:        8
-UseTab:          ForContinuationAndIndentation
-...
-
+BasedOnStyle:					LLVM
+Language:					Cpp
+IndentWidth:					8
+UseTab:						Always
+BreakBeforeBraces:				Linux
+AllowShortIfStatementsOnASingleLine:		false
+IndentCaseLabels:				false
+SortIncludes:					false
+ContinuationIndentWidth:			8
+ColumnLimit:					96
+AlwaysBreakBeforeMultilineStrings:		true
+AllowShortLoopsOnASingleLine:			false
+AllowShortFunctionsOnASingleLine:		false
+AlignEscapedNewlinesLeft:			false
+AlignTrailingComments:				true
+AllowAllParametersOfDeclarationOnNextLine:	false
+AlignAfterOpenBracket:				true
+SpaceAfterCStyleCast:				false
+MaxEmptyLinesToKeep:				2
+BreakBeforeBinaryOperators:			NonAssignment
+BreakStringLiterals:				false

.editorconfig

@@ -9,7 +9,3 @@ charset = utf-8
 insert_final_newline = true
 end_of_line = lf
 trim_trailing_whitespace = true
-
-[*.sh]
-indent_style = space
-indent_size = 2

.gitmodules

@@ -1,70 +1,70 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe
 [submodule "util/goswid"]
 	path = util/goswid
-	url = ../goswid
+	url = https://review.coreboot.org/goswid.git
 	branch = trunk
 [submodule "src/vendorcode/amd/opensil/genoa_poc/opensil"]
 	path = src/vendorcode/amd/opensil/genoa_poc/opensil
-	url = ../opensil_genoa_poc.git
+	url = https://review.coreboot.org/opensil_genoa_poc.git

Documentation/getting_started/kconfig.md

@@ -69,6 +69,9 @@ These variables are typically set in the makefiles or on the make command line.
 These variables were added to Kconfig specifically for coreboot and are not
 included in the Linux version.
 
+- KCONFIG_STRICT=value. Define to enable warnings as errors.   This is enabled
+  in coreboot, and should not be changed.
+
 - KCONFIG_NEGATIVES=value. Define to show negative values in the autoconf.h file
   (build/config.h). This is enabled in coreboot, and should not be changed.
 
@@ -99,9 +102,6 @@ included in the Linux version.
 - KCONFIG_SPLITCONFIG=”directory name for individual SYMBOL.h files”.
   coreboot sets this to $(obj)/config.
 
-- KCONFIG_WERROR=value. Define to enable warnings as errors. This is enabled
-  in coreboot, and should not be changed.
-
 #### Used only for ‘make menuconfig’
 - MENUCONFIG_MODE=single_menu.  Set to "single_menu" to enable.  All other
   values disable the option.  This makes submenus appear below the menu option
@@ -1160,6 +1160,10 @@ saved .config file. As always, a 'select' statement overrides any specified
 - coreboot has added the glob operator '*' for the 'source' keyword.
 - coreboot’s Kconfig always defines variables except for strings. In other
   Kconfig implementations, bools set to false/0/no are not defined.
+- coreboot’s version of Kconfig adds the KCONFIG_STRICT environment variable to
+  error out if there are any issues in the Kconfig files.  In the Linux kernel,
+  Kconfig will generate a warning, but will still output an updated .config or
+  config.h file.
 
 
 ## Kconfig Editor Highlighting

Documentation/mainboard/lenovo/vboot.md

@@ -9,7 +9,7 @@ updates using an A/B partitioning scheme once enabled.
 ## Enabling vboot
 You can enable [vboot] in Kconfig's *Security* section. Besides a verified
 boot you can also enable a measured boot by setting
-`CONFIG_TPM_MEASURED_BOOT`. Both options need a working TPM, which is
+`CONFIG_VBOOT_MEASURED_BOOT`. Both options need a working TPM, which is
 present on all recent Lenovo devices.
 
 ## Updating and recovery

Documentation/releases/coreboot-24.02-relnotes.md

@@ -1,99 +0,0 @@
-Upcoming release - coreboot 24.02
-========================================================================
-
-The 24.02 release is scheduled for Mid February, 2024
-
-
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-* Note that all changes before the release are done are marked upcoming.
-  A final version of the notes are done after the release.
-
-### Release number format update
-
-The previous release was the last to use the incrementing 4.xx release
-name scheme. For this and future releases, coreboot has switched to a
-Year.Month.Sub-version naming scheme. As such, the next release,
-scheduled for May of 2024 will be numbered 24.05, with the sub-version
-of 00 implied. If we need to do a fix or incremental release, we’ll
-append the values .01, .02 and so on to the initial release value.
-
-
-Significant or interesting changes
-----------------------------------
-
-* Add changes that need a full description here
-
-* This section should have full descriptions and can or should have
-  a link to the referenced commits.
-
-
-
-Additional coreboot changes
----------------------------
-
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Changes that only need a line or two of description go here.
-
-
-Changes to external resources
------------------------------
-
-### Toolchain updates
-
-
-### Git submodule pointers
-
-
-### External payloads
-
-
-Platform Updates
-----------------
-
-### Added mainboards:
-* To be filled in immediately before the release by the release team
-
-
-### Removed Mainboards
-* To be filled in immediately before the release by the release team
-
-
-### Updated SoCs
-* To be filled in immediately before the release by the release team
-
-
-Plans to move platform support to a branch
-------------------------------------------
-* To be filled in immediately before the release by the release team
-
-
-Statistics from the 4.22 to the 24.02 release
---------------------------------------------
-* To be filled in immediately before the release by the release team
-
-
-
-Significant Known and Open Issues
----------------------------------
-
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-* To be filled in immediately before the release by the release team
-
-
-
-coreboot Links and Contact Information
---------------------------------------
-
-* Main Web site: https://www.coreboot.org
-* Downloads: https://coreboot.org/downloads.html
-* Source control: https://review.coreboot.org
-* Documentation: https://doc.coreboot.org
-* Issue tracker: https://ticket.coreboot.org/projects/coreboot
-* Donations: https://coreboot.org/donate.html

Documentation/releases/coreboot-4.22-relnotes.md

@@ -1,7 +1,7 @@
-coreboot 4.22 & 4.22.01 releases
+Upcoming release - coreboot 4.22
 ========================================================================
 
-The next release is planned for the 19th of February, 2024
+The next release is planned for mid-February, 2024
 
 These notes cover the latest updates and improvements to coreboot over
 the past three months. A big thank you to the returning contributors as
@@ -11,17 +11,6 @@ releases, this one reflects a commitment to open source innovation,
 security enhancements, and expanding hardware support.
 
 
-### 4.22.01 release
-
-The week between tagging a release and announcing it publicly is used
-to test the tagged version and make sure everything is working as we
-expect. This is done instead of freezing the tree and doing release
-candidates before the release.
-
-For the 4.22 release cycle we found an uninitialized variable error on
-the sandybridge/ivybridge platforms and rolled that into the 4.22.01
-release package.
-
 ### coreboot version naming update
 
 This release is the last release to use the incrementing 4.xx release
@@ -29,14 +18,14 @@ name scheme. For future releases, coreboot is switching to a
 Year.Month.Sub-version naming scheme. As such, the next release,
 scheduled for February of 2024 will be numbered 24.02, with the
 sub-version of 00 implied. If we need to do a fix or future release of
-the 24.02 release, we'll append the values .01, .02 and so on to the
+the 24.02 release, we’ll append the values .01, .02 and so on to the
 initial release value.
 
 
 ### coreboot default branch update
 
 Immediately after the 4.21 release, the coreboot project changed the
-default git branch from 'master' to 'main'. For the first couple of
+default git branch from ‘master’ to ‘main’. For the first couple of
 months after the change, The master branch was synced with the main
 branch several times a day, allowing people time to update any scripts.
 As of 2023-11-01, the sync rate has slowed to once a week. This will
@@ -166,7 +155,7 @@ GPU drivers will fail to load with a code 43 error in Device Manager.
 Additional coreboot changes
 ---------------------------
 
-* Move all 'select' statements from Kconfig.name files to Kconfig
+* Move all ‘select’ statements from Kconfig.name files to Kconfig
 * acpigen now generates variable-length PkgLength fields instead of a
   fixed 3-byte size to improve compatibility and to bring it in line
   with IASL
@@ -246,15 +235,15 @@ Platform Updates
 Statistics from the 4.21 to the 4.22 release
 --------------------------------------------
 
-* Total Commits: 977
-* Average Commits per day: 10.98
-* Total lines added: 62993
-* Average lines added per commit: 64.48
-* Number of patches adding more than 100 lines: 60
-* Average lines added per small commit: 37.55
-* Total lines removed: 30042
-* Average lines removed per commit: 30.75
-* Total difference between added and removed: 32951
+* Total Commits: 885
+* Average Commits per day: 10.72
+* Total lines added: 58276
+* Average lines added per commit: 65.85
+* Number of patches adding more than 100 lines: 54
+* Average lines added per small commit: 37.77
+* Total lines removed: 27790
+* Average lines removed per commit: 31.40
+* Total difference between added and removed: 30486
 * Total authors: 135
 * New authors: 14
 

Documentation/releases/index.md

@@ -3,7 +3,7 @@
 ## Upcoming release
 
 Please add to the release notes as changes are added:
-* [24.02 - February 2024](coreboot-24.02-relnotes.md)
+* [4.22 - November 2023](coreboot-4.22-relnotes.md)
 
 The [checklist] contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -15,7 +15,6 @@ important is taken care of.
 
 ## Previous releases
 
-* [4.22 - November 2023](coreboot-4.22-relnotes.md)
 * [4.21   - August 2023](coreboot-4.21-relnotes.md)
 * [4.20.1 - May 2023](coreboot-4.20.1-relnotes.md)
 * [4.19   - January 2023](coreboot-4.19-relnotes.md)

Documentation/security/vboot/measured_boot.md

@@ -68,7 +68,7 @@ specific IBB measurements without hard-coding them.
 
 #### Runtime Data
 * CBFS data which changes by external input dynamically. Never stays the same.
-* It is identified by TPM_MEASURED_BOOT_RUNTIME_DATA kconfig option and
+* It is identified by VBOOT_MEASURED_BOOT_RUNTIME_DATA kconfig option and
   measured into a different PCR (PCR_RUNTIME_DATA kconfig option, 3 by default)
   in order to avoid PCR pre-calculation issues.
 

MAINTAINERS

@@ -349,7 +349,7 @@ GOOGLE REX MAINBOARDS
 M:	Subrata Banik <subratabanik@google.com>
 M:	Tarun Tuli <tstuli@gmail.com>
 M:	Kapil Porwal <kapilporwal@google.com>
-M:	Jakub Czapiga <czapiga@google.com>
+M:	Jakub Czapiga <jacz@semihalf.com>
 M:	Eran Mitrani <mitrani@google.com>
 M:	Dinesh Gehlot <digehlot@google.com>
 S:	Maintained
@@ -886,7 +886,7 @@ INTEL METEORLAKE SOC
 M:	Subrata Banik <subratabanik@google.com>
 M:	Tarun Tuli <tstuli@gmail.com>
 M:	Kapil Porwal <kapilporwal@google.com>
-M:	Jakub Czapiga <czapiga@google.com>
+M:	Jakub Czapiga <jacz@semihalf.com>
 M:	Eran Mitrani <mitrani@google.com>
 M:	Dinesh Gehlot <digehlot@google.com>
 S:	Maintained
@@ -1180,7 +1180,7 @@ S:	Maintained
 F:	src/drivers/i2c/tas5825m/
 
 TESTS
-M:	Jakub Czapiga <czapiga@google.com>
+M:	Jakub Czapiga <jacz@semihalf.com>
 S:	Maintained
 F:	tests/
 F:	payloads/libpayload/tests/

Makefile

@@ -23,27 +23,20 @@ COREBOOT_EXPORTS += top src srck obj objutil objk
 DOTCONFIG ?= $(top)/.config
 KCONFIG_CONFIG = $(DOTCONFIG)
 KCONFIG_AUTOADS := $(obj)/cb-config.ads
-KCONFIG_RUSTCCFG := $(obj)/cb-config.rustcfg
 KCONFIG_AUTOHEADER := $(obj)/config.h
 KCONFIG_AUTOCONFIG := $(obj)/auto.conf
 KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd
 KCONFIG_SPLITCONFIG := $(obj)/config/
 KCONFIG_TRISTATE := $(obj)/tristate.conf
 KCONFIG_NEGATIVES := 1
-KCONFIG_WERROR := 1
-KCONFIG_WARN_UNKNOWN_SYMBOLS := 1
+KCONFIG_STRICT := 1
 KCONFIG_PACKAGE := CB.Config
 KCONFIG_MAKEFILE_REAL ?= $(objk)/Makefile.real
 
 COREBOOT_EXPORTS += KCONFIG_CONFIG KCONFIG_AUTOHEADER KCONFIG_AUTOCONFIG
 COREBOOT_EXPORTS += KCONFIG_DEPENDENCIES KCONFIG_SPLITCONFIG KCONFIG_TRISTATE
-COREBOOT_EXPORTS += KCONFIG_NEGATIVES
-ifeq ($(filter %config,$(MAKECMDGOALS)),)
-COREBOOT_EXPORTS += KCONFIG_WERROR
-endif
-COREBOOT_EXPORTS += KCONFIG_WARN_UNKNOWN_SYMBOLS
+COREBOOT_EXPORTS += KCONFIG_NEGATIVES KCONFIG_STRICT
 COREBOOT_EXPORTS += KCONFIG_AUTOADS KCONFIG_PACKAGE
-COREBOOT_EXPORTS += KCONFIG_RUSTCCFG
 
 # Make does not offer a recursive wildcard function, so here's one:
 rwildcard=$(wildcard $1$2) $(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2))

Makefile.inc

@@ -59,36 +59,22 @@ COREBOOT_EXPORTS += CCACHE_EXTRAFILES
 
 #######################################################################
 # root rule to resolve if in build mode (ie. configuration exists)
-real-target: $(obj)/config.h coreboot files_added show_coreboot show_notices
+real-target: $(obj)/config.h coreboot files_added
 coreboot: $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool $(obj)/ifwitool $(obj)/cse_fpt $(obj)/cse_serger
 
-# This target can be used to run scripts or additional targets
-# after the build completes by creating a target named 'build_complete::'
-.PHONY: build_complete
-build_complete:: | coreboot
-
-# This target can be used to run rules after all files were added to CBFS,
-# for example to process FMAP regions or the entire image.
-.PHONY: files_added
-files_added:: | build_complete
-
-# This target should come just before the show_notices target.  If there
-# are no notices, the build should finish with the text of what was just
-# built.
-.PHONY: show_coreboot
-show_coreboot: | files_added
-	$(CBFSTOOL) $(obj)/coreboot.rom print -r $(subst $(spc),$(comma),$(all-regions))
+# This target can be used in site local to run scripts or additional
+# targets after the build completes by creating a Makefile.inc in the
+# site-local directory with a target named 'build_complete::'
+build_complete:: coreboot
 	printf "\nBuilt %s (%s)\n" $(MAINBOARDDIR) $(CONFIG_MAINBOARD_PART_NUMBER)
 	if [ -f "$(CCACHE_STATSLOG)" ]; then \
 		printf "\nccache statistics\n"; \
 		$(CCACHE) --show-log-stats -v; \
 	fi
 
-# This is intended to run at the *very end* of the build to show warnings
-# notices and the like.  If another target needs to be added, add it
-# BEFORE this target.
-.PHONY: show_notices
-show_notices:: | show_coreboot
+# This target can be used to run rules after all files were added to CBFS,
+# for example to process FMAP regions or the entire image.
+files_added:: build_complete
 
 #######################################################################
 # our phony targets
@@ -1255,6 +1241,7 @@ endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	@printf "    CBFSLAYOUT  $(subst $(obj)/,,$(@))\n\n"
 	$(CBFSTOOL) $@ layout
 	@printf "    CBFSPRINT  $(subst $(obj)/,,$(@))\n\n"
+	$(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions))
 ifeq ($(CONFIG_CBFS_VERIFICATION),y)
 	line=$$($(CBFSTOOL) $@ print -kv 2>/dev/null | grep -F '[CBFS VERIFICATION (COREBOOT)]') ;\
 	if ! printf "$$line" | grep -q 'fully valid'; then \

README.md

@@ -140,10 +140,9 @@ These uncopyrightable files include:
   These may be required to exist as part of the build process but are
   not needed for the particular project.
 - Configuration files either in binary or text form. Examples would be
-  files such as .vbt files describing graphics configuration, .apcb
-  files containing configuration parameters for AMD firmware binaries,
-  and spd files as binary .spd or text \*spd\*.hex representing memory
-  chip configuration.
+  files such as .vbt files describing graphics configuration, spd files
+  as binary .spd or text \*spd\*.hex representing memory chip
+  configuration.
 - Machine-generated files containing version numbers, dates, hash
   values or other "non-creative" content.
 

configs/config.emulation_qemu_x86_i440fx_debug

@@ -8,3 +8,4 @@ CONFIG_DEBUG_PIRQ=y
 CONFIG_DEBUG_MALLOC=y
 CONFIG_DEBUG_BOOT_STATE=y
 CONFIG_DEBUG_ADA_CODE=y
+CONFIG_CPU_QEMU_X86_PARALLEL_MP=y

configs/config.emulation_qemu_x86_q35_smm_tseg

@@ -1,3 +1,5 @@
 CONFIG_VENDOR_EMULATION=y
 CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y
+CONFIG_CPU_QEMU_X86_PARALLEL_MP=y
 CONFIG_CPU_QEMU_X86_TSEG_SMM=y
+CONFIG_CPU_QEMU_X86_SMMLOADERV2=y

configs/config.google_meep_cros

@@ -10,6 +10,7 @@ CONFIG_ANY_TOOLCHAIN=y
 # ChromeOS
 CONFIG_CHROMEOS=y
 CONFIG_HAS_RECOVERY_MRC_CACHE=y
+CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN=y
 
 # Event Logging
 CONFIG_CMOS_POST=y
@@ -33,5 +34,5 @@ CONFIG_CONSOLE_SERIAL=y
 CONFIG_CONSOLE_SERIAL_115200=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 # GLK specific setting to auto select all the correct settings.
-CONFIG_INTEL_LPSS_UART_FOR_CONSOLE=y
+CONFIG_UART_DEBUG=y
 CONFIG_NO_BOOTBLOCK_CONSOLE=y

configs/config.google_octopus_spi_flash_console

@@ -1,4 +1,4 @@
 CONFIG_VENDOR_GOOGLE=y
 CONFIG_BOARD_GOOGLE_OCTOPUS=y
 CONFIG_CONSOLE_SPI_FLASH=y
-# CONFIG_TPM_MEASURED_BOOT is not set
+# CONFIG_VBOOT_MEASURED_BOOT is not set

configs/config.intel_coffeelake_rvp11.fsp_car

@@ -0,0 +1,7 @@
+CONFIG_USE_BLOBS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_INTEL_GMA_VBT_FILE="3rdparty/fsp/CoffeeLakeFspBinPkg/SampleCode/Vbt/Vbt.bin"
+CONFIG_BOARD_INTEL_COFFEELAKE_RVP11=y
+CONFIG_USE_CANNONLAKE_FSP_CAR=y
+CONFIG_RUN_FSP_GOP=y
+CONFIG_PAYLOAD_NONE=y

configs/config.pcengines_apu1

@@ -6,5 +6,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 CONFIG_PXE_ROM_ID="10ec,8168"
-# CONFIG_IPXE_SERIAL_CONSOLE is not set
+# CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

configs/config.pcengines_apu2

@@ -8,5 +8,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 CONFIG_PXE_ROM_ID="8086,157b"
-# CONFIG_IPXE_SERIAL_CONSOLE is not set
+# CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

configs/config.pcengines_apu3

@@ -8,5 +8,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 CONFIG_PXE_ROM_ID="8086,1539"
-# CONFIG_IPXE_SERIAL_CONSOLE is not set
+# CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

configs/config.pcengines_apu4

@@ -8,5 +8,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 CONFIG_PXE_ROM_ID="8086,1539"
-# CONFIG_IPXE_SERIAL_CONSOLE is not set
+# CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

configs/config.pcengines_apu5

@@ -8,5 +8,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 CONFIG_PXE_ROM_ID="8086,1539"
-# CONFIG_IPXE_SERIAL_CONSOLE is not set
+# CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

payloads/Makefile.inc

@@ -50,7 +50,7 @@ print-repo-info-payloads:
 	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
 
 ifeq ($(CONFIG_PAYLOAD_NONE),y)
-show_notices:: warn_no_payload
+files_added:: warn_no_payload
 endif
 
 warn_no_payload:

payloads/libpayload/arch/arm/head.S

@@ -56,4 +56,4 @@ ENDPROC(_entry)
 1:
 .word	cb_header_ptr
 2:
-.word	_estack
+.word	_stack

payloads/libpayload/arch/arm/libpayload.ldscript

@@ -40,35 +40,29 @@ SECTIONS
 	_start = .;
 
 	.text : {
-		_text = .;
 		*(.text._entry)
 		*(.text)
 		*(.text.*)
-		_etext = .;
 	}
 
 	.rodata : {
-		_rodata = .;
 		*(.rodata)
 		*(.rodata.*)
-		_erodata = .;
 	}
 
 	.data : {
-		_data = .;
 		*(.data)
 		*(.data.*)
-		_edata = .;
 	}
 
+	_edata = .;
+
 	.bss : {
-		_bss = .;
 		*(.sbss)
 		*(.sbss.*)
 		*(.bss)
 		*(.bss.*)
 		*(COMMON)
-		_ebss = .;
 
 		/* Stack and heap */
 
@@ -78,10 +72,10 @@ SECTIONS
 		. = ALIGN(16);
 		_eheap = .;
 
-		_stack = .;
+		_estack = .;
 		. += CONFIG_LP_STACK_SIZE;
 		. = ALIGN(16);
-		_estack = .;
+		_stack = .;
 	}
 
 	_end = .;

payloads/libpayload/arch/arm64/head.S

@@ -55,4 +55,4 @@ ENDPROC(_entry)
 1:
 .quad	cb_header_ptr
 2:
-.quad	_estack
+.quad	_stack

payloads/libpayload/arch/arm64/libpayload.ldscript

@@ -40,37 +40,29 @@ SECTIONS
 	_start = .;
 
 	.text : {
-		_text = .;
 		*(.text._entry)
 		*(.text)
 		*(.text.*)
-		_etext = .;
 	}
 
 	.rodata : {
-		_rodata = .;
 		*(.rodata)
 		*(.rodata.*)
-		_erodata = .;
 	}
 
 	.data : {
-		_data = .;
 		*(.data)
 		*(.data.*)
-		_edata = .;
 	}
 
-	.bss : {
-		*(.ttb_buffer)
+	_edata = .;
 
-		_bss = .;
+	.bss : {
 		*(.sbss)
 		*(.sbss.*)
 		*(.bss)
 		*(.bss.*)
 		*(COMMON)
-		_ebss = .;
 
 		/* Stack and heap */
 
@@ -80,10 +72,10 @@ SECTIONS
 		. = ALIGN(16);
 		_eheap = .;
 
-		_stack = .;
+		_estack = .;
 		. += CONFIG_LP_STACK_SIZE;
 		. = ALIGN(16);
-		_estack = .;
+		_stack = .;
 	}
 
 	_end = .;

payloads/libpayload/arch/arm64/mmu.c

@@ -41,8 +41,7 @@ static unsigned int max_tables;
 static uint64_t *xlat_addr;
 
 static int free_idx;
-static uint8_t ttb_buffer[TTB_DEFAULT_SIZE] __aligned(GRANULE_SIZE)
-	__attribute__((__section__(".ttb_buffer")));
+static uint8_t ttb_buffer[TTB_DEFAULT_SIZE] __attribute__((aligned(GRANULE_SIZE)));
 
 static const char * const tag_to_string[] = {
 	[TYPE_NORMAL_MEM] = "normal",
@@ -575,6 +574,8 @@ static struct mmu_memrange *_mmu_add_fb_range(
 
 	prop.type = TYPE_DMA_MEM;
 
+	/* make sure to allocate a size of multiple of GRANULE_SIZE */
+	size = ALIGN_UP(size, GRANULE_SIZE);
 	prop.size = size;
 	prop.lim_excl = MIN_64_BIT_ADDR;
 	prop.align = MB_SIZE;
@@ -632,9 +633,6 @@ static void mmu_add_fb_range(struct mmu_ranges *mmu_ranges)
 	if (!fb_size)
 		return;
 
-	/* make sure to allocate a size of multiple of GRANULE_SIZE */
-	fb_size = ALIGN_UP(fb_size, GRANULE_SIZE);
-
 	/* framebuffer address has been set already, so just add it as DMA */
 	if (framebuffer->physical_address) {
 		if (mmu_add_memrange(mmu_ranges,

payloads/libpayload/arch/x86/head.S

@@ -73,7 +73,7 @@ _init:
 
 	/* Store current stack pointer and set up new stack. */
 	movl %esp, %eax
-	movl $_estack, %esp
+	movl $_stack, %esp
 	pushl %eax
 
 	/* Enable special x86 functions if present. */

payloads/libpayload/arch/x86/libpayload.ldscript

@@ -39,35 +39,29 @@ SECTIONS
 	_start = .;
 
 	.text : {
-		_text = .;
 		*(.text._entry)
 		*(.text)
 		*(.text.*)
-		_etext = .;
 	}
 
 	.rodata : {
-		_rodata = .;
 		*(.rodata)
 		*(.rodata.*)
-		_erodata = .;
 	}
 
 	.data : {
-		_data = .;
 		*(.data)
 		*(.data.*)
-		_edata = .;
 	}
 
+	_edata = .;
+
 	.bss : {
-		_bss = .;
 		*(.sbss)
 		*(.sbss.*)
 		*(.bss)
 		*(.bss.*)
 		*(COMMON)
-		_ebss = .;
 
 		/* Stack and heap */
 
@@ -77,10 +71,10 @@ SECTIONS
 		. = ALIGN(16);
 		_eheap = .;
 
-		_stack = .;
+		_estack = .;
 		. += CONFIG_LP_STACK_SIZE;
 		. = ALIGN(16);
-		_estack = .;
+		_stack = .;
 	}
 
 	_end = .;

payloads/libpayload/configs/config.unit-tests

@@ -1,2 +1,2 @@
 CONFIG_LP_ARCH_MOCK=y
-CONFIG_LP_ARCH_MOCK_BIG_ENDIAN=n
+CONFIG_LP_ARCH_BIG_ENDIAN=n

payloads/libpayload/include/stdlib.h

@@ -137,7 +137,6 @@ void print_malloc_map(void);
 void init_dma_memory(void *start, u32 size);
 int dma_initialized(void);
 int dma_coherent(const void *ptr);
-void dma_allocator_range(void **start_out, size_t *size_out);
 
 static inline void *xmalloc_work(size_t size, const char *file,
 				 const char *func, int line)

payloads/libpayload/libc/malloc.c

@@ -123,18 +123,6 @@ int dma_coherent(const void *ptr)
 	return !dma_initialized() || (dma->start <= ptr && dma->end > ptr);
 }
 
-/* Get the range of memory that can be allocated by the dma allocator. */
-void dma_allocator_range(void **start_out, size_t *size_out)
-{
-	if (dma_initialized()) {
-		*start_out = dma->start;
-		*size_out = dma->end - dma->start;
-	} else {
-		*start_out = NULL;
-		*size_out = 0;
-	}
-}
-
 /* Find free block of size >= len */
 static hdrtype_t volatile *find_free_block(int len, struct memory_type *type)
 {

src/acpi/Kconfig

@@ -86,36 +86,8 @@ config ACPI_GTDT
 	help
 	  Selected by platforms that implement ARM generic timers
 
-config ACPI_IORT
-	def_bool n
-	depends on ARCH_ARM64 && HAVE_ACPI_TABLES
-	help
-	  Selected by platforms that implement ARM IO Remap table.
-
 config MAX_ACPI_TABLE_SIZE_KB
 	int
 	default 144
 	help
 	  Set the maximum size of all ACPI tables in KiB.
-
-config ACPI_PPTT
-	bool
-	depends on HAVE_ACPI_TABLES
-	help
-	  Selected to build an ACPI Processor Properties Topology Table.
-
-config ACPI_PPTT_MAX_CACHES
-	int
-	depends on ACPI_PPTT
-	default 4
-	help
-	  This variable sets the maximum number of distinct caches per
-	  topology level. Increasing this option also increases stack usage.
-
-config ACPI_WDAT_WDT
-	bool
-	default n
-	depends on HAVE_ACPI_TABLES
-	help
-	  Selected by platforms that support and fill ACPI Watchdog Action Table
-	  (WDAT).

src/acpi/Makefile.inc

@@ -8,7 +8,6 @@ ramstage-y += acpi_apic.c
 ramstage-y += acpi_dmar.c
 ramstage-y += acpi_hpet.c
 endif
-ramstage-$(CONFIG_ACPI_PPTT) += acpi_pptt.c
 ramstage-y += acpigen.c
 ramstage-y += acpigen_dptf.c
 ramstage-y += acpigen_dsm.c

src/acpi/acpi.c

@@ -14,7 +14,6 @@
  */
 
 #include <acpi/acpi.h>
-#include <acpi/acpi_iort.h>
 #include <acpi/acpi_ivrs.h>
 #include <acpi/acpigen.h>
 #include <cbfs.h>
@@ -22,7 +21,6 @@
 #include <commonlib/helpers.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
-#include <device/device.h>
 #include <device/mmio.h>
 #include <device/pci.h>
 #include <drivers/uart/pl011.h>
@@ -300,9 +298,7 @@ static void acpi_ssdt_write_cbtable(void)
 	acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
 	acpigen_write_name("_CRS");
 	acpigen_write_resourcetemplate_header();
-	acpigen_resource_consumer_mmio(base, base + size - 1,
-				       MEM_RSRC_FLAG_MEM_READ_ONLY
-				       | MEM_RSRC_FLAG_MEM_ATTR_CACHE);
+	acpigen_write_mem32fixed(0, base, size);
 	acpigen_write_resourcetemplate_footer();
 	acpigen_pop_len();
 }
@@ -900,14 +896,6 @@ unsigned long acpi_pl011_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long curren
 				    name);
 }
 
-unsigned long acpi_16550_mmio32_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long current,
-					 uint64_t base, const char *name)
-{
-	return acpi_write_dbg2_uart(rsdp, current, ACPI_ADDRESS_SPACE_MEMORY, base,
-				    0x100, ACPI_ACCESS_SIZE_DWORD_ACCESS,
-				    name);
-}
-
 static void acpi_create_facs(void *header)
 {
 	acpi_facs_t *facs = header;
@@ -1198,45 +1186,6 @@ unsigned long acpi_gtdt_add_watchdog(unsigned long current, uint64_t refresh_fra
 	return current + sizeof(struct acpi_gtdt_watchdog);
 }
 
-static void acpi_create_iort(acpi_header_t *header, void *unused)
-{
-	if (!CONFIG(ACPI_IORT))
-		return;
-
-	acpi_iort_t *iort = (acpi_iort_t *)header;
-	unsigned long current = (unsigned long)iort + sizeof(acpi_iort_t);
-
-	if (acpi_fill_header(header, "IORT", IORT, sizeof(acpi_iort_t)) != CB_SUCCESS)
-		return;
-
-	iort->node_count = 0;
-	iort->node_offset = current - (unsigned long)iort;
-
-	current = acpi_soc_fill_iort(iort, current);
-
-	/* (Re)calculate length */
-	header->length = current - (unsigned long)iort;
-}
-
-static void acpi_create_wdat(acpi_header_t *header, void *unused)
-{
-	if (!CONFIG(ACPI_WDAT_WDT))
-		return;
-
-	acpi_wdat_t *wdat = (acpi_wdat_t *)header;
-	unsigned long current = (unsigned long)wdat + sizeof(acpi_wdat_t);
-
-	memset((void *)wdat, 0, sizeof(acpi_wdat_t));
-
-	if (acpi_fill_header(header, "WDAT", WDAT, sizeof(acpi_wdat_t)) != CB_SUCCESS)
-		return;
-
-	current = acpi_soc_fill_wdat(wdat, current);
-
-	/* (Re)calculate length. */
-	header->length = current - (unsigned long)wdat;
-}
-
 unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid)
 {
 	memset(lpi_desc, 0, sizeof(acpi_lpi_desc_ncst_t));
@@ -1247,18 +1196,6 @@ unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t
 	return lpi_desc->header.length;
 }
 
-static void acpi_create_pptt(acpi_header_t *header, void *unused)
-{
-	if (!CONFIG(ACPI_PPTT))
-		return;
-
-	if (acpi_fill_header(header, "PPTT", PPTT, sizeof(acpi_pptt_t)) != CB_SUCCESS)
-		return;
-
-	acpi_pptt_t *pptt = (acpi_pptt_t *)header;
-	acpi_create_pptt_body(pptt);
-}
-
 static uint8_t acpi_spcr_type(void)
 {
 	/* 16550-compatible with parameters defined in Generic Address Structure */
@@ -1410,8 +1347,6 @@ static void acpixtract_compatible_hexdump(const void *memory, size_t length)
 
 static void acpidump_print(void *table_ptr)
 {
-	if (table_ptr == NULL)
-		return;
 	const acpi_header_t *header = (acpi_header_t *)table_ptr;
 	const size_t table_size = header->length;
 	printk(BIOS_SPEW, "%.4s @ 0x0000000000000000\n", header->signature);
@@ -1451,9 +1386,6 @@ unsigned long write_acpi_tables(const unsigned long start)
 		{ acpi_create_bert, NULL, sizeof(acpi_bert_t) },
 		{ acpi_create_spcr, NULL, sizeof(acpi_spcr_t) },
 		{ acpi_create_gtdt, NULL, sizeof(acpi_gtdt_t) },
-		{ acpi_create_pptt, NULL, sizeof(acpi_pptt_t) },
-		{ acpi_create_iort, NULL, sizeof(acpi_iort_t) },
-		{ acpi_create_wdat, NULL, sizeof(acpi_wdat_t) },
 	};
 
 	current = start;
@@ -1803,12 +1735,6 @@ int get_acpi_table_revision(enum acpi_tables table)
 		return 4;
 	case GTDT:
 		return 3;
-	case PPTT: /* ACPI 6.4 */
-		return 3;
-	case IORT: /* IO Remapping Table E.e */
-		return 6;
-	case WDAT:
-		return 1;
 	default:
 		return -1;
 	}

src/acpi/acpi_apic.c

@@ -5,7 +5,6 @@
 #include <arch/smp/mpspec.h>
 #include <commonlib/sort.h>
 #include <cpu/cpu.h>
-#include <device/device.h>
 
 static int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic)
 {

src/acpi/acpi_gic.c

@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi.h>
-#include <device/device.h>
 
 static int acpi_create_madt_one_gicc_v3(acpi_madt_gicc_t *gicc, u32 acpi_uid, u32 pi_gsiv,
 					uint32_t vgic_mi, uint64_t mpidr)
@@ -80,37 +79,11 @@ static unsigned long acpi_create_madt_gicr_v3(unsigned long current)
 	return current + gicr->length;
 }
 
-__weak int platform_get_gic_its(uintptr_t **base)
-{
-	return 0;
-}
-
-static unsigned long acpi_create_madt_gic_its_v3(unsigned long current)
-{
-	int i, its_count;
-	uintptr_t *its_base;
-
-	its_count = platform_get_gic_its(&its_base);
-
-	for (i = 0; i < its_count; i++) {
-		acpi_madt_gic_its_t *gic_its = (acpi_madt_gic_its_t *)current;
-		memset(gic_its, 0, sizeof(acpi_madt_gic_its_t));
-		gic_its->type = GIC_ITS;
-		gic_its->gic_its_id = i;
-		gic_its->physical_base_address = its_base[i];
-		gic_its->length = sizeof(acpi_madt_gic_its_t);
-
-		current = current + gic_its->length;
-	}
-	return current;
-}
-
 unsigned long acpi_arch_fill_madt(acpi_madt_t *madt, unsigned long current)
 {
 	current = acpi_create_madt_giccs_v3(current);
 	current = acpi_create_madt_gicd_v3(current);
 	current = acpi_create_madt_gicr_v3(current);
-	current = acpi_create_madt_gic_its_v3(current);
 
 	return current;
 }

src/acpi/acpi_hpet.c

@@ -3,7 +3,6 @@
 #include <acpi/acpi.h>
 #include <arch/hpet.h>
 #include <console/console.h>
-#include <device/device.h>
 #include <device/mmio.h>
 #include <version.h>
 

src/acpi/acpi_pptt.c

@@ -1,186 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi.h>
-#include <include/assert.h>
-#include <console/console.h>
-
-/*
- * A structure to hold a cache pointer
- * and its corresponding reference within
- * the PPTT table.
- */
-struct cache_reference {
-	struct pptt_cache *cache; // cache pointer
-	u32                ref;   // and its reference within PPTT
-};
-
-/*
- * A list of 'struct cache_reference', used
- * to keep track of generated caches per topology level.
- */
-struct cache_list {
-	u32                    n_caches;                                // number of caches in list
-	struct cache_reference cache_refs[CONFIG_ACPI_PPTT_MAX_CACHES]; // cache reference list
-};
-
-/*
- * Start of the PPTT table. Constant
- * value as soon as we enter acpi_create_pptt_body.
- */
-static uintptr_t pptt_start;
-
-/* --- Helper Functions (non exposed) --- */
-
-static inline u32 node_to_reference(const void *node)
-{
-	/*
-	 * References are the offset from the start
-	 * of the PPTT table.
-	 *
-	 *    PPTT
-	 * +---------+ <- pptt_start (acpi_pptt_t) <---+
-	 * |         |                                 | node - pptt_start
-	 * |         |                                 |
-	 * +---------+ <- node (cpu or cache) <--------+
-	 * |         |
-	 * |         |
-	 * |         |
-	 * +---------+
-	 */
-	return ((uintptr_t)node - pptt_start);
-}
-
-static u32 count_resources(struct pptt_cpu_resources *res)
-{
-	u32 n_resources = 0;
-
-	while (res != NULL) {
-		n_resources += 1;
-		res = res->next;
-	}
-
-	return n_resources;
-}
-
-static u32 cache_list_ref_of(struct cache_list *cache_list, const struct pptt_cache *cache)
-{
-	/*
-	 * Lookup the PPTT reference of 'cache'.
-	 * Return 0, if no PPTT structure exists for 'cache'.
-	 */
-
-	for (int i = 0; i < cache_list->n_caches; i++) {
-		if (cache_list->cache_refs[i].cache == cache)
-			return cache_list->cache_refs[i].ref;
-	}
-
-	/* no cache reference found */
-	return 0;
-}
-
-static inline void cache_list_append(struct cache_list *cache_list, struct pptt_cache *cache, const u32 ref)
-{
-	printk(BIOS_DEBUG, "acpi: pptt: cache=%p ref=%u\n", cache, ref);
-
-	cache_list->cache_refs[cache_list->n_caches].cache = cache;
-	cache_list->cache_refs[cache_list->n_caches].ref   = ref;
-
-	cache_list->n_caches += 1;
-}
-
-static u32 new_pptt_cache(unsigned long *current, struct pptt_cache *cache, struct cache_list *cache_list)
-{
-	static u32 unique_cache_id = 1;
-	u32 current_reference      = 0;
-
-	if ((current_reference = cache_list_ref_of(cache_list, cache)) != 0)
-		return current_reference;
-
-	if (cache_list->n_caches >= CONFIG_ACPI_PPTT_MAX_CACHES) {
-		printk(BIOS_WARNING, "acpi: pptt: Too many distinct caches! PPTT incomplete.\n");
-		return 0;
-	}
-
-	acpi_pptt_cache_node_t *cache_node = (acpi_pptt_cache_node_t *)*current;
-	memset(cache_node, 0x0, sizeof(acpi_pptt_cache_node_t));
-
-	cache_node->type   = PPTT_NODE_TYPE_CACHE;
-	cache_node->length = sizeof(acpi_pptt_cache_node_t);
-
-	cache_node->flags         = cache->flags.raw;
-	cache_node->size          = cache->size;
-	cache_node->n_sets        = cache->numsets;
-	cache_node->associativity = cache->associativity;
-
-	cache_node->attributes = cache->attributes;
-	cache_node->line_size  = cache->line_size;
-	cache_node->cache_id   = unique_cache_id++;
-
-	*current += cache_node->length;
-
-	current_reference = node_to_reference(cache_node);
-	cache_list_append(cache_list, cache, current_reference);
-
-	if (cache->next_level != NULL)
-		cache_node->next_level = new_pptt_cache(current, cache->next_level, cache_list);
-
-	return current_reference;
-}
-
-static u32 new_pptt_cpu(unsigned long *current, const struct pptt_topology *cpu, const u32 parent_ref, struct cache_list *cache_list)
-{
-	acpi_pptt_cpu_node_t *cpu_node = (acpi_pptt_cpu_node_t *)*current;
-
-	const u32 n_resources      = count_resources(cpu->resources);
-	const u32 structure_length = sizeof(acpi_pptt_cpu_node_t) + (n_resources * sizeof(u32));
-
-	memset(cpu_node, 0x0, structure_length);
-
-	cpu_node->type         = PPTT_NODE_TYPE_CPU;
-	cpu_node->length       = structure_length;
-	cpu_node->flags        = cpu->flags.raw;
-	cpu_node->processor_id = cpu->processor_id;
-	cpu_node->parent       = parent_ref;
-
-	*current += cpu_node->length;
-
-	for (struct pptt_cpu_resources *it = cpu->resources; it != NULL; it = it->next)
-		cpu_node->resources[cpu_node->n_resources++] = new_pptt_cache(current, it->cache, cache_list);
-
-	return node_to_reference(cpu_node);
-}
-
-static void setup_topology(const struct pptt_topology *node, const u32 parent_ref, unsigned long *current)
-{
-	struct cache_list cache_list = {
-		.cache_refs = { },
-		.n_caches   = 0
-	};
-
-	while (node != NULL) {
-		const u32 cpu_ref = new_pptt_cpu(current, node, parent_ref, &cache_list);
-		setup_topology(node->child, cpu_ref, current);
-
-		node = node->sibling;
-	}
-}
-
-/* --- PPTT generation helper functions (exposed) --- */
-
-void acpi_create_pptt_body(acpi_pptt_t *pptt)
-{
-	/* set start of pptt table */
-	pptt_start = (uintptr_t)pptt;
-
-	/* locate start of pptt body */
-	unsigned long current = (unsigned long)(pptt->body);
-
-	/* retrieve processor topology */
-	const struct pptt_topology *topology_tree = acpi_get_pptt_topology();
-
-	/* write processor properties topology table to memory */
-	setup_topology(topology_tree, 0, &current);
-
-	/* update length field in pptt header */
-	pptt->header.length = current - (unsigned long)pptt;
-}

src/acpi/acpigen.c

@@ -2296,54 +2296,42 @@ void acpigen_resource_producer_io(u16 io_base, u16 io_limit)
 			      io_limit - io_base + 1); /* length */
 }
 
-static void acpigen_resource_mmio32(u32 mmio_base, u32 mmio_limit, u16 gen_flags,
-				    u16 type_flags)
+static void acpigen_resource_producer_mmio32(u32 mmio_base, u32 mmio_limit, u16 type_flags)
 {
 	acpigen_resource_dword(RSRC_TYPE_MEM, /* res_type */
-			       gen_flags, /* gen_flags */
-			       type_flags, /* type_flags */
-			       0, /* gran */
-			       mmio_base, /* range_min */
-			       mmio_limit, /* range_max */
-			       0x0, /* translation */
-			       mmio_limit - mmio_base + 1); /* length */
+			      ADDR_SPACE_GENERAL_FLAG_MAX_FIXED
+			      | ADDR_SPACE_GENERAL_FLAG_MIN_FIXED
+			      | ADDR_SPACE_GENERAL_FLAG_DEC_POS
+			      | ADDR_SPACE_GENERAL_FLAG_PRODUCER, /* gen_flags */
+			      type_flags, /* type_flags */
+			      0, /* gran */
+			      mmio_base, /* range_min */
+			      mmio_limit, /* range_max */
+			      0x0, /* translation */
+			      mmio_limit - mmio_base + 1); /* length */
 }
 
-static void acpigen_resource_mmio64(u64 mmio_base, u64 mmio_limit, u16 gen_flags,
-				    u16 type_flags)
+static void acpigen_resource_producer_mmio64(u64 mmio_base, u64 mmio_limit, u16 type_flags)
 {
 	acpigen_resource_qword(RSRC_TYPE_MEM, /* res_type */
-			       gen_flags, /* gen_flags */
-			       type_flags, /* type_flags */
-			       0, /* gran */
-			       mmio_base, /* range_min */
-			       mmio_limit, /* range_max */
-			       0x0, /* translation */
-			       mmio_limit - mmio_base + 1); /* length */
-}
-
-static void acpigen_resource_mmio(u64 mmio_base, u64 mmio_limit, bool is_producer, u16 type_flags)
-{
-	const u16 gen_flags = ADDR_SPACE_GENERAL_FLAG_MAX_FIXED
-		| ADDR_SPACE_GENERAL_FLAG_MIN_FIXED
-		| ADDR_SPACE_GENERAL_FLAG_DEC_POS
-		| (is_producer ? ADDR_SPACE_GENERAL_FLAG_PRODUCER
-		   : ADDR_SPACE_GENERAL_FLAG_CONSUMER);
-
-	if (mmio_base < 4ULL * GiB && mmio_limit < 4ULL * GiB)
-		acpigen_resource_mmio32(mmio_base, mmio_limit, gen_flags, type_flags);
-	else
-		acpigen_resource_mmio64(mmio_base, mmio_limit, gen_flags, type_flags);
+			      ADDR_SPACE_GENERAL_FLAG_MAX_FIXED
+			      | ADDR_SPACE_GENERAL_FLAG_MIN_FIXED
+			      | ADDR_SPACE_GENERAL_FLAG_DEC_POS
+			      | ADDR_SPACE_GENERAL_FLAG_PRODUCER, /* gen_flags */
+			      type_flags, /* type_flags */
+			      0, /* gran */
+			      mmio_base, /* range_min */
+			      mmio_limit, /* range_max */
+			      0x0, /* translation */
+			      mmio_limit - mmio_base + 1); /* length */
 }
 
 void acpigen_resource_producer_mmio(u64 mmio_base, u64 mmio_limit, u16 type_flags)
 {
-	acpigen_resource_mmio(mmio_base, mmio_limit, true, type_flags);
-}
-
-void acpigen_resource_consumer_mmio(u64 mmio_base, u64 mmio_limit, u16 type_flags)
-{
-	acpigen_resource_mmio(mmio_base, mmio_limit, false, type_flags);
+	if (mmio_base < 4ULL * GiB && mmio_limit < 4ULL * GiB)
+		acpigen_resource_producer_mmio32(mmio_base, mmio_limit, type_flags);
+	else
+		acpigen_resource_producer_mmio64(mmio_base, mmio_limit, type_flags);
 }
 
 void acpigen_write_ADR(uint64_t adr)
@@ -2459,10 +2447,10 @@ void acpigen_write_delay_until_namestr_int(uint32_t wait_ms, const char *name, u
 	uint32_t wait_ms_segment = 1;
 	uint32_t segments = wait_ms;
 
-	/* Sleep in 2ms segments if delay is more than 2ms. */
-	if (wait_ms > 2) {
-		wait_ms_segment = 2;
-		segments = wait_ms / wait_ms_segment;
+	/* Sleep in 16ms segments if delay is more than 32ms. */
+	if (wait_ms > 32) {
+		wait_ms_segment = 16;
+		segments = wait_ms / 16;
 	}
 
 	acpigen_write_store_int_to_op(segments, LOCAL7_OP);

src/acpi/acpigen_usb.c

@@ -4,7 +4,6 @@
 #include <acpi/acpi_pld.h>
 #include <acpi/acpigen.h>
 #include <acpi/acpigen_usb.h>
-#include <device/device.h>
 
 static const char *power_role_to_str(enum usb_typec_power_role power_role)
 {

src/acpi/dsdt_top.asl

@@ -57,27 +57,11 @@ Scope(\_SB) {
 	Device (PERC)	// PCI ECAM Resource Consumption
 	{
 		Name (_HID, EisaId("PNP0C02"))
-		Method (_CRS, 0, Serialized)
+		Name (_CRS, ResourceTemplate()
 		{
-			Name (RBUF, ResourceTemplate ()
-			{
-				QWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed,
-				    NonCacheable, ReadWrite,
-				    0x0000000000000000, // Granularity
-				    0x0000000000000000, // _MIN
-				    0x0000000000000001, // _MAX
-				    0x0000000000000000, // Translation
-				    0x0000000000000002, // _Len
-				    ,, _Y00, AddressRangeMemory, TypeStatic)
-			})
-			CreateQWordField (RBUF, \_SB.PERC._CRS._Y00._MIN, MIN1)
-			CreateQWordField (RBUF, \_SB.PERC._CRS._Y00._MAX, MAX1)
-			CreateQWordField (RBUF, \_SB.PERC._CRS._Y00._LEN, LEN1)
-			MIN1 = CONFIG_ECAM_MMCONF_BASE_ADDRESS
-			MAX1 = (MIN1 + CONFIG_ECAM_MMCONF_LENGTH -1)
-			LEN1 = CONFIG_ECAM_MMCONF_LENGTH
-			Return (RBUF)
-		}
+			Memory32Fixed (ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS,
+			CONFIG_ECAM_MMCONF_LENGTH)
+		})
 	}
 }
 #endif

src/arch/arm64/armv8/Makefile.inc

@@ -13,11 +13,6 @@ armv8_flags = -march=$(march) -I$(src)/arch/arm64/include/armv8/ -D__COREBOOT_AR
 ################################################################################
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV8_64),y)
 
-ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
-decompressor-ld-ccopts += -target arm64-elf
-bootblock-ld-ccopts += -target arm64-elf
-endif
-
 ifneq ($(CONFIG_BOOTBLOCK_CUSTOM),y)
 decompressor-y += bootblock.S
 ifneq ($(CONFIG_COMPRESS_BOOTBLOCK),y)
@@ -49,10 +44,6 @@ endif
 ################################################################################
 ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV8_64),y)
 
-ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
-verstage-ld-ccopts += -target arm64-elf
-endif
-
 verstage-y += cache.c
 verstage-y += cpu.S
 verstage-y += exception.c
@@ -66,10 +57,6 @@ endif
 ################################################################################
 ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y)
 
-ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
-romstage-ld-ccopts += -target arm64-elf
-endif
-
 romstage-y += cache.c
 romstage-y += cpu.S
 romstage-y += exception.c
@@ -86,10 +73,6 @@ endif
 ################################################################################
 ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV8_64),y)
 
-ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
-ramstage-ld-ccopts += -target arm64-elf
-endif
-
 ramstage-y += cache.c
 ramstage-y += cpu.S
 ramstage-y += exception.c

src/arch/riscv/Makefile.inc

@@ -96,7 +96,7 @@ endif #CONFIG_ARCH_BOOTBLOCK_RISCV
 ################################################################################
 ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y)
 
-romstage-y += romstage.S
+romstage-y += romstage.c
 
 # Build the romstage
 

src/arch/riscv/include/arch/header.ld

@@ -8,4 +8,8 @@ PHDRS
 	to_load PT_LOAD;
 }
 
+#if ENV_BOOTBLOCK || ENV_RAMSTAGE
 ENTRY(_start)
+#else
+ENTRY(stage_entry)
+#endif

src/arch/riscv/include/arch/stages.h

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __ARCH_STAGES_H
+#define __ARCH_STAGES_H
+
+#include <main_decl.h>
+
+void stage_entry(int hart_id, void *fdt)
+	__attribute__((section(".text.stage_entry")));
+
+#endif

src/arch/riscv/payload.c

@@ -39,6 +39,13 @@ void run_payload(struct prog *prog, void *fdt, int payload_mode)
 	status = INSERT_FIELD(status, MSTATUS_MPIE, 0);
 
 	switch (payload_mode) {
+	case RISCV_PAYLOAD_MODE_U:
+		status = INSERT_FIELD(status, MSTATUS_MPP, PRV_U);
+		/* Trap vector base address point to the payload */
+		write_csr(utvec, doit);
+		/* disable U-Mode interrupt */
+		write_csr(uie, 0);
+		break;
 	case RISCV_PAYLOAD_MODE_S:
 		status = INSERT_FIELD(status, MSTATUS_MPP, PRV_S);
 		/* Trap vector base address point to the payload */

src/arch/riscv/romstage.S

@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/encoding.h>
-#include <bits.h>
-#include <mcall.h>
-
-.section ".text._start", "ax", %progbits
-.globl _start
-_start:
-	# initialize stack point for each hart
-	# and the stack must be page-aligned.
-	# 0xDEADBEEF used to check stack overflow
-	csrr a0, mhartid
-	la   t0, _stack
-	slli t1, a0, RISCV_PGSHIFT
-	add  t0, t0, t1
-	li   t1, 0xDEADBEEF
-	STORE t1, 0(t0)
-	li   t1, RISCV_PGSIZE - HLS_SIZE
-	add  sp, t0, t1
-
-	# initialize hart-local storage
-	csrr a0, mhartid
-	call hls_init
-
-	li   a0, CONFIG_RISCV_WORKING_HARTID
-	call smp_pause
-
-	# initialize entry of interrupt/exception
-	la   t0, trap_entry
-	csrw mtvec, t0
-
-	# clear any pending interrupts
-	csrwi mip, 0
-
-	# set up the mstatus register
-	call mstatus_init
-	tail main

src/arch/riscv/romstage.c

@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * Entry points must be placed at the location the previous stage jumps
+ * to (the lowest address in the stage image). This is done by giving
+ * stage_entry() its own section in .text and placing it first in the
+ * linker script.
+ */
+
+#include <arch/stages.h>
+#include <arch/smp/smp.h>
+#include <mcall.h>
+
+void stage_entry(int hart_id, void *fdt)
+{
+	HLS()->hart_id = hart_id;
+	HLS()->fdt = fdt;
+	smp_pause(CONFIG_RISCV_WORKING_HARTID);
+
+	main();
+}

src/arch/riscv/trap_handler.c

@@ -33,10 +33,10 @@ static const char *const exception_names[] = {
 static const char *mstatus_to_previous_mode(uintptr_t ms)
 {
 	switch (ms & MSTATUS_MPP) {
-	case 0x00000000: return "user";
-	case 0x00000800: return "supervisor";
-	case 0x00001000: return "hypervisor";
-	case 0x00001800: return "machine";
+		case 0x00000000: return "user";
+		case 0x00000800: return "supervisor";
+		case 0x00001000: return "hypervisor";
+		case 0x00001800: return "machine";
 	}
 
 	return "unknown";
@@ -117,31 +117,31 @@ void trap_handler(trapframe *tf)
 	}
 
 	switch (tf->cause) {
-	case CAUSE_MISALIGNED_FETCH:
-	case CAUSE_FETCH_ACCESS:
-	case CAUSE_ILLEGAL_INSTRUCTION:
-	case CAUSE_BREAKPOINT:
-	case CAUSE_LOAD_ACCESS:
-	case CAUSE_STORE_ACCESS:
-	case CAUSE_USER_ECALL:
-	case CAUSE_HYPERVISOR_ECALL:
-	case CAUSE_MACHINE_ECALL:
-		print_trap_information(tf);
-		break;
-	case CAUSE_SUPERVISOR_ECALL:
-		handle_sbi(tf);
-		return;
-	case CAUSE_MISALIGNED_LOAD:
-	case CAUSE_MISALIGNED_STORE:
-		print_trap_information(tf);
-		handle_misaligned(tf);
-		return;
-	default:
-		printk(BIOS_EMERG, "================================\n");
-		printk(BIOS_EMERG, "coreboot: can not handle a trap:\n");
-		printk(BIOS_EMERG, "================================\n");
-		print_trap_information(tf);
-		break;
+		case CAUSE_MISALIGNED_FETCH:
+		case CAUSE_FETCH_ACCESS:
+		case CAUSE_ILLEGAL_INSTRUCTION:
+		case CAUSE_BREAKPOINT:
+		case CAUSE_LOAD_ACCESS:
+		case CAUSE_STORE_ACCESS:
+		case CAUSE_USER_ECALL:
+		case CAUSE_HYPERVISOR_ECALL:
+		case CAUSE_MACHINE_ECALL:
+			print_trap_information(tf);
+			break;
+		case CAUSE_SUPERVISOR_ECALL:
+			handle_sbi(tf);
+			return;
+		case CAUSE_MISALIGNED_LOAD:
+		case CAUSE_MISALIGNED_STORE:
+			print_trap_information(tf);
+			handle_misaligned(tf);
+			return;
+		default:
+			printk(BIOS_EMERG, "================================\n");
+			printk(BIOS_EMERG, "coreboot: can not handle a trap:\n");
+			printk(BIOS_EMERG, "================================\n");
+			print_trap_information(tf);
+			break;
 	}
 
 	die("Can't recover from trap. Halting.\n");

src/arch/x86/Makefile.inc

@@ -317,7 +317,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 
 $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE))
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE))
+	$(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE))
 
 $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"

src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h

@@ -4,7 +4,7 @@
 #define _CBMEM_ID_H_
 
 #define CBMEM_ID_ACPI		0x41435049
-#define CBMEM_ID_ACPI_BERT	0x42455254
+#define CBMEM_ID_ACPI_BERT      0x42455254
 #define CBMEM_ID_ACPI_CNVS	0x434e5653
 #define CBMEM_ID_ACPI_GNVS	0x474e5653
 #define CBMEM_ID_ACPI_HEST	0x48455354
@@ -56,7 +56,7 @@
 #define CBMEM_ID_ROMSTAGE_INFO	0x47545352
 #define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
 #define CBMEM_ID_ROOT		0xff4007ff
-#define CBMEM_ID_SMBIOS		0x534d4254
+#define CBMEM_ID_SMBIOS         0x534d4254
 #define CBMEM_ID_SMM_SAVE_SPACE	0x07e9acee
 #define CBMEM_ID_STAGEx_META	0x57a9e000
 #define CBMEM_ID_STAGEx_CACHE	0x57a9e100
@@ -89,7 +89,6 @@
 #define CBMEM_ID_AMD_MP2	0x5f32504d
 #define CBMEM_ID_CSE_INFO	0x4553435F
 #define CBMEM_ID_CSE_BP_INFO	0x42455343
-#define CBMEM_ID_AMD_OPENSIL	0x4153494C
 
 #define CBMEM_ID_TO_NAME_TABLE				 \
 	{ CBMEM_ID_ACPI,		"ACPI       " }, \
@@ -108,7 +107,7 @@
 	{ CBMEM_ID_CB_EARLY_DRAM,	"EARLY DRAM USAGE" }, \
 	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
 	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
-	{ CBMEM_ID_CPU_CRASHLOG,	"CPU CRASHLOG (deprecated)"}, \
+	{ CBMEM_ID_CPU_CRASHLOG,	"CPU CRASHLOG"}, \
 	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
 	{ CBMEM_ID_ELOG,		"ELOG       " }, \
 	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
@@ -127,7 +126,7 @@
 	{ CBMEM_ID_MMC_STATUS,		"MMC STATUS " }, \
 	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
 	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
-	{ CBMEM_ID_PMC_CRASHLOG,	"PMC CRASHLOG (deprecated)"}, \
+	{ CBMEM_ID_PMC_CRASHLOG,	"PMC CRASHLOG"}, \
 	{ CBMEM_ID_VAR_MRCDATA,		"VARMRC DATA" }, \
 	{ CBMEM_ID_MTC,			"MTC        " }, \
 	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \
@@ -167,10 +166,9 @@
 	{ CBMEM_ID_FSP_LOGO,		"FSP LOGO   "}, \
 	{ CBMEM_ID_SMM_COMBUFFER,	"SMM COMBUFFER"}, \
 	{ CBMEM_ID_TYPE_C_INFO,		"TYPE_C INFO"},\
-	{ CBMEM_ID_MEM_CHIP_INFO,	"MEM CHIP INFO"},\
+	{ CBMEM_ID_MEM_CHIP_INFO,       "MEM CHIP INFO"},\
 	{ CBMEM_ID_AMD_STB,		"AMD STB"},\
 	{ CBMEM_ID_AMD_MP2,		"AMD MP2 BUFFER"},\
 	{ CBMEM_ID_CSE_INFO,		"CSE SPECIFIC INFO"},\
-	{ CBMEM_ID_CSE_BP_INFO,		"CSE BP INFO"}, \
-	{ CBMEM_ID_AMD_OPENSIL,		"OPENSIL DATA"}
+	{ CBMEM_ID_CSE_BP_INFO,		"CSE BP INFO"}
 #endif /* _CBMEM_ID_H_ */

src/cpu/intel/model_206ax/Makefile.inc

@@ -9,6 +9,10 @@ subdirs-y += ../turbo
 
 ramstage-y += acpi.c
 
+ramstage-y += common.c
+romstage-y += common.c
+smm-y += common.c
+
 smm-y += finalize.c
 
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*)

src/cpu/intel/model_206ax/common.c

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/msr.h>
+#include "model_206ax.h"
+
+int get_platform_id(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(IA32_PLATFORM_ID);
+	/* Read Platform Id Bits 52:50 */
+	return (msr.hi >> 18) & 0x7;
+}

src/cpu/intel/model_206ax/model_206ax.h

@@ -73,10 +73,8 @@
 #define  PKG_POWER_LIMIT_TIME_MASK	0x7f
 
 #define MSR_PP0_CURRENT_CONFIG		0x601
-#define  PP0_CURRENT_LIMIT_LOCK		(1U << 31)
 #define  PP0_CURRENT_LIMIT		(112 << 3) /* 112 A */
 #define MSR_PP1_CURRENT_CONFIG		0x602
-#define  PP1_CURRENT_LIMIT_LOCK		(1U << 31)
 #define  PP1_CURRENT_LIMIT_SNB		(35 << 3) /* 35 A */
 #define  PP1_CURRENT_LIMIT_IVB		(50 << 3) /* 50 A */
 #define MSR_PKG_POWER_SKU_UNIT		0x606
@@ -131,6 +129,7 @@ void intel_model_206ax_finalize_smm(void);
 /* Configure power limits for turbo mode */
 void set_power_limits(u8 power_limit_1_time);
 int cpu_config_tdp_levels(void);
+int get_platform_id(void);
 
 static inline u8 cpu_stepping(void)
 {

src/cpu/intel/model_206ax/model_206ax_init.c

@@ -16,7 +16,6 @@
 #include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/common/common.h>
 #include <smbios.h>
-#include <smp/node.h>
 #include <types.h>
 
 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
@@ -171,54 +170,45 @@ static void configure_c_states(void)
 	msr.lo |= (1 << 15);	// Lock C-State MSR
 	wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
 
-	if (boot_cpu()) {
-		/*
-		 * The following MSRs are in scope 'Package', thus it's sufficient
-		 * to write them once on one core.
-		 */
+	msr = rdmsr(MSR_MISC_PWR_MGMT);
+	msr.lo &= ~(1 << 0);	// Enable P-state HW_ALL coordination
+	wrmsr(MSR_MISC_PWR_MGMT, msr);
 
-		msr = rdmsr(MSR_MISC_PWR_MGMT);
-		msr.lo &= ~(1 << 0);	// Enable P-state HW_ALL coordination
-		wrmsr(MSR_MISC_PWR_MGMT, msr);
+	msr = rdmsr(MSR_POWER_CTL);
+	msr.lo |= (1 << 18);	// Enable Energy Perf Bias MSR 0x1b0
+	msr.lo |= (1 << 1);	// C1E Enable
+	msr.lo |= (1 << 0);	// Bi-directional PROCHOT#
+	wrmsr(MSR_POWER_CTL, msr);
 
-		msr = rdmsr(MSR_POWER_CTL);
-		msr.lo |= (1 << 18);	// Enable Energy Perf Bias MSR 0x1b0
-		msr.lo |= (1 << 1);	// C1E Enable
-		msr.lo |= (1 << 0);	// Bi-directional PROCHOT#
-		wrmsr(MSR_POWER_CTL, msr);
+	/* C3 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
+	wrmsr(MSR_PKGC3_IRTL, msr);
 
-		/* C3 Interrupt Response Time Limit */
-		msr.hi = 0;
-		msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
-		wrmsr(MSR_PKGC3_IRTL, msr);
+	/* C6 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
+	wrmsr(MSR_PKGC6_IRTL, msr);
 
-		/* C6 Interrupt Response Time Limit */
-		msr.hi = 0;
-		msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
-		wrmsr(MSR_PKGC6_IRTL, msr);
+	/* C7 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
+	wrmsr(MSR_PKGC7_IRTL, msr);
 
-		/* C7 Interrupt Response Time Limit */
-		msr.hi = 0;
-		msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
-		wrmsr(MSR_PKGC7_IRTL, msr);
+	/* Primary Plane Current Limit */
+	msr = rdmsr(MSR_PP0_CURRENT_CONFIG);
+	msr.lo &= ~0x1fff;
+	msr.lo |= PP0_CURRENT_LIMIT;
+	wrmsr(MSR_PP0_CURRENT_CONFIG, msr);
 
-		/* Primary Plane Current Limit */
-		msr = rdmsr(MSR_PP0_CURRENT_CONFIG);
-		msr.lo &= ~0x1fff;
-		msr.lo |= PP0_CURRENT_LIMIT;
-		msr.lo |= PP0_CURRENT_LIMIT_LOCK;
-		wrmsr(MSR_PP0_CURRENT_CONFIG, msr);
-
-		/* Secondary Plane Current Limit */
-		msr = rdmsr(MSR_PP1_CURRENT_CONFIG);
-		msr.lo &= ~0x1fff;
-		if (IS_IVY_CPU(cpu_get_cpuid()))
-			msr.lo |= PP1_CURRENT_LIMIT_IVB;
-		else
-			msr.lo |= PP1_CURRENT_LIMIT_SNB;
-		msr.lo |= PP1_CURRENT_LIMIT_LOCK;
-		wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
-	}
+	/* Secondary Plane Current Limit */
+	msr = rdmsr(MSR_PP1_CURRENT_CONFIG);
+	msr.lo &= ~0x1fff;
+	if (cpuid_eax(1) >= 0x30600)
+		msr.lo |= PP1_CURRENT_LIMIT_IVB;
+	else
+		msr.lo |= PP1_CURRENT_LIMIT_SNB;
+	wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
 }
 
 static void configure_thermal_target(struct device *dev)
@@ -226,20 +216,13 @@ static void configure_thermal_target(struct device *dev)
 	struct cpu_intel_model_206ax_config *conf = dev->bus->dev->chip_info;
 	msr_t msr;
 
-	if (boot_cpu()) {
-		/*
-		 * The following MSR is in scope 'Package', thus it's sufficient
-		 * to write it once on one core.
-		 */
-
-		/* Set TCC activation offset if supported */
-		msr = rdmsr(MSR_PLATFORM_INFO);
-		if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
-			msr = rdmsr(MSR_TEMPERATURE_TARGET);
-			msr.lo &= ~(0xf << 24); /* Bits 27:24 */
-			msr.lo |= (conf->tcc_offset & 0xf) << 24;
-			wrmsr(MSR_TEMPERATURE_TARGET, msr);
-		}
+	/* Set TCC activation offset if supported */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
+		msr = rdmsr(MSR_TEMPERATURE_TARGET);
+		msr.lo &= ~(0xf << 24); /* Bits 27:24 */
+		msr.lo |= (conf->tcc_offset & 0xf) << 24;
+		wrmsr(MSR_TEMPERATURE_TARGET, msr);
 	}
 }
 
@@ -258,17 +241,10 @@ static void configure_misc(void)
 	msr.hi = 0;
 	wrmsr(IA32_THERM_INTERRUPT, msr);
 
-	if (boot_cpu()) {
-		/*
-		 * The following MSR is in scope 'Package', thus it's sufficient
-		 * to write it once on one core.
-		 */
-
-		/* Enable package critical interrupt only */
-		msr.lo = 1 << 4;
-		msr.hi = 0;
-		wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
-	}
+	/* Enable package critical interrupt only */
+	msr.lo = 1 << 4;
+	msr.hi = 0;
+	wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
 }
 
 static void set_max_ratio(void)
@@ -323,6 +299,9 @@ static void model_206ax_report(void)
 	fill_processor_name(processor_name);
 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
 
+	/* Print platform ID */
+	printk(BIOS_INFO, "CPU: platform id %x\n", get_platform_id());
+
 	/* CPUID and features */
 	cpu_id = cpu_get_cpuid();
 	printk(BIOS_INFO, "CPU: cpuid(1) 0x%x\n", cpu_id);

src/device/Kconfig

@@ -297,6 +297,10 @@ config YABEL_DIRECTHW
 	  they can still access all devices in the system.
 	  Enable this option for a good compromise between security and speed.
 
+config MULTIPLE_VGA_ADAPTERS
+	bool
+	default n
+
 menu "Display"
 	depends on HAVE_VGA_TEXT_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER
 

src/device/i2c_bus.c

@@ -11,8 +11,6 @@
 bool i2c_dev_detect(struct device *dev, unsigned int addr)
 {
 	struct i2c_msg seg = { .flags = 0, .slave = addr, .buf = NULL, .len = 0 };
-	if (!dev)
-		return false;
 	return dev->ops->ops_i2c_bus->transfer(dev, &seg, 1) == 0;
 }
 

src/device/pci_rom.c

@@ -169,8 +169,10 @@ struct rom_header *pci_rom_load(struct device *dev,
 	 * devices have a mismatch between the hardware and the ROM.
 	 */
 	if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
+#if !CONFIG(MULTIPLE_VGA_ADAPTERS)
 		extern struct device *vga_pri; /* Primary VGA device (device.c). */
 		if (dev != vga_pri) return NULL; /* Only one VGA supported. */
+#endif
 		if ((void *)PCI_VGA_RAM_IMAGE_START != rom_header) {
 			printk(BIOS_DEBUG,
 			       "Copying VGA ROM Image from %p to 0x%x, 0x%x bytes\n",

src/drivers/gfx/nvidia/Kconfig

@@ -0,0 +1,38 @@
+config DRIVERS_GFX_NVIDIA
+	bool
+	default n
+	help
+	  Support for NVIDIA Optimus graphics
+
+config DRIVERS_GFX_NVIDIA_BRIDGE
+	hex "PCI bridge for the GPU device"
+	default 0x01
+	depends on DRIVERS_GFX_NVIDIA
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	depends on DRIVERS_GFX_NVIDIA
+	bool
+	default n
+	help
+	  Support for NVIDIA Dynamic Boost
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
+	int "Total processor power offset from default TGP in watts"
+	default 45
+	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	help
+	  This identifies the available power for the CPU or GPU boost
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN
+	int "Minimum TGP offset from default TGP in watts"
+	default 0
+	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	help
+	  This is used to transfer power from the GPU to the CPU
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
+	int "Maximum TGP offset from default TGP in watts"
+	default 0
+	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	help
+	  This is used to transfer power from the CPU to the GPU

src/drivers/gfx/nvidia/Makefile.inc

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
+
+ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c

src/drivers/gfx/nvidia/acpi/coffeelake.asl

@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* NVIDIA GC6 on CFL and CML CPU PCIe ports */
+
+// Memory mapped PCI express config space
+OperationRegion (PCIC, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + (CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15), 0x1000)
+
+Field (PCIC, ByteAcc, NoLock, Preserve) {
+	PVID,   16,
+	PDID,   16,
+
+	Offset (0x248),
+		,   7,
+	L23E,   1,      /* L23_Rdy Entry Request */
+	L23R,   1,      /* L23_Rdy to Detect Transition */
+
+	Offset (0xC20),
+		,   4,
+	P0AP,   2,      /* Additional power savings */
+
+	Offset (0xC38),
+		,   3,
+	P0RM,   1,      /* Robust squelch mechanism */
+}
+
+// Enter L23
+Method (DL23, 0, Serialized) {
+	Printf("      GPU PORT DL23 START")
+
+	L23E = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23E) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+
+	P0RM = 1
+	P0AP = 3
+
+	Printf("      GPU PORT DL23 FINISH")
+}
+
+// Exit L23
+Method (L23D, 0, Serialized) {
+	Printf("      GPU PORT L23D START")
+
+	L23R = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23R) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+
+	P0RM = 0
+	P0AP = 0
+
+	Printf("      GPU PORT L23D FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PORT PWRR._ON")
+
+		^^DEV0._ON()
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PORT PWRR._OFF")
+
+		^^DEV0._OFF()
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
+
+#include "common/gpu.asl"

src/drivers/gfx/nvidia/acpi/common/dsm.asl

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define NV_ERROR_SUCCESS 0x0
+#define NV_ERROR_UNSPECIFIED 0x80000001
+#define NV_ERROR_UNSUPPORTED 0x80000002
+
+#include "gps.asl"
+#include "nvjt.asl"
+
+Method (_DSM, 4, Serialized) {
+	Printf("GPU _DSM")
+	If (Arg0 == ToUUID (JT_DSM_GUID)) {
+		If (ToInteger(Arg1) >= JT_REVISION_ID_MIN) {
+			Return (NVJT(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported JT revision: %o", SFST(Arg1))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	} ElseIf (Arg0 == ToUUID (GPS_DSM_GUID)) {
+		If (ToInteger(Arg1) == GPS_REVISION_ID) {
+			Return (GPS(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported GPS revision: %o", SFST(Arg1))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	} Else {
+		Printf("  Unsupported GUID: %o", IDST(Arg0))
+		Return (NV_ERROR_UNSPECIFIED)
+	}
+}

src/drivers/gfx/nvidia/acpi/common/gps.asl

@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define GPS_DSM_GUID "A3132D01-8CDA-49BA-A52E-BC9D46DF6B81"
+#define GPS_REVISION_ID 0x00000200
+#define GPS_FUNC_SUPPORT 0x00000000
+#define GPS_FUNC_PSHARESTATUS 0x00000020
+#define GPS_FUNC_PSHAREPARAMS 0x0000002A
+
+Method(GPS, 2, Serialized) {
+	Printf("  GPU GPS")
+	Switch(ToInteger(Arg0)) {
+		Case(GPS_FUNC_SUPPORT) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << GPS_FUNC_SUPPORT) |
+				(1 << GPS_FUNC_PSHARESTATUS) |
+				(1 << GPS_FUNC_PSHAREPARAMS)
+			))
+		}
+		Case(GPS_FUNC_PSHARESTATUS) {
+			Printf("    Power Share Status")
+			Return(ITOB(0))
+		}
+		Case(GPS_FUNC_PSHAREPARAMS) {
+			Printf("    Power Share Parameters")
+
+			CreateField(Arg1, 0, 4, QTYP) // Query type
+
+			Name(GPSP, Buffer(36) { 0x00 })
+			CreateDWordField(GPSP, 0, RSTS) // Response status
+			CreateDWordField(GPSP, 4, VERS) // Version
+
+			// Set query type of response
+			RSTS = QTYP
+			// Set version of response
+			VERS = 0x00010000
+
+			Switch(ToInteger(QTYP)) {
+				Case(0) {
+					Printf("      Request Current Information")
+					// No required information
+					Return(GPSP)
+				}
+				Case(1) {
+					Printf("      Request Supported Fields")
+					// Support GPU temperature field
+					RSTS |= (1 << 8)
+					Return(GPSP)
+				}
+				Case(2) {
+					Printf("      Request Current Limits")
+					// No required limits
+					Return(GPSP)
+				}
+				Default {
+					Printf("      Unknown Query: %o", SFST(QTYP))
+					Return(NV_ERROR_UNSUPPORTED)
+				}
+			}
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return(NV_ERROR_UNSUPPORTED)
+		}
+	}
+}

src/drivers/gfx/nvidia/acpi/common/gpu.asl

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (DEV0) {
+	Name(_ADR, 0x00000000)
+
+	#include "utility.asl"
+	#include "dsm.asl"
+	#include "power.asl"
+}
+
+#if CONFIG(DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST)
+Scope (\_SB) {
+	Device(NPCF) {
+		#include "utility.asl"
+		#include "nvpcf.asl"
+	}
+}
+#endif

src/drivers/gfx/nvidia/acpi/common/nvjt.asl

@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define JT_DSM_GUID "CBECA351-067B-4924-9CBD-B46B00B86F34"
+#define JT_REVISION_ID_MIN 0x00000100
+#define JT_REVISION_ID_MAX 0x00000200
+#define JT_FUNC_SUPPORT 0x00000000
+#define JT_FUNC_CAPS 0x00000001
+#define JT_FUNC_POWERCONTROL 0x00000003
+
+//TODO: SMI traps and EGIN/XCLM
+#define JT_GPC_GSS 0 // Get current GPU GCx sleep status
+#define JT_GPC_EGNS 1 // Enter GC6 without self-refresh
+#define JT_GPC_EGIS 2 // Enter GC6 with self-refresh
+#define JT_GPC_XGXS 3 // Exit GC6 and stop self-refresh
+#define JT_GPC_XGIS 4 // Exit GC6 for self-refresh update
+
+#define JT_DFGC_NONE 0 // Handle request immediately
+#define JT_DFGC_DEFER 1 // Defer GPC and GPCX
+//TODO #define JT_DFGC_CLEAR 2 // Clear pending requests
+
+// Deferred GC6 enter/exit until D3-cold (saved DFGC)
+Name(DFEN, 0)
+
+// Deferred GC6 enter control (saved GPC)
+Name(DFCI, 0)
+
+// Deferred GC6 exit control (saved GPCX)
+Name(DFCO, 0)
+
+Method (NVJT, 2, Serialized) {
+	Printf("  GPU NVJT")
+	Switch (ToInteger(Arg0)) {
+		Case (JT_FUNC_SUPPORT) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << JT_FUNC_SUPPORT) |
+				(1 << JT_FUNC_CAPS) |
+				(1 << JT_FUNC_POWERCONTROL)
+			))
+		}
+		Case (JT_FUNC_CAPS) {
+			Printf("    Capabilities")
+			Return(ITOB(
+				(1 << 0) | // G-SYNC NSVR power-saving features are enabled
+				(1 << 1) | // NVSR disabled
+				(2 << 3) | // Panel power and backlight are on the suspend rail
+				(0 << 5) | // self-refresh controller remains powered while panel is powered
+				(0 << 6) | // FB is not on the suspend rail but is powered on in GC6
+				(0 << 8) | // Combined power rail for all GPUs
+				(0 << 10) | // External SPI ROM
+				(1 << 11) | // No SMI handler for kernel panic exit while in GC6
+				(0 << 12) | // Supports notify on GC6 state done
+				(1 << 13) | // Support deferred GC6
+				(1 << 14) | // Support fine-grained root port control
+				(2 << 15) | // GC6 version is GC6-R
+				(0 << 17) | // GC6 exit ISR is not supported
+				(0 << 18) | // GC6 self wakeup not supported
+				(JT_REVISION_ID_MAX << 20) // Highest revision supported
+			))
+		}
+		Case (JT_FUNC_POWERCONTROL) {
+			Printf("    Power Control: %o", SFST(Arg1))
+
+			CreateField (Arg1, 0, 3, GPC) // GPU power control
+			CreateField (Arg1, 4, 1, PPC) // Panel power control
+			CreateField (Arg1, 14, 2, DFGC) // Defer GC6 enter/exit until D3 cold
+			CreateField (Arg1, 16, 3, GPCX) // Deferred GC6 exit control
+
+			// Save deferred GC6 request
+			If ((ToInteger(GPC) != 0) || (ToInteger(DFGC) != 0)) {
+				DFEN = DFGC
+				DFCI = GPC
+				DFCO = GPCX
+			}
+
+			// Buffer to cache current state
+			Name (JTBF, Buffer (4) { 0, 0, 0, 0 })
+			CreateField (JTBF, 0, 3, CGCS) // Current GC state
+			CreateField (JTBF, 3, 1, CGPS) // Current GPU power status
+			CreateField (JTBF, 7, 1, CPSS) // Current panel and SRC state (0 when on)
+
+			// If doing deferred GC6 request, return now
+			If (ToInteger(DFGC) != 0) {
+				CGCS = 1
+				CGPS = 1
+				Return (JTBF)
+			}
+
+			// Apply requested state
+			Switch (ToInteger(GPC)) {
+				Case (JT_GPC_GSS) {
+					Printf("    Get current GPU GCx sleep status")
+					//TODO: include transitions!
+					If (GTXS(DGPU_RST_N)) {
+						// GPU powered on
+						CGCS = 1
+						CGPS = 1
+					} ElseIf (GTXS(DGPU_PWR_EN)) {
+						// GPU powered off, GC6
+						CGCS = 3
+						CGPS = 0
+					} Else {
+						// GPU powered off, D3 cold
+						CGCS = 2
+						CGPS = 0
+					}
+				}
+				Case (JT_GPC_EGNS) {
+					Printf("    Enter GC6 without self-refresh")
+					GC6I()
+					CPSS = 1
+				}
+				Case (JT_GPC_EGIS) {
+					Printf("    Enter GC6 with self-refresh")
+					GC6I()
+					If (ToInteger(PPC) == 0) {
+						CPSS = 0
+					}
+				}
+				Case (JT_GPC_XGXS) {
+					Printf("    Exit GC6 and stop self-refresh")
+					GC6O()
+
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger(PPC) != 0) {
+						CPSS = 0
+					}
+				}
+				Case (JT_GPC_XGIS) {
+					Printf("    Exit GC6 for self-refresh update")
+					GC6O()
+
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger(PPC) != 0) {
+						CPSS = 0
+					}
+				}
+				Default {
+					Printf("    Unsupported GPU power control: %o", SFST(GPC))
+				}
+			}
+
+			Return (JTBF)
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	}
+}

src/drivers/gfx/nvidia/acpi/common/nvpcf.asl

@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define NVPCF_DSM_GUID "36b49710-2483-11e7-9598-0800200c9a66"
+#define NVPCF_REVISION_ID 0x00000200
+#define NVPCF_ERROR_SUCCESS 0x0
+#define NVPCF_ERROR_GENERIC 0x80000001
+#define NVPCF_ERROR_UNSUPPORTED 0x80000002
+#define NVPCF_FUNC_GET_SUPPORTED 0x00000000
+#define NVPCF_FUNC_GET_STATIC_CONFIG_TABLES 0x00000001
+#define NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS 0x00000002
+
+Name(_HID, "NVDA0820")
+
+Name(_UID, "NPCF")
+
+Method(_DSM, 4, Serialized) {
+	Printf("NVPCF _DSM")
+	If (Arg0 == ToUUID(NVPCF_DSM_GUID)) {
+		If (ToInteger(Arg1) == NVPCF_REVISION_ID) {
+			Return(NPCF(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported NVPCF revision: %o", SFST(Arg1))
+			Return(NVPCF_ERROR_GENERIC)
+		}
+	} Else {
+		Printf("  Unsupported GUID: %o", IDST(Arg0))
+		Return(NVPCF_ERROR_GENERIC)
+	}
+}
+
+Method(NPCF, 2, Serialized) {
+	Printf("  NVPCF NPCF")
+	Switch(ToInteger(Arg0)) {
+		Case(NVPCF_FUNC_GET_SUPPORTED) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << NVPCF_FUNC_GET_SUPPORTED) |
+				(1 << NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) |
+				(1 << NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS)
+			))
+		}
+		Case(NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) {
+			Printf("    Get Static Config")
+			Return(Buffer(14) {
+				// Device table header
+				0x20, 0x03, 0x01,
+				// Intel + NVIDIA
+				0x00,
+				// Controller table header
+				0x23, 0x04, 0x05, 0x01,
+				// Dynamic boost controller
+				0x01,
+				// Supports DC
+				0x01,
+				// Reserved
+				0x00, 0x00, 0x00,
+				// Checksum
+				0xAD
+			})
+		}
+		Case(NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS) {
+			Printf("    Update Dynamic Boost")
+
+			CreateField(Arg1, 0x28, 2, ICMD) // Input command
+
+			Name(PCFP, Buffer(49) {
+				// Table version
+				0x23,
+				// Table header size
+				0x05,
+				// Size of common status in bytes
+				0x10,
+				// Size of controller entry in bytes
+				0x1C,
+				// Other fields filled in later
+			})
+			CreateByteField(PCFP, 0x04, CCNT) // Controller count
+			CreateWordField(PCFP, 0x19, ATPP) // AC TPP offset
+			CreateWordField(PCFP, 0x1D, AMXP) // AC maximum TGP offset
+			CreateWordField(PCFP, 0x21, AMNP) // AC minimum TGP offset
+
+			Switch(ToInteger(ICMD)) {
+				Case(0) {
+					Printf("      Get Controller Params")
+					// Number of controllers
+					CCNT = 1
+					// AC total processor power offset from default TGP in 1/8 watt units
+					ATPP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP << 3)
+					// AC maximum TGP offset from default TGP in 1/8 watt units
+					AMXP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX << 3)
+					// AC minimum TGP offset from default TGP in 1/8 watt units
+					AMNP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN << 3)
+					Printf("PCFP: %o", SFST(PCFP))
+					Return(PCFP)
+				}
+				Case(1) {
+					Printf("      Set Controller Status")
+					//TODO
+					Printf("PCFP: %o", SFST(PCFP))
+					Return(PCFP)
+				}
+				Default {
+					Printf("      Unknown Input Command: %o", SFST(ICMD))
+					Return(NV_ERROR_UNSUPPORTED)
+				}
+			}
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return(NVPCF_ERROR_UNSUPPORTED)
+		}
+	}
+}

src/drivers/gfx/nvidia/acpi/common/power.asl

@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+//TODO: evaluate sleeps
+
+OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
+Field (PCIC, DwordAcc, NoLock, Preserve) {
+	Offset (0x40),
+	SSID, 32, // Subsystem vendor and product ID
+}
+
+// Enter GC6
+Method(GC6I, 0, Serialized) {
+	Printf("    GPU GC6I START")
+
+	// Enter L23
+	^^DL23()
+	Sleep(5)
+
+	// Put GPU into reset
+	Printf("      Put GPU into reset")
+	CTXS(DGPU_RST_N)
+	Sleep(5)
+
+	Printf("    GPU GC6I FINISH")
+}
+
+// Exit GC6
+Method(GC6O, 0, Serialized) {
+	Printf("    GPU GC6O START")
+
+	// Bring GPU out of reset
+	Printf("      Bring GPU out of reset")
+	STXS(DGPU_RST_N)
+	Sleep(5)
+
+	// Exit L23
+	^^L23D()
+	Sleep(5)
+
+	Printf("    GPU GC6O FINISH")
+}
+
+Method (_ON, 0, Serialized) {
+	Printf("  GPU _ON START")
+
+	If (DFEN == JT_DFGC_DEFER) {
+		Switch (ToInteger(DFCO)) {
+			Case (JT_GPC_XGXS) {
+				Printf("    Exit GC6 and stop self-refresh")
+				GC6O()
+			}
+			Default {
+				Printf("    Unsupported DFCO: %o", SFST(DFCO))
+			}
+		}
+		DFEN = JT_DFGC_NONE
+	} Else {
+		Printf("    Standard RTD3 power on")
+		STXS(DGPU_PWR_EN)
+		Sleep(5)
+		GC6O()
+	}
+
+	Printf("  GPU _ON FINISH")
+}
+
+Method (_OFF, 0, Serialized) {
+	Printf("  GPU _OFF START")
+
+	If (DFEN == JT_DFGC_DEFER) {
+		Switch (ToInteger(DFCI)) {
+			Case (JT_GPC_EGNS) {
+				Printf("    Enter GC6 without self-refresh")
+				GC6I()
+			}
+			Case (JT_GPC_EGIS) {
+				Printf("    Enter GC6 with self-refresh")
+				GC6I()
+			}
+			Default {
+				Printf("    Unsupported DFCI: %o", SFST(DFCI))
+			}
+		}
+		DFEN = JT_DFGC_NONE
+	} Else {
+		Printf("    Standard RTD3 power off")
+		GC6I()
+		CTXS(DGPU_PWR_EN)
+		Sleep(5)
+	}
+
+	Printf("  GPU _OFF FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PWRR._ON")
+
+		// Restore SSID
+		^^SSID = DGPU_SSID
+		Printf("  Restore SSID: %o", SFST(^^SSID))
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PWRR._OFF")
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })

src/drivers/gfx/nvidia/acpi/common/utility.asl

@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Convert a byte to a hex string, trimming extra parts
+Method (BHEX, 1) {
+	Local0 = ToHexString(Arg0)
+	Return (Mid(Local0, SizeOf(Local0) - 2, 2))
+}
+
+// UUID to string
+Method (IDST, 1) {
+	Local0 = ""
+	Fprintf(
+		Local0,
+		"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
+		BHEX(DerefOf(Arg0[3])),
+		BHEX(DerefOf(Arg0[2])),
+		BHEX(DerefOf(Arg0[1])),
+		BHEX(DerefOf(Arg0[0])),
+		BHEX(DerefOf(Arg0[5])),
+		BHEX(DerefOf(Arg0[4])),
+		BHEX(DerefOf(Arg0[7])),
+		BHEX(DerefOf(Arg0[6])),
+		BHEX(DerefOf(Arg0[8])),
+		BHEX(DerefOf(Arg0[9])),
+		BHEX(DerefOf(Arg0[10])),
+		BHEX(DerefOf(Arg0[11])),
+		BHEX(DerefOf(Arg0[12])),
+		BHEX(DerefOf(Arg0[13])),
+		BHEX(DerefOf(Arg0[14])),
+		BHEX(DerefOf(Arg0[15]))
+	)
+	Return (Local0)
+}
+
+// Safe hex conversion, checks type first
+Method (SFST, 1) {
+	Local0 = ObjectType(Arg0)
+	If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
+		Return (ToHexString(Arg0))
+	} Else {
+		Return (Concatenate("Type: ", Arg0))
+	}
+}
+
+// Convert from 4-byte buffer to 32-bit integer
+Method (BTOI, 1) {
+	Return(
+		DerefOf(Arg0[0]) |
+		(DerefOf(Arg0[1]) << 8) |
+		(DerefOf(Arg0[2]) << 16) |
+		(DerefOf(Arg0[3]) << 24)
+	)
+}
+
+// Convert from 32-bit integer to 4-byte buffer
+Method (ITOB, 1) {
+	Local0 = Buffer(4) { 0, 0, 0, 0 }
+	Local0[0] = Arg0 & 0xFF
+	Local0[1] = (Arg0 >> 8) & 0xFF
+	Local0[2] = (Arg0 >> 16) & 0xFF
+	Local0[3] = (Arg0 >> 24) & 0xFF
+	Return (Local0)
+}

src/drivers/gfx/nvidia/acpi/tigerlake.asl

@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* NVIDIA GC6 on (TGL and ADL) (CPU and PCH) PCIe ports */
+
+// Port mapped PCI express config space
+OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
+
+Field (PCIC, AnyAcc, NoLock, Preserve) {
+	Offset(0x52),  /* LSTS - Link Status Register */
+	, 13,
+	LASX, 1,       /* 0, Link Active Status */
+
+	Offset(0x60),  /* RSTS - Root Status Register */
+	, 16,
+	PSPX, 1,       /* 16,  PME Status */
+
+	Offset(0xD8),  /* 0xD8, MPC - Miscellaneous Port Configuration Register */
+	, 30,
+	HPEX, 1,       /* 30,  Hot Plug SCI Enable */
+	PMEX, 1,       /* 31,  Power Management SCI Enable */
+
+	Offset (0xE0), /* 0xE0, SPR - Scratch Pad Register */
+	SCB0, 1,       /* Scratch bit 0 */
+
+	Offset(0xE2),  /* 0xE2, RPPGEN - Root Port Power Gating Enable */
+	, 2,
+	L23E, 1,       /* 2,   L23_Rdy Entry Request (L23ER) */
+	L23R, 1,       /* 3,   L23_Rdy to Detect Transition (L23R2DT) */
+}
+
+Field (PCIC, AnyAcc, NoLock, WriteAsZeros) {
+	Offset(0xDC),  /* 0xDC, SMSCS - SMI/SCI Status Register */
+	, 30,
+	HPSX, 1,       /* 30,  Hot Plug SCI Status */
+	PMSX, 1        /* 31,  Power Management SCI Status */
+}
+
+// Enter L23
+Method (DL23, 0, Serialized) {
+	Printf("      GPU PORT DL23 START")
+
+	L23E = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23E) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+	SCB0 = 1
+
+	Printf("      GPU PORT DL23 FINISH")
+}
+
+// Exit L23
+Method (L23D, 0, Serialized) {
+	Printf("      GPU PORT L23D START")
+
+	If ((SCB0 == 1)) {
+		L23R = 1
+		Local0 = 0
+		While (L23R) {
+			If ((Local0 > 4)) {
+				Break
+			}
+			Sleep (16)
+			Local0++
+		}
+
+		SCB0 = 0
+		Local0 = 0
+		While ((LASX == 0)) {
+			If ((Local0 > 8)) {
+				Break
+			}
+			Sleep (16)
+			Local0++
+		}
+	}
+
+	Printf("      GPU PORT L23D FINISH")
+}
+
+Method (HPME, 0, Serialized) {
+	Printf("  GPU PORT HPME START")
+
+	If (PMSX == 1) {
+		Printf("    Notify GPU driver of PME SCI")
+		Notify(DEV0, 0x2)
+		Printf("    Clear PME SCI")
+		PMSX = 1
+		Printf("    Consume PME notification")
+		PSPX = 1
+	}
+
+	Printf("  GPU PORT HPME FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PORT PWRR._ON")
+
+		HPME();
+		If (PMEX == 1) {
+			Printf("  Disable power management SCI")
+			PMEX = 0
+		}
+
+		^^DEV0._ON()
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PORT PWRR._OFF")
+
+		^^DEV0._OFF()
+
+		If (PMEX == 0) {
+			Printf("  Enable power management SCI")
+			PMEX = 1
+			HPME()
+		}
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
+
+#include "common/gpu.asl"

src/drivers/gfx/nvidia/chip.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_
+#define _DRIVERS_GFX_NVIDIA_CHIP_H_
+
+struct drivers_gfx_nvidia_config {
+	/* TODO: Set GPIOs in devicetree? */
+};
+
+#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */

src/drivers/gfx/nvidia/gpu.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_
+#define _DRIVERS_GFX_NVIDIA_GPU_H_
+
+#include <stdbool.h>
+
+struct nvidia_gpu_config {
+	/* GPIO for GPU_PWR_EN */
+	unsigned int power_gpio;
+	/* GPIO for GPU_RST# */
+	unsigned int reset_gpio;
+	/* Enable or disable GPU power */
+	bool enable;
+};
+
+void nvidia_set_power(const struct nvidia_gpu_config *config);
+
+#endif /* _DRIVERS_NVIDIA_GPU_H_ */

src/drivers/gfx/nvidia/nvidia.c

@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40
+
+static void nvidia_read_resources(struct device *dev)
+{
+	printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev));
+
+	pci_dev_read_resources(dev);
+
+	// Find all BARs on GPU, mark them above 4g if prefetchable
+	for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
+		struct resource *res = probe_resource(dev, bar);
+
+		if (res) {
+			if (res->flags & IORESOURCE_PREFETCH) {
+				printk(BIOS_INFO, "  BAR at 0x%02x marked above 4g\n", bar);
+				res->flags |= IORESOURCE_ABOVE_4G;
+			} else {
+				printk(BIOS_DEBUG, "  BAR at 0x%02x not prefetch\n", bar);
+			}
+		} else {
+			printk(BIOS_DEBUG, "  BAR at 0x%02x not found\n", bar);
+		}
+	}
+}
+
+static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
+{
+	pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations nvidia_device_ops_pci = {
+	.set_subsystem = nvidia_set_subsystem,
+};
+
+static struct device_operations nvidia_device_ops = {
+	.read_resources   = nvidia_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.write_acpi_tables = pci_rom_write_acpi_tables,
+	.acpi_fill_ssdt    = pci_rom_ssdt,
+#endif
+	.init             = pci_dev_init,
+	.ops_pci          = &nvidia_device_ops_pci,
+
+};
+
+static void nvidia_enable(struct device *dev)
+{
+	if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
+		return;
+
+	if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_NVIDIA)
+		return;
+
+	dev->ops = &nvidia_device_ops;
+}
+
+struct chip_operations drivers_gfx_nvidia_ops = {
+	CHIP_NAME("NVIDIA Optimus Graphics Device")
+	.enable_dev = nvidia_enable
+};

src/drivers/gfx/nvidia/romstage.c

@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <gpio.h>
+#include "chip.h"
+#include "gpu.h"
+
+void nvidia_set_power(const struct nvidia_gpu_config *config)
+{
+	if (!config->power_gpio || !config->reset_gpio) {
+		printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__);
+		return;
+	}
+
+	printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio);
+	printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio);
+
+	gpio_set(config->reset_gpio, 0);
+	mdelay(10);
+
+	if (config->enable) {
+		gpio_set(config->power_gpio, 1);
+		mdelay(25);
+		gpio_set(config->reset_gpio, 1);
+	} else {
+		gpio_set(config->power_gpio, 0);
+	}
+
+	mdelay(10);
+}

src/drivers/intel/dtbt/Kconfig

@@ -0,0 +1,5 @@
+config DRIVERS_INTEL_DTBT
+	bool
+	default n
+	help
+	  Support for discrete Thunderbolt controllers

src/drivers/intel/dtbt/Makefile.inc

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_DRIVERS_INTEL_DTBT) += dtbt.c

src/drivers/intel/dtbt/chip.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_INTEL_DTBT_CHIP_H_
+#define _DRIVERS_INTEL_DTBT_CHIP_H_
+
+struct drivers_intel_dtbt_config {};
+
+#endif /* _DRIVERS_INTEL_DTBT_CHIP_H_ */

src/drivers/intel/dtbt/dtbt.c

@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include <acpi/acpigen.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include <device/pci_ids.h>
+
+#define PCIE2TBT 0x54C
+#define PCIE2TBT_GO2SX ((0x02 << 1) | 1)
+#define PCIE2TBT_GO2SX_NO_WAKE ((0x03 << 1) | 1)
+#define PCIE2TBT_SX_EXIT_TBT_CONNECTED ((0x04 << 1) | 1)
+#define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED ((0x05 << 1) | 1)
+#define PCIE2TBT_SET_SECURITY_LEVEL ((0x08 << 1) | 1)
+#define PCIE2TBT_GET_SECURITY_LEVEL ((0x09 << 1) | 1)
+#define PCIE2TBT_BOOT_ON ((0x18 << 1) | 1)
+#define TBT2PCIE 0x548
+
+static void dtbt_cmd(struct device *dev, u32 command)
+{
+	printk(BIOS_DEBUG, "DTBT send command %08x\n", command);
+
+	pci_write_config32(dev, PCIE2TBT, command);
+
+	u32 timeout;
+	u32 status;
+	for (timeout = 1000000; timeout > 0; timeout--) {
+		status = pci_read_config32(dev, TBT2PCIE);
+		if (status & 1) {
+			break;
+		}
+		udelay(1);
+	}
+	if (timeout == 0) {
+		printk(BIOS_ERR, "DTBT command %08x timeout on status %08x\n", command, status);
+	}
+
+	printk(BIOS_DEBUG, "DTBT command %08x status %08x\n", command, status);
+
+	pci_write_config32(dev, PCIE2TBT, 0);
+
+	u32 status_clear;
+	for (timeout = 1000000; timeout > 0; timeout--) {
+		status_clear = pci_read_config32(dev, TBT2PCIE);
+		if (!(status_clear & 1)) {
+			break;
+		}
+		udelay(1);
+	}
+	if (timeout == 0) {
+		printk(BIOS_ERR, "DTBT command %08x timeout on status clear %08x\n", command, status_clear);
+	}
+}
+
+static void dtbt_fill_ssdt(const struct device *dev)
+{
+	printk(BIOS_DEBUG, "DTBT fill SSDT\n");
+
+	if (!dev) {
+		printk(BIOS_ERR, "DTBT device invalid\n");
+	}
+	printk(BIOS_DEBUG, "  Dev %s\n", dev_path(dev));
+
+	struct bus *bus = dev->bus;
+	if (!bus) {
+		printk(BIOS_ERR, "DTBT bus invalid\n");
+	}
+	printk(BIOS_DEBUG, "  Bus %s\n", bus_path(bus));
+
+	struct device *parent = bus->dev;
+	if (!parent || parent->path.type != DEVICE_PATH_PCI) {
+		printk(BIOS_ERR, "DTBT parent invalid\n");
+		return;
+	}
+	printk(BIOS_DEBUG, "  Parent %s\n", dev_path(parent));
+
+	const char *parent_scope = acpi_device_path(parent);
+	if (!parent_scope) {
+		printk(BIOS_ERR, "DTBT parent scope not valid\n");
+		return;
+	}
+
+	{ /* Scope */
+		printk(BIOS_DEBUG, "  Scope %s\n", parent_scope);
+		acpigen_write_scope(parent_scope);
+
+		struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
+
+		/* Indicate that device supports hotplug in D3. */
+		acpi_device_add_hotplug_support_in_d3(dsd);
+
+		/* Indicate that port is external. */
+		acpi_device_add_external_facing_port(dsd);
+
+		acpi_dp_write(dsd);
+
+		{ /* Device */
+			const char *dev_name = acpi_device_name(dev);
+			printk(BIOS_DEBUG, "    Device %s\n", dev_name);
+			acpigen_write_device(dev_name);
+
+			acpigen_write_name_integer("_ADR", 0);
+
+			uintptr_t mmconf_base = (uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS
+						+ (((uintptr_t)(bus->secondary)) << 20);
+			printk(BIOS_DEBUG, "      MMCONF base %08lx\n", mmconf_base);
+			const struct opregion opregion = OPREGION("PXCS", SYSTEMMEMORY, mmconf_base, 0x1000);
+			const struct fieldlist fieldlist[] = {
+				FIELDLIST_OFFSET(TBT2PCIE),
+				FIELDLIST_NAMESTR("TB2P", 32),
+				FIELDLIST_OFFSET(PCIE2TBT),
+				FIELDLIST_NAMESTR("P2TB", 32),
+			};
+			acpigen_write_opregion(&opregion);
+			acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist),
+					    FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE);
+
+			{ /* Method */
+				acpigen_write_method_serialized("PTS", 0);
+
+				acpigen_write_debug_string("DTBT prepare to sleep");
+
+				acpigen_write_store_int_to_namestr(PCIE2TBT_GO2SX_NO_WAKE, "P2TB");
+				acpigen_write_delay_until_namestr_int(600, "TB2P", PCIE2TBT_GO2SX_NO_WAKE);
+
+				acpigen_write_debug_namestr("TB2P");
+
+				acpigen_write_store_int_to_namestr(0, "P2TB");
+				acpigen_write_delay_until_namestr_int(600, "TB2P", 0);
+
+				acpigen_write_debug_namestr("TB2P");
+
+				acpigen_write_method_end();
+			}
+
+			acpigen_write_device_end();
+		}
+
+		acpigen_write_scope_end();
+	}
+
+	{ /* Scope */
+		acpigen_write_scope("\\");
+
+		{ /* Method */
+			acpigen_write_method("TBTS", 0);
+
+			acpigen_emit_namestring(acpi_device_path_join(dev, "PTS"));
+
+			acpigen_write_method_end();
+		}
+
+		acpigen_write_scope_end();
+	}
+}
+
+static const char *dtbt_acpi_name(const struct device *dev)
+{
+	return "DTBT";
+}
+
+static struct pci_operations dtbt_device_ops_pci = {
+	.set_subsystem = 0,
+};
+
+static struct device_operations dtbt_device_ops = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.acpi_fill_ssdt   = dtbt_fill_ssdt,
+	.acpi_name        = dtbt_acpi_name,
+	.scan_bus         = pciexp_scan_bridge,
+	.reset_bus        = pci_bus_reset,
+	.ops_pci          = &dtbt_device_ops_pci,
+};
+
+static void dtbt_enable(struct device *dev)
+{
+	if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
+		return;
+
+	if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_INTEL)
+		return;
+
+	// TODO: check device ID
+
+	dev->ops = &dtbt_device_ops;
+
+	printk(BIOS_INFO, "DTBT controller found at %s\n", dev_path(dev));
+
+	printk(BIOS_DEBUG, "DTBT get security level\n");
+	dtbt_cmd(dev, PCIE2TBT_GET_SECURITY_LEVEL);
+
+	printk(BIOS_DEBUG, "DTBT set security level SL0\n");
+	dtbt_cmd(dev, PCIE2TBT_SET_SECURITY_LEVEL);
+
+	printk(BIOS_DEBUG, "DTBT get security level\n");
+	dtbt_cmd(dev, PCIE2TBT_GET_SECURITY_LEVEL);
+
+	if (acpi_is_wakeup_s3()) {
+		printk(BIOS_INFO, "DTBT SX exit\n");
+		dtbt_cmd(dev, PCIE2TBT_SX_EXIT_TBT_CONNECTED);
+	} else {
+		printk(BIOS_INFO, "DTBT boot on\n");
+		dtbt_cmd(dev, PCIE2TBT_BOOT_ON);
+	}
+}
+
+struct chip_operations drivers_intel_dtbt_ops = {
+	CHIP_NAME("Intel Discrete Thunderbolt Device")
+	.enable_dev = dtbt_enable
+};

src/drivers/intel/fsp2_0/Makefile.inc

@@ -162,7 +162,7 @@ $(error No second FSP-S binary file specified.)
 endif # CONFIG_FSP_S_FILE_2
 endif # CONFIG_PLATFORM_USES_SECOND_FSP
 else # CONFIG_ADD_FSP_BINARIES
-show_notices:: warn_no_fsp_binaries
+build_complete:: warn_no_fsp_binaries
 endif # CONFIG_ADD_FSP_BINARIES
 
 PHONY+=warn_no_fsp_binaries

src/drivers/maxim/max77686/max77686.h

@@ -77,8 +77,8 @@ enum {
 };
 
 enum {
-	MAX77686_MV = 0,	/* millivolt */
-	MAX77686_UV		/* microvolt */
+	MAX77686_MV = 0,	/* mili volt */
+	MAX77686_UV		/* micro volt */
 };
 
 /**

src/drivers/maxim/max77802/max77802.h

@@ -199,7 +199,7 @@ enum {
 #define MAX77802_BUCK_TYPE2_ON	(1 << 4)
 #define MAX77802_BUCK_TYPE2_IGNORE_PWRREQ (1 << 5)
 
-/* LDO35 1.2 volt value for bridge IC */
+/* LDO35 1.2 volt value for bridge ic */
 #define MAX77802_LDO35CTRL1_1_2V (1 << 4)
 #define MAX77802_LOD35CTRL1_ON	 (1 << 6)
 

src/drivers/mipi/panel-CMN_P097PFG_SSD2858.c

@@ -21,7 +21,7 @@ struct panel_serializable_data P097PFG_SSD2858 = {
 	.init = {
 		PANEL_GENERIC(0xff, 0x00),
 		/* LOCKCNT=0x1f4, MRX=0, POSTDIV=1 (/2} }, MULT=0x49
-		 * 27 MHz => 985.5 MHz */
+		 * 27 Mhz => 985.5 Mhz */
 		PANEL_GENERIC(0x00, 0x08, 0x01, 0xf4, 0x01, 0x49),
 		/* MTXDIV=1, SYSDIV=3 (=> 4) */
 		PANEL_GENERIC(0x00, 0x0c, 0x00, 0x00, 0x00, 0x03),
@@ -34,7 +34,7 @@ struct panel_serializable_data P097PFG_SSD2858 = {
 		PANEL_GENERIC(0x10, 0x08, 0x01, 0x20, 0x08, 0x45),
 		PANEL_GENERIC(0x10, 0x1c, 0x00, 0x00, 0x00, 0x00),
 		PANEL_GENERIC(0x20, 0x0c, 0x00, 0x00, 0x00, 0x04),
-		/* Pixel clock 985.5 MHz * 0x49/0x4b = 959 MHz */
+		/* Pixel clock 985.5 Mhz * 0x49/0x4b = 959 Mhz */
 		PANEL_GENERIC(0x20, 0x10, 0x00, 0x4b, 0x00, 0x49),
 		PANEL_GENERIC(0x20, 0xa0, 0x00, 0x00, 0x00, 0x00),
 		/* EOT=1, LPE = 0, LSOUT=4 lanes, LPD=25 */

src/drivers/mrc_cache/mrc_cache.c

@@ -431,7 +431,7 @@ static void log_event_cache_update(uint8_t slot, enum result res)
 /* During ramstage this code purposefully uses incoherent transactions between
  * read and write. The read assumes a memory-mapped boot device that can be used
  * to quickly locate and compare the up-to-date data. However, when an update
- * is required it uses the writable region access to perform the update. */
+ * is required it uses the writeable region access to perform the update. */
 static void update_mrc_cache_by_type(int type,
 				     struct mrc_metadata *new_md,
 				     const void *new_data,

src/drivers/net/atl1e.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 /*
- * This driver sets the MAC address of an Atheros AR8121/AR8113/AR8114
+ * This driver sets the macaddress of a Atheros AR8121/AR8113/AR8114
  */
 
 #include <device/mmio.h>

src/drivers/ocp/include/vpd.h

@@ -64,7 +64,7 @@ enum cxl_memory_mode {
 #define DISABLE_BOOTDRIVE "disable_bootdrive"
 #define DISABLE_BOOTDRIVE_DEFAULT 0 /* By default don't disable */
 
-/* Skip Global reset so that information in Previous Boot Error HOB won't be cleared */
+/* Skip Global reset so that information in Previous Boot Error Hob won't be cleared */
 #define SKIP_GLOBAL_RESET "skip_global_reset"
 #define SKIP_GLOBAL_RESET_DEFAULT 1
 

src/drivers/smmstore/ramstage.c

@@ -8,6 +8,7 @@
 #include <smmstore.h>
 #include <types.h>
 #include <cbmem.h>
+#include <delay.h>
 
 static struct smmstore_params_info info;
 
@@ -39,6 +40,7 @@ static void init_store(void *unused)
 	struct smmstore_params_init args;
 	uint32_t eax = ~0;
 	uint32_t ebx;
+	uint8_t retry = 5;
 
 	if (smmstore_get_info(&info) < 0) {
 		printk(BIOS_INFO, "SMMSTORE: Failed to get meta data\n");
@@ -57,14 +59,24 @@ static void init_store(void *unused)
 
 	printk(BIOS_INFO, "SMMSTORE: Setting up SMI handler\n");
 
-	/* Issue SMI using APM to update the com buffer and to lock the SMMSTORE */
-	__asm__ __volatile__ (
-		"outb %%al, %%dx"
-		: "=a" (eax)
-		: "a" ((SMMSTORE_CMD_INIT << 8) | APM_CNT_SMMSTORE),
-		  "b" (ebx),
-		  "d" (APM_CNT)
-		: "memory");
+	/*
+	 * Issue SMI using APM to update the com buffer and to lock the SMMSTORE.
+	 * Retry 5 times in case the SMI isn't triggered immediately.
+	 */
+	do {
+		__asm__ __volatile__ (
+			"outb %%al, %%dx"
+			: "=a" (eax)
+			: "a" ((SMMSTORE_CMD_INIT << 8) | APM_CNT_SMMSTORE),
+			  "b" (ebx),
+			  "d" (APM_CNT)
+			: "memory");
+
+		if (eax == SMMSTORE_RET_SUCCESS)
+			break;
+
+		mdelay(1);
+	} while (retry--);
 
 	if (eax != SMMSTORE_RET_SUCCESS) {
 		printk(BIOS_ERR, "SMMSTORE: Failed to install com buffer\n");

src/drivers/smmstore/store.c

@@ -185,7 +185,7 @@ static enum cb_err scan_end(struct region_device *store)
 
 	if (k_sz != 0xffffffff) {
 		printk(BIOS_WARNING,
-			"EOF of data marker looks invalid: 0x%x\n", k_sz);
+			"eof of data marker looks invalid: 0x%x\n", k_sz);
 		return CB_ERR;
 	}
 

src/drivers/spi/Kconfig

@@ -155,13 +155,6 @@ config SPI_FLASH_WINBOND
 	  Select this option if your chipset driver needs to store certain
 	  data in the SPI flash and your SPI flash is made by Winbond.
 
-config SPI_FLASH_ISSI
-	bool
-	default y if SPI_FLASH_INCLUDE_ALL_DRIVERS
-	help
-	  Select this option if your chipset driver needs to store certain
-	  data in the SPI flash and your SPI flash is made by ISSI.
-
 config SPI_FLASH_HAS_VOLATILE_GROUP
 	bool
 	default n

src/drivers/spi/Makefile.inc

@@ -30,7 +30,6 @@ $(1)-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c
 $(1)-$(CONFIG_SPI_FLASH_SST) += sst.c
 $(1)-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c
 $(1)-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c
-$(1)-$(CONFIG_SPI_FLASH_ISSI) += issi.c
 endef
 
 $(eval $(call add_spi_stage,bootblock,_EARLY))

src/drivers/spi/issi.c

@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <console/console.h>
-#include <commonlib/helpers.h>
-#include <spi_flash.h>
-#include <spi-generic.h>
-#include <delay.h>
-#include <lib.h>
-
-#include "spi_flash_internal.h"
-
-static const struct spi_flash_part_id flash_table[] = {
-	{
-		/* IS25WP256D */
-		.id[0]				= 0x7019,
-		.nr_sectors_shift		= 13,
-	},
-};
-
-const struct spi_flash_vendor_info spi_flash_issi_vi = {
-	.id = VENDOR_ID_ISSI,
-	.page_size_shift = 8,        // 256 byte page size
-	.sector_size_kib_shift = 2,  // 4 Kbyte sector size
-	.match_id_mask[0] = 0xffff,
-	.ids = flash_table,
-	.nr_part_ids = ARRAY_SIZE(flash_table),
-	.desc = &spi_flash_pp_0x20_sector_desc,
-	.prot_ops = NULL,
-};

src/drivers/spi/spi-generic.c

@@ -101,7 +101,7 @@ unsigned int spi_crop_chunk(const struct spi_slave *slave, unsigned int cmd_len,
 	/* Subtract command length from usable buffer size. If
 	   deduct_opcode_len is set, only subtract the number command bytes
 	   after the opcode. If the adjusted cmd_len is larger than ctrlr_max
-	   return 0 to indicate an error. */
+	   return 0 to inidicate an error. */
 	if (deduct_cmd_len) {
 		if (ctrlr_max >= cmd_len) {
 			ctrlr_max -= cmd_len;

src/drivers/spi/spi_flash.c

@@ -397,9 +397,6 @@ static const struct spi_flash_vendor_info *spi_flash_vendors[] = {
 #if CONFIG(SPI_FLASH_WINBOND)
 	&spi_flash_winbond_vi,
 #endif
-#if CONFIG(SPI_FLASH_ISSI)
-	&spi_flash_issi_vi,
-#endif
 };
 #define IDCODE_LEN 5
 

src/drivers/spi/spi_flash_internal.h

@@ -112,7 +112,7 @@ extern const struct spi_flash_vendor_info spi_flash_atmel_vi;
 extern const struct spi_flash_vendor_info spi_flash_eon_vi;
 extern const struct spi_flash_vendor_info spi_flash_gigadevice_vi;
 extern const struct spi_flash_vendor_info spi_flash_macronix_vi;
-/* Probing order matters between the Spansion sequence. */
+/* Probing order matters between the spansion sequence. */
 extern const struct spi_flash_vendor_info spi_flash_spansion_ext1_vi;
 extern const struct spi_flash_vendor_info spi_flash_spansion_ext2_vi;
 extern const struct spi_flash_vendor_info spi_flash_spansion_vi;
@@ -123,7 +123,6 @@ extern const struct spi_flash_vendor_info spi_flash_stmicro2_vi;
 extern const struct spi_flash_vendor_info spi_flash_stmicro3_vi;
 extern const struct spi_flash_vendor_info spi_flash_stmicro4_vi;
 extern const struct spi_flash_vendor_info spi_flash_winbond_vi;
-extern const struct spi_flash_vendor_info spi_flash_issi_vi;
 
 /* Page Programming Command Set with 0x20 Sector Erase command. */
 extern const struct spi_flash_ops_descriptor spi_flash_pp_0x20_sector_desc;