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20 Commits

Author SHA1 Message Date
Tim Crawford
02221a31f0 mb/system76/rpl: darp9: Add SSD RTD3 configs
Some drives block the CPU from reaching C10 on suspend without the RTD3
config.

Fixes suspend with the following drives:

- Kingston KC3000 (SKC3000D/4096G)
- Kingston HyperX (SHPM2280P2H/240G)
- Solidigm P44 Pro (SSDPFKKW010X7)

The following drives continue to work:

- Samsung 970 Evo (MZVLB250HAHQ)
- WD Black SN770 (WDS250G3X0E)
- WD Green SN350 (WDS240G2G0C-00AJM0)
- WD Blue SN570 (WDS100T3B0C)

Change-Id: I205d78377fa2b0db8d37542cdb94ba86ded1d66e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Tested-by: Levi Portenier <levi@system76.com>
2024-01-22 08:50:54 -07:00
Tim Crawford
cd9cf8b9a5 mb/system76: Add custom CMOS default for darp8,darp9
Since these boards will use S0ix they need to leave CSME enabled for the
CPU to reach C10.

Change-Id: I70c908402c9964508bb9c439d48d24773f5a35ab
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-01-11 08:54:34 -07:00
Tim Crawford
09bdd1e515 mb/system76: Enable S0ix for darp8/darp9
The newer batch of these boards do not de-assert VW PLTRST# on S3
resume, causes the units to not power on in the EC code. Switch them to
S0ix by default, but leave S3 available.

Change-Id: I95337c1391102db9e020e82bdd938659c1a4f905
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-01-11 08:54:23 -07:00
Tim Crawford
1a5bdc52cc mb/system76: Enable EC lockdown on TGL+
Change-Id: I4b07846c404eb93ab4baf0a78a4bbffcc5d8afca
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-12-19 08:41:08 -07:00
Tim Crawford
2f5e31762c ec/system76: Support lockdown based on EC security state
Change-Id: I202c0607c2cdac1df59f42fb41735704dd5bd95c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-12-19 08:41:08 -07:00
Tim Crawford
8270aee13e mb/system76: Enable dGPUs
Change-Id: I28fe45afaccd60621f2f2456af14306e18df2657
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-12-19 08:41:08 -07:00
Jeremy Soller
1cf29703ee drivers/gfx/nvidia: Add driver for NVIDIA GPU
Add a driver for laptops with NVIDIA Optimus (hybrid) graphics. The
driver provides ACPI support for dynamically powering on and off the
GPU, NVIDIA Dynamic Boost support, and a function for enabling the GPU
power in romstage.

References:
- DG-09845-001: NVIDIA GN20/QN20 Hardware Design Guide
- DG-09954-001: NVIDIA GN20/QN20 Software Design Guide

Change-Id: I2dec7aa2c8db7994f78a7cc1220502676e248465
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-11-19 22:05:06 -07:00
Tim Crawford
f97ffca766 soc/intel/alderlake: Add IRQ for non-existent CPU PCIe device
Device 0:01.1 does not exist on ADL-P. I assume this works because the
bridged device has function 1.

Fixes the following error in Linux:

    pcieport 0000:00:01.0: can't derive routing for PCI INT B
    snd_hda_intel 0000:01:00.1: PCI INT B: no GSI - using ISA IRQ 10

Which in turn resolves the conflict with the PCH HDA device...again:

    irq 10: nobody cared (try booting with the "irqpoll" option)
    <snip>
    [<00000000bf549647>] azx_interrupt [snd_hda_codec]
    Disabling IRQ #10

Change-Id: I9d9a0003764a1e031be578c1f406b2a5d7512de7
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-11-19 22:05:06 -07:00
Tim Crawford
c93689d557 mb/system76/bonw14: Enable TAS5825M smart amp
The Bonobo has 2 AMPs: one for the speakers and one for the subwoofer.

Smart AMP data was collected using a logic analyzer connected to the IC
during system start on proprietary firmware. This data is then used to
generate a C file [1].

[1]: https://github.com/system76/smart-amp

Change-Id: I5389a9890563ebd3adb20096b6225f474bc006f9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-11-19 22:05:06 -07:00
Tim Crawford
dca78e4373 mb/system76/rpl: Enable discrete TBT device
The HX board, using PCH-S, use a discrete Thunderbolt device (Intel
Maple Ridge), as opposed to a built-in one like the boards using PCH-P.

Fixes Thunderbolt on RPL-HX boards using the Maple Ridge controller.

Change-Id: I53d18f3ec5a084431e1113782c791bcb42728350
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-11-19 22:05:06 -07:00
Jeremy Soller
fa90e35cae drivers/intel/dtbt: Add discrete Thunderbolt driver
Add a new driver for discrete Thunderbolt controllers. This allows using
Maple Ridge devices on Raptor Point PCH.

Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-11-19 22:05:06 -07:00
Jeremy Soller
3289a306e6 lib,soc/intel/common/block/smbus: Use a SPD length of 512 bytes for DDR5
Change-Id: I8bdc4c676a0f571fd8f34e078f6a1c73a2e90a87
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-11-19 22:05:06 -07:00
Jeremy Soller
7fcf710e7f soc/intel/adl: Fill in SPD data on both channels of DDR5 memory
CB:52731 introduced support for reading SPD from the EEPROM via SMBus.
Replace the now unneeded workaround for DDR5 with filling in the correct
channels for DDR5.

Change-Id: I5a92199a7cd2718e9396f0dac8257df40e4f834c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-11-19 22:05:06 -07:00
Meera Ravindranath
828935066d soc/common/smbus: Add support for reading spd data via smbus for DDR5
DDR5 uses a Serial Presence Detect EEPROM with hub function
(SPD5 hub device) to store the spd data.
This CL adds support to read the spd5 hub device via smbus.

BUG=b:180458099
TEST=Boot adlrvp DDR5 board to kernel

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe
2023-11-19 22:05:06 -07:00
Jeremy Soller
e312861a9d soc/intel/alderlake: Hack to preserve SBREG
Change-Id: Ie70905d34a4050aeff4b5cda116eb700f19a18ea
2023-11-19 22:05:06 -07:00
Michał Kopeć
5f608c9734 drivers/smmstore/ramstage.c: retry smmstore init up 5 times
Retry calling the SMI 5 times in case the initial write to APM did not
cause SMM entry immediately.

Fixes occasional SMMSTORE initialization failure on Clevo NV4xPZ with
Intel i5-1240P processor. The issue was especially evident when all
logging in coreboot was disabled.

Based on SMMSTORE implementation in MrChromebox's fork of EDK2:
27854bc8c5

Change-Id: I8929af25c4f69873bbdd835fde5cb60fc324b6ab
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-11-19 22:05:06 -07:00
Tim Crawford
d9977a9fa9 security/tpm/tspi: Do TPM Restart if TPM Resume fails
The Infineon SLB 9672 on newer Clevo machines regularly fails TPM Resume
on S3 with the error `TPM_RC_VALUE`.

Per TPM2 spec, handle the failure by performing a TPM Restart.

> The startup behavior defined by this specification is different than
> TPM 1.2 with respect to Startup(STATE). A TPM 1.2 device will enter
> Failure Mode if no state is available when the TPM receives
> Startup(STATE). This is not the case in this specification. It is up
> to the CRTM to take corrective action if it the TPM returns
> TPM_RC_VALUE in response to Startup(STATE).

Fixes the following error from being repeatedly logged in Linux:

> kernel: tpm tpm0: A TPM error (256) occurred attempting get random

Ref: Trusted Platform Module Library, Part 1: Architecture, rev 1.59
Change-Id: I3388007d4448c93bd0dda591c8ca7d1a8dc5306b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-11-19 22:05:06 -07:00
Jeremy Soller
ea848eba56 intel/block/pcie/rtd3: Also implement _PR3
Change-Id: Id7f4373989dffe8c3bc68a034f59a94d2160dd15
Signed-off-by: Jeremy Soller <jeremy@system76.com>
2023-11-19 22:05:06 -07:00
Jeremy Soller
5f3df49cf7 intel/block/pcie/rtd3: ACPI debug messages
Change-Id: Icc4a882ff73f62a134b92f1afb0dc298ea809189
Signed-off-by: Jeremy Soller <jeremy@system76.com>
2023-11-19 22:05:06 -07:00
Tim Crawford
9fa04e13ca submodules: Use absolute paths
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: If03415f80a6028e263e76a9e3cc10df0cde5cc3c
2023-11-19 22:05:06 -07:00
3738 changed files with 15035 additions and 86987 deletions

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@@ -1,228 +1,21 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# clang-format configuration file. Intended for clang-format >= 16.
#
# For more information, see:
#
# https://clang.llvm.org/docs/ClangFormat.html
# https://clang.llvm.org/docs/ClangFormatStyleOptions.html
# https://clang-format-configurator.site/
#
---
Language: Cpp
AccessModifierOffset: -4
AlignAfterOpenBracket: Align
AlignArrayOfStructures: Left
AlignConsecutiveAssignments:
Enabled: false
AcrossEmptyLines: false
AcrossComments: true
AlignCompound: false
PadOperators: true
AlignConsecutiveBitFields:
Enabled: true
AcrossEmptyLines: false
AcrossComments: false
AlignCompound: false
PadOperators: true
AlignConsecutiveDeclarations:
Enabled: false
AcrossEmptyLines: false
AcrossComments: false
AlignCompound: false
PadOperators: true
AlignConsecutiveMacros:
Enabled: true
AcrossEmptyLines: false
AcrossComments: false
AlignCompound: false
PadOperators: true
AlignEscapedNewlines: Left
AlignOperands: Align
AlignTrailingComments:
Kind: Always
OverEmptyLines: 0
AllowAllArgumentsOnNextLine: true
AllowAllParametersOfDeclarationOnNextLine: false
AllowShortBlocksOnASingleLine: Never
AllowShortCaseLabelsOnASingleLine: false
AllowShortEnumsOnASingleLine: true
AllowShortFunctionsOnASingleLine: None
AllowShortIfStatementsOnASingleLine: Never
AllowShortLambdasOnASingleLine: All
AllowShortLoopsOnASingleLine: false
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
AlwaysBreakTemplateDeclarations: MultiLine
# git grep '^#define [^[:space:]]*__.*[^[:space:]]*__attribute__' | grep -v "vendorcode\|payloads\|util" | sed "s|.*:||;s|^#define \([^[:space:]]*__[^([:space:]]*\).*$| - '\1'|" | LC_ALL=C sort -u
AttributeMacros:
- '__aligned'
- '__always_inline'
- '__always_unused'
- '__cpu_driver'
- '__fallthrough'
- '__maybe_unused'
- '__must_check'
- '__noreturn'
- '__packed'
- '__pci_driver'
- '__printf'
- '__weak'
BinPackArguments: true
BinPackParameters: true
BitFieldColonSpacing: Both
BraceWrapping:
AfterCaseLabel: false
AfterClass: false
AfterControlStatement: Never
AfterEnum: false
AfterExternBlock: false
AfterFunction: true
AfterNamespace: true
AfterObjCDeclaration: false
AfterStruct: false
AfterUnion: false
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BeforeElse: false
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IndentBraces: false
SplitEmptyFunction: true
SplitEmptyRecord: true
SplitEmptyNamespace: true
BreakAfterAttributes: Never
BreakAfterJavaFieldAnnotations: false
BreakArrays: false
BreakBeforeBinaryOperators: None
BreakBeforeConceptDeclarations: Always
BreakBeforeBraces: Custom
BreakBeforeInlineASMColon: OnlyMultiline
BreakBeforeTernaryOperators: false
BreakConstructorInitializers: AfterColon
BreakInheritanceList: AfterColon
BreakStringLiterals: false
ColumnLimit: 96
CommentPragmas: '^ IWYU pragma:'
CompactNamespaces: false
ConstructorInitializerIndentWidth: 8
ContinuationIndentWidth: 8
Cpp11BracedListStyle: true
DerivePointerAlignment: false
DisableFormat: false
EmptyLineAfterAccessModifier: Never
EmptyLineBeforeAccessModifier: LogicalBlock
ExperimentalAutoDetectBinPacking: false
FixNamespaceComments: false
# git grep '^#define [^[:space:]]*for_each[^[:space:]]*(' | grep -v "vendorcode\|payloads\|util" | sed "s|.*:||;s|^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$| - '\1'|" | LC_ALL=C sort -u
ForEachMacros:
- 'list_for_each'
# git grep -i '^#define \+if[^[:space:]]*(' | grep -v "vendorcode\|payloads\|util" | sed "s|.*:||;s|^#define \([^[:space:]]*if[^[:space:]]*\)(.*$| - '\1'|I" | grep -v IFIX | LC_ALL=C sort -u
IfMacros:
- 'IF_CHANNEL_POPULATED'
- 'IF_DIMM_POPULATED'
- 'IF_RANK_POPULATED'
- 'IfBit0'
IncludeBlocks: Preserve
IncludeIsMainSourceRegex: ''
IndentAccessModifiers: false
IndentCaseBlocks: false
IndentCaseLabels: false
IndentExternBlock: AfterExternBlock
IndentGotoLabels: false
IndentPPDirectives: None
IndentRequiresClause: true
IndentWidth: 8
IndentWrappedFunctionNames: false
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InsertNewlineAtEOF: true
InsertTrailingCommas: None
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Binary: 0
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JavaScriptQuotes: Leave
JavaScriptWrapImports: true
KeepEmptyLinesAtTheStartOfBlocks: false
LambdaBodyIndentation: Signature
LineEnding: LF
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 1
NamespaceIndentation: None
ObjCBinPackProtocolList: Auto
ObjCBlockIndentWidth: 8
ObjCBreakBeforeNestedBlockParam: true
ObjCSpaceAfterProperty: true
ObjCSpaceBeforeProtocolList: true
PackConstructorInitializers: BinPack
PenaltyBreakAssignment: 10
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PenaltyIndentedWhitespace: 0
PenaltyReturnTypeOnItsOwnLine: 60
PointerAlignment: Right
PPIndentWidth: -1
QualifierAlignment: Left
ReferenceAlignment: Pointer
ReflowComments: false
RemoveBracesLLVM: false
RemoveSemicolon: false
RequiresClausePosition: OwnLine
RequiresExpressionIndentation: OuterScope
SeparateDefinitionBlocks: Leave
ShortNamespaceLines: 1
SortIncludes: Never
SortJavaStaticImport: Before
SortUsingDeclarations: Never
SpaceAfterCStyleCast: false
SpaceAfterLogicalNot: false
SpaceAfterTemplateKeyword: true
SpaceAroundPointerQualifiers: Default
SpaceBeforeAssignmentOperators: true
SpaceBeforeCaseColon: false
SpaceBeforeCpp11BracedList: false
SpaceBeforeCtorInitializerColon: true
SpaceBeforeInheritanceColon: true
SpaceBeforeParens: ControlStatementsExceptControlMacros
SpaceBeforeParensOptions:
AfterControlStatements: true
AfterForeachMacros: false
AfterFunctionDefinitionName: false
AfterFunctionDeclarationName: false
AfterIfMacros: false
AfterOverloadedOperator: false
AfterRequiresInClause: false
AfterRequiresInExpression: false
BeforeNonEmptyParentheses: false
SpaceBeforeRangeBasedForLoopColon: true
SpaceBeforeSquareBrackets: false
SpaceInEmptyBlock: false
SpaceInEmptyParentheses: false
SpacesBeforeTrailingComments: 1
SpacesInAngles: Never
SpacesInConditionalStatement: false
SpacesInContainerLiterals: false
SpacesInCStyleCastParentheses: false
SpacesInLineCommentPrefix:
Minimum: 1
Maximum: 1
SpacesInParentheses: false
SpacesInSquareBrackets: false
Standard: c++17
TabWidth: 8
UseTab: ForContinuationAndIndentation
...
BasedOnStyle: LLVM
Language: Cpp
IndentWidth: 8
UseTab: Always
BreakBeforeBraces: Linux
AllowShortIfStatementsOnASingleLine: false
IndentCaseLabels: false
SortIncludes: false
ContinuationIndentWidth: 8
ColumnLimit: 96
AlwaysBreakBeforeMultilineStrings: true
AllowShortLoopsOnASingleLine: false
AllowShortFunctionsOnASingleLine: false
AlignEscapedNewlinesLeft: false
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AlignAfterOpenBracket: true
SpaceAfterCStyleCast: false
MaxEmptyLinesToKeep: 2
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@@ -9,7 +9,3 @@ charset = utf-8
insert_final_newline = true
end_of_line = lf
trim_trailing_whitespace = true
[*.sh]
indent_style = space
indent_size = 2

1
.gitignore vendored
View File

@@ -9,7 +9,6 @@ defconfig
build/
coreboot-builds/
coreboot-builds*/
generated/
site-local

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@@ -2,4 +2,4 @@
host=review.coreboot.org
port=29418
project=coreboot
defaultbranch=main
defaultbranch=master

2
3rdparty/fsp vendored

2
3rdparty/vboot vendored

View File

@@ -808,7 +808,7 @@ eDP display panel encounters an I2C error, it should print a "cannot read EDID"
message and return an error code. The calling display initialization function
knows that without the EDID there is no way to initialize the display correctly,
so it will also immediately return with an error code without running its
remaining code that would initialize the SoC's display controller. Execution
remaining code that would initialize the SoC's display controller. Exeuction
returns further up the function stack to the mainboard initialization code
which continues booting despite the failed display initialization, since
display functionality is non-essential to the system. (Code is encouraged but

View File

@@ -43,16 +43,6 @@ ships with coreboot and support upstream maintenance for the devices through a
third party, [3mdeb](https://3mdeb.com). They provide current and tested
firmware binaries on [GitHub](https://pcengines.github.io).
### Protectli
[Protectli](https://protectli.com) is dedicated to providing reliable,
cost-effective, and secure computer equipment with coreboot-based firmware
tailored for their hardware. It comes with the [Dasharo](#dasharo)
firmware, maintained by [3mdeb](https://3mdeb.com/). Protectli hardware has
verified support for many popular operating systems, such as Linux distributions,
FreeBSD, and Windows. Support includes Debian, Ubuntu, OPNsense, pfSense,
ProxMox VE, VMware ESXi, Windows 10 and 11, and many more.
### Purism
[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and

View File

@@ -7,10 +7,10 @@ to the point of providing its own custom language.
The overhead of learning this new syntax is (hopefully) offset by its lower
complexity.
The build system is defined in the toplevel `Makefile` and `toolchain.mk`
The build system is defined in the toplevel `Makefile` and `toolchain.inc`
and is supposed to be generic (and is in fact used with a number of other
projects). Project specific configuration should reside in files called
`Makefile.mk`.
`Makefile.inc`.
In general, the build system provides a number of "classes" that describe
various parts of the build. These cover the various build targets in coreboot
@@ -36,7 +36,7 @@ TODO: explain how to create new classes and how to evaluate them.
### subdirs
`subdirs` contains subdirectories (relative to the current directory) that
should also be handled by the build system. The build system expects these
directories to contain a file called `Makefile.mk`.
directories to contain a file called `Makefile.inc`.
Subdirectories are not read at the point where the `subdirs` statement
resides but later, after the current directory is handled (and potentially
@@ -66,7 +66,7 @@ supported options are:
You can use the `add_intermediate` helper to add new post-processing steps for
the final `coreboot.rom` image. For example you can add new files to CBFS by
adding something like this to `site-local/Makefile.mk`
adding something like this to `site-local/Makefile.inc`
```
$(call add_intermediate, add_mrc_data)
@@ -100,4 +100,4 @@ The default implementation just returns `COREBOOT` (the default region) for
all files.
vboot provides its own implementation of `regions-for-file` that can be used
as reference in `src/vboot/Makefile.mk`.
as reference in `src/vboot/Makefile.inc`.

View File

@@ -1,312 +0,0 @@
# coreboot FAQ
## General coreboot questions
### What is coreboot?
coreboot is a free and open software project designed to initialize
computers and embedded systems in a fast, secure, and auditable fashion.
The focus is on minimal hardware initialization: to do only what is
absolutely needed, then pass control to other software (a payload, in
coreboot parlance) in order to boot the operating system securely.
### What is a coreboot payload?
coreboot itself does not deal with boot media such as hard-drives,
SSDs, or USB flash-drives, beyond initializing the underlying hardware.
So in order to actually boot an operating system, another piece of
software which does do those things must be used. coreboot supports
a large number of diverse payloads; see below for more details.
### Is coreboot the same as UEFI?
No. coreboot and UEFI are both system firmware that handle the
initialization of the hardware, but are otherwise not similar.
coreboots goal is to **just** initialize the hardware and exit.
This makes coreboot smaller and simpler, leading to faster boot times,
and making it easier to find and fix bugs. The result is a higher
overall security.
### What's the difference between coreboot and UEFI?
UEFI is actually a firmware specification, not a specific software
implementation. Intel, along with the rest of the Tianocore project,
has released an open-source implementation of the overall framework,
EDK2, but it does not come with hardware support. Most hardware running
UEFI uses a proprietary implementation built on top of EDK2.
coreboot does not implement the UEFI specification, but it can be used to
initialize the system, then launch a UEFI payload such as EDK2 in order
to provide UEFI boot services.
The UEFI specification also defines and allows for many things that are
outside of coreboots scope, including (but not limited to):
* Boot device selection
* Updating the firmware
* A CLI shell
* Network communication
* An integrated setup menu
### Can coreboot boot operating systems that require UEFI?
Yes, but... again, coreboot **just** initializes the hardware. coreboot
itself doesnt load operating systems from storage media other than the
flash chip. Unlike UEFI, coreboot does not, and will not contain a Wi-Fi
driver or communicate directly with any sort of network. That sort of
functionality is not related to hardware initialization.
To boot operating systems that require UEFI, coreboot can be compiled with
EDK2 as the payload. This allows coreboot to perform the hardware init,
with EDK2 supplying the UEFI boot interface and runtime services to
the operating system.
### What non-UEFI payloads does coreboot support?
* SeaBIOS, behaves like a classic BIOS, allowing you to boot operating
systems that rely on the legacy interrupts.
* GRUB can be used as a coreboot payload, and is currently the most
common approach to full disk encryption (FDE).
* A Linux kernel and initramfs stored alongside coreboot in the boot
ROM can also be used as a payload. In this scenario coreboot
initializes hardware, loads Linux from boot ROM into RAM, and
executes it. The embedded Linux environment can look for a target OS
kernel to load from local storage or over a network and execute it
using kexec. This is sometimes called LinuxBoot.
* U-boot, depthcharge, FILO, etc.
Theres [https://doc.coreboot.org/payloads.html](https://doc.coreboot.org/payloads.
html) with a list, although its not complete.
### What does coreboot leave in memory after it's done initializing the hardware?
While coreboot tries to remove itself completely from memory after
finishing, some tables and data need to remain for the OS. coreboot
reserves an area in memory known as CBMEM, to save this data after it
has finished booting. This contains things such as the boot log, tables
that get passed to the payload, SMBIOS, and ACPI tables for the OS.
In addition to CBMEM, on X86 systems, coreboot will typically set up
SMM, which will remain resident after coreboot exits.
## Platforms
### Whats the best coreboot platform for a user?
The choice of the best coreboot platform for a user can vary depending
on their specific needs, preferences, and use cases.
Typically, people who want a system with a minimum of proprietary
firmware are restricted to older systems like the Lenovo X220, or more
expensive, non-x86 solutions like TALOS, from Raptor Engineering.
There are a number of companies selling modern systems, but those all
require more proprietary binaries in addition to coreboot (e.g., Intel
FSP). However, unlike the older ThinkPads, many of these newer devices
use open-source embedded controller (EC) firmware, so there are
tradeoffs with either option.
The coreboot project mantains a list of companies selling machines
which use coreboot on the [website](https://coreboot.org/users.html).
### Whats the best platform for coreboot development?
Similar to the best platform for users, the best platform for
developers very much depends on what a developer is trying to do.
* QEMU is generally the easiest platform for coreboot development, just
because its easy to run anywhere. However, its possible for things
to work properly in QEMU but fail miserably on actual hardware.
While laptops tend to be harder to develop than desktop platforms, a
majority of newer platforms on coreboot tend to be laptops. The
development difficulty is due to a few different factors:
1. The EC (Embedded Controller) is a specialized microcontroller that
typically handles keyboard and sometimes mouse input for a laptop.
It also controls many power management functions such as fans, USB-C
power delivery, etc. ECs run mainboard-specific firmware, which is
typically undocumented.
2. ThinkPads (X230, 30-series, 20-series, T430, T540, T520). Sandy
Bridge and Ivy Bridge are well-supported. Some may have
difficult-to-reach SPI flash chips. Boards with two flash chips (e.g.
30-series ThinkPads) are harder to externally reflash as one needs to
make sure the non-targeted flash chip remains disabled at all times.
The X230 is notoriously sensitive to external reflashing issues.
3. Laptops often lack a convenient method to obtain firmware boot logs.
One can use EHCI debug on older systems and Chromebook-specific
solutions for Chromebooks, but one often has to resort to flashconsole
(writing coreboot logs to the flash chip where coreboot resides). On
the other hand, several desktop mainboards still have a RS-232 serial
port.
Some of the easiest physical systems to use for coreboot development
are Chromebooks. Newer Chromebooks allow for debug without opening the
case. Look for SuzyQ Cables or SuzyQables or instructions on how to
build one. These cables only work on a specific port in a specific
orientation. Google [supplies
specifications](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/master/docs/ccd.md#SuzyQ-SuzyQable)
for these cables.
### What platforms does coreboot support?
The most accurate way to determine what systems coreboot supports is by
browsing the src/mainboard tree or running “make menuconfig” and going
through the “Mainboard” submenu. You can also search Gerrit to see if
there are any unmerged ports for your board.
There is also the board status page
([https://coreboot.org/status/board-status.html](https://coreboot.org/status/board-status.html)),
however this does not currently show supported board variants.
## coreboot Development
### Can coreboot be ported to [this board]?
The best way to determine if coreboot can be ported to a system is to
see if the processor and chipset is supported. The next step is to see
whether the system is locked to the proprietary firmware which comes
with the board.
Intel Platforms:
* coreboot only supports a few northbridges (back when northbridges
were on a separate package), and there's next to no support for
"server" platforms (multi-socket and similar things). Here's a list
of more recent supported Intel processors:
* Alder Lake (2021 - Core Gen 12)
* Apollo Lake (2016 - Atom)
* Baytrail (2014 - Atom)
* Braswell (2016 - Atom)
* Broadwell (2014 - Core Gen 5)
* Comet Lake (2019 - Core Gen 10)
* Cannon Lake (2018 - Core Gen 8/9)
* Denverton (2017)
* Elkhart lake (2021 - Atom)
* Haswell (2013 - Core Gen 4)
* Ivy Bridge (2012 - Core Gen 3)
* Jasper Lake (2021 - Atom)
* Kaby Lake (2016 - Core Gen 7/8)
* Meteor Lake (2023 - Gen 1 Ultra-mobile)
* Sandy Bridge (2011 - Core Gen 2)
* Sky Lake (2015 - Core Gen 6)
* Tiger Lake (2020 - Core Gen 11)
* Whiskey Lake (2018 - Core Gen 8)
* Intel Boot Guard is a security feature which tries to prevent loading
unauthorized firmware by the mainboard. If supported by the platform,
and the platform is supported by intelmetool, you should check if Boot
Guard is enabled. If it is, then getting coreboot to run will be
difficult or impossible even if it is ported. You can run
`intelmetool -b` on supported platforms to see if Boot Guard is
enabled (although it can fail because it wants to probe the ME
beforehand).
AMD Ryzen-based platforms:
* The AMD platforms Ryzen-based platforms unfortunately are currently
not well supported outside of the Chromebooks (and AMD reference
boards) currently in the tree.
The responsible teams are trying to fix this, but currently it's
**very** difficult to do a new port. Recent supported SoCs:
* Stoney Ridge
* Picasso
* Cezanne
* Mendocino
* Phoenix
General notes:
* Check the output of `lspci` to determine what processor/chipset
family your system has. Processor/chipset support is the most
important to determine if a board can be ported.
* Check the output of `superiotool` to see if it detects the Super I/O
on the system. You can also check board schematics and/or boardviews
if you can find them, or physically look at the mainboard for a chip
from one of the common superio vendors.
* Check what EC your system has (mostly applicable to laptops, but some
desktops have EC-like chips). You will likely need to refer to the
actual board or schematics/boardviews for this. Physical observation
is the most accurate identification procedure; software detection can
then be used to double-check if the chip is correct, but one should
not rely on software detection alone to identify an EC.
### How do I port coreboot to [this board]?
A critical piece for anyone attempting to do a board port is to make
sure that you have a method to recover your system from a failed flash.
We need an updated motherboard porting guide, but currently the guide
on the [wiki](https://www.coreboot.org/Motherboard_Porting_Guide) looks
to be the best reference.
At the moment, the best answer to this question is to ask for help on
one of the [various community
forums](https://doc.coreboot.org/community/forums.html).
### What about the Intel ME?
There seems to be a lot of FUD about what the ME can and cant do.
coreboot currently does not have a clear recommendation on how to
handle the ME. We understand that there are serious concerns about the
ME, and would like to flatly recommend removing as much as possible,
however modifying the ME can cause serious stability issues.
Additionally, coreboot and the Intel ME are completely separate entites
which in many cases simply happen to occupy the same flash chip. It is
not necessary to run coreboot to modify the ME, and running coreboot
does not imply anything about the ME's operational state.
#### A word of caution about the modifying ME
Messing with the ME firmware can cause issues, and this is outside the
scope of the coreboot project.
If you do decide to modify the ME firmware, please make sure coreboot
works **before** messing with it. Even if the vendor boot firmware
works when the ME isn't operating normally, it's possible that coreboot
doesn't handle it the same way and something breaks. If someone asks
for help with coreboot and we think the ME state may be a factor, we'll
ask them to try reproducing the issue with the ME running normally to
reduce the number of variables involved. This is especially important
when flashing coreboot for the first time, as it's best for newbies to
start with small steps: start by flashing coreboot to the BIOS region
and leaving the remaining regions untouched, then tinker around with
coreboot options (e.g. other payloads, bootsplash, RAM overclock...),
or try messing with the ME firmware **without changing coreboot**.
Most people don't understand the implications of messing with the ME
firmware, especially the use of `me_cleaner`. We admit that we don't
know everything about the ME, but we try to understand it as much as
possible. The ME is designed to operate correctly with the HAP (or
AltMeDisable) bit set, and it will gracefully enter a debug state (not
normal, but not an error). However, when using `me_cleaner` to remove
parts of the ME firmware, the ME will often end up in an error state
because parts of its FW are missing. It is known that removing some of
these parts ([`EFFS` and `FCRS` on Cougar Point,
c.f.](https://review.coreboot.org/c/coreboot/+/27798/6/src/mainboard/asus/p8h61-m_lx/Kconfig#63))
can cause problems. We do not know whether the state the ME ends up in
after applying `me_cleaner` is as secure as the state the ME goes to
when only the HAP bit is set: the removed FW modules could contain
steps to lock down important settings for security reasons.
To sum up, **we do not recommend messing with the ME firmware**. But if
you have to, please use `ifdtool` to set the HAP bit initially before
progressing to `me_cleaner` if necessary.

View File

@@ -7,4 +7,3 @@
* [Writing Documentation](writing_documentation.md)
* [Setting up GPIOs](gpio.md)
* [Adding devices to a device tree](devicetree.md)
* [Frequently Asked Questions](faq.md)

View File

@@ -69,6 +69,9 @@ These variables are typically set in the makefiles or on the make command line.
These variables were added to Kconfig specifically for coreboot and are not
included in the Linux version.
- KCONFIG_STRICT=value. Define to enable warnings as errors. This is enabled
in coreboot, and should not be changed.
- KCONFIG_NEGATIVES=value. Define to show negative values in the autoconf.h file
(build/config.h). This is enabled in coreboot, and should not be changed.
@@ -99,9 +102,6 @@ included in the Linux version.
- KCONFIG_SPLITCONFIG=”directory name for individual SYMBOL.h files”.
coreboot sets this to $(obj)/config.
- KCONFIG_WERROR=value. Define to enable warnings as errors. This is enabled
in coreboot, and should not be changed.
#### Used only for make menuconfig
- MENUCONFIG_MODE=single_menu. Set to "single_menu" to enable. All other
values disable the option. This makes submenus appear below the menu option
@@ -963,7 +963,7 @@ variable. This is not set in coreboot, which uses the default CONFIG_ prefix
for all of its symbols.
The coreboot makefile forces the config.h file to be included into all coreboot
C files. This is done in Makefile.mk on the compiler command line using the
C files. This is done in Makefile.inc on the compiler command line using the
“-include $(obj)/config.h” command line option.
Example of various symbol types in the config.h file:
@@ -1160,6 +1160,10 @@ saved .config file. As always, a 'select' statement overrides any specified
- coreboot has added the glob operator '*' for the 'source' keyword.
- coreboots Kconfig always defines variables except for strings. In other
Kconfig implementations, bools set to false/0/no are not defined.
- coreboots version of Kconfig adds the KCONFIG_STRICT environment variable to
error out if there are any issues in the Kconfig files. In the Linux kernel,
Kconfig will generate a warning, but will still output an updated .config or
config.h file.
## Kconfig Editor Highlighting

View File

@@ -1,52 +0,0 @@
# Operating our services
## Mailing list moderation
Our [mailing lists] experience the same barrage of spam mails than any
other email address. We do have a spam filter in front of it, and
since the lists require registration, spam ends up in the moderation
queue. But not only spam ends up there, sometimes users send inquiries
without registering first. It's a custom of the project to let these
through, so that such emails can be discussed. This requires manual
intervention.
This section describes the tasks related to mailing list management.
### Registration
To participate in mailing list moderation, you need to become a list
moderator or owner. This is up for the existing owners to handle and
if you want to contribute in that area, it might be best to bring it
up at the leadership meeting.
After gaining leadership approval, list admins can add you to the
appropriate group in the [mailing list backend] by selecting the list,
then User / group-name, and add your email address there.
### Regular tasks
Most of our lists are auto-subscribing, so users can register
themselves and finish the process by responding to the double-opt-in
email. Some lists are manually managed though. The [mailing list
backend] shows the number of open subscription requests for these
lists on the mailing list's main page.
It also provides a list of held messages, where they can be accepted,
rejected or dropped. Spam should be dropped, that's clear. Emails with
huge attachments (e.g. screenshots) should be rejected, which gives
you an opportunity to explain the reason (in case of large
attachments, something like "Please re-send without attachments, offer
the files through some other mechanism please: Our emails are
distributed to hundreds of readers, and sending the files to everybody
is inconsiderate of traffic and storage constraints.")
Legit emails (often simple requests of the form "is this or that
supported") can be accepted, which means they'll be sent out.
If you notice recurring spam sources (e.g. marketers) you can put them
on the [global ban list] to filter them out across all lists. It takes
entries in regular expression format.
[mailing lists]: https://mail.coreboot.org/hyperkitty/
[mailing list backend]: https://mail.coreboot.org/postorius/
[global ban list]: https://mail.coreboot.org/postorius/bans/

View File

@@ -5,7 +5,7 @@ This section contains documentation about our infrastructure
## Services
* [Project services](services.md)
* [Administrator's handbook](admin.md)
## Jenkins builders and builds
* [Setting up Jenkins build machines](builders.md)

View File

@@ -9,7 +9,7 @@ updates using an A/B partitioning scheme once enabled.
## Enabling vboot
You can enable [vboot] in Kconfig's *Security* section. Besides a verified
boot you can also enable a measured boot by setting
`CONFIG_TPM_MEASURED_BOOT`. Both options need a working TPM, which is
`CONFIG_VBOOT_MEASURED_BOOT`. Both options need a working TPM, which is
present on all recent Lenovo devices.
## Updating and recovery

View File

@@ -222,4 +222,4 @@ and [u-root] as initramfs.
[All about u-root]: https://github.com/linuxboot/book/tree/master/u-root
[u-root]: https://u-root.org/
[ChromeOS VPD]: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md
[src/mainboard/ocp/deltalake/vpd.h]: https://review.coreboot.org/plugins/gitiles/coreboot/+/HEAD/src/mainboard/ocp/deltalake/vpd.h
[src/mainboard/ocp/deltalake/vpd.h]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/src/mainboard/ocp/deltalake/vpd.h

View File

@@ -1,282 +0,0 @@
Upcoming release - coreboot 24.02
========================================================================
The 24.02 release is scheduled for February 19, 2024. The next release,
which will be 24.05, is scheduled for mid-May.
The coreboot project is happy to announce our next release for February
2024. Over the past three months, our contributors have focused on
refining the coreboot codebase, generally prioritizing cleanup and
quality enhancements. We extend our gratitude to all the contributors
who have dedicated their time and expertise. Thank you for your
invaluable contributions to this vital phase of maintenance and
optimization.
### Release number format update
The previous release was the last to use the incrementing 4.xx release
name scheme. For this and future releases, coreboot has switched to a
Year.Month.Sub-version naming scheme. As such, the next release,
scheduled for May of 2024 will be numbered 24.05, with the sub-version
of 00 implied. If we need to do a fix or incremental release, we'll
append the values .01, .02 and so on to the initial release value.
### The master branch is being deleted
The coreboot project changed from master to main roughly 6 months ago,
and has been keeping the two branches in sync since then to ease the
transition. As of this release, we are getting rid of the master branch
completely. Please make sure any scripts you're using that reference the
'master' branch have been switched to 'main'.
Significant or interesting changes
----------------------------------
### acpi: Add Arm IO Remapping Table structures
Input Output Remapping Table (IORT) represents the IO topology of an Arm
based system.
Document number: ARM DEN 0049E.e, Sep 2022
### acpi: Add PPTT support
This patch adds code to generate Processor Properties Topology Tables
(PPTT) compliant to the ACPI 6.4 specification.
- The 'acpi_get_pptt_topology' hook is mandatory once ACPI_PPTT is
selected. Its purpose is to return a pointer to a topology tree,
which describes the relationship between CPUs and caches. The hook
can be provided by, for example, mainboard code.
Background: We are currently working on mainboard code for qemu-sbsa and
Neoverse N2. Both require a valid PPTT table. Patch was tested against
the qemu-sbsa board.
### acpi: Add support for WDAT table
This commit lays the groundwork for implementing the ACPI WDAT (Watchdog
Action Table) table specification. The WDAT is a special ACPI table
introduced by Microsoft that describes the watchdog for the OS.
Platforms that need to implement the WDAT table must describe the
hardware watchdog management operations as described in the
specification. See “Links to ACPI-Related Documents”
(http://uefi.org/acpi) under the heading “Watchdog Action Table”.
### lib/jpeg: Replace decoder with Wuffs' implementation
To quote its repo[0]: Wuffs is a memory-safe programming language (and a
standard library written in that language) for Wrangling Untrusted File
Formats Safely. Wrangling includes parsing, decoding and encoding.
It compiles its library, written in its own language, to a C/C++ source
file that can then be used independently without needing support for the
language. That library is now imported to src/vendorcode/wuffs/.
This change modifies our linters to ignore that directory because it's
supposed to contain the wuffs compiler's result verbatim.
Nigel Tao provided an initial wrapper around wuffs' jpeg decoder that
implements our JPEG API. I further changed it a bit regarding data
placement, dropped stuff from our API that wasn't ever used, or isn't
used anymore, and generally made it fit coreboot a bit better. Features
are Nigel's, bugs are mine.
This commit also adapts our jpeg fuzz test to work with the modified
API. After limiting it to deal only with approximately screen sized
inputs, it fuzzed for 25 hours CPU time without a single hang or crash.
This is a notable improvement over running the test with our old decoder
which crashes within a minute.
Finally, I tried the new parser with a pretty-much-random JPEG file I
got from the internet, and it just showed it (once the resolution
matched), which is also a notable improvement over the old decoder which
is very particular about the subset of JPEG it supports.
In terms of code size, a QEmu build's ramstage increases
from 128060 bytes decompressed (64121 bytes after LZMA)
to 172304 bytes decompressed (82734 bytes after LZMA).
[0] https://github.com/google/wuffs
Additional coreboot changes
---------------------------
* Rename Makefiles from .inc to .mk to better identify them
* SPI: Add GD25LQ255E and IS25WP256D chip support
* device: Add support for multiple PCI segment groups
* device: Drop unused multiple downstream link support
* device: Rename bus and link_list to upstream and downstream
* Updated devicetree files for modern Intel platforms to use chipset.cb
* Updated xeon-sp to use the coreboot allocator
Changes to external resources
-----------------------------
### Toolchain updates
* Add buildgcc support for Apple M1/M2 devices
* crossgcc: Upgrade GCC from 11.4.0 to 13.2.0
* util/crossgcc: Update CMake from 3.26.4 to 3.27.7
* util/kconfig: Uprev to Linux 6.7 kconfig
### Git submodule pointers
* /3rdparty/amd_blobs: Update from commit id e4519efca7 to 64cdd7c8ef
(5 commits)
* /3rdparty/arm-trusted-firmware: Update from commit id 88b2d81345 to
17bef2248d (701 commits)
* /3rdparty/fsp: Update from commit id 481ea7cf0b to 507ef01cce (16 commits)
* /3rdparty/intel-microcode: Update from commit id 6788bb07eb to
ece0d294a2 (1 commits)
* /3rdparty/vboot: Update from commit id 24cb127a5e to 3d37d2aafe (121
commits)
### External payloads
* payload/grub2: Update from 2.06 to 2.12
* payload/seabios: Update from 1.16.2 to 1.16.3
Platform Updates
----------------
### Added mainboards:
* Google: Dita
* Google: Xol
* Lenovo: ThinkPad X230 eDP Mod (2K/FHD)
### Removed Mainboards
* Google -> Primus4ES
Statistics from the 4.22 to the 24.02 release
--------------------------------------------
* Total Commits: 814
* Average Commits per day: 8.65
* Total lines added: 105203
* Average lines added per commit: 129.24
* Number of patches adding more than 100 lines: 46
* Average lines added per small commit: 41.34
* Total lines removed: 16505
* Average lines removed per commit: 20.28
* Total difference between added and removed: 88698
* Total authors: 111
* New authors: 19
Significant Known and Open Issues
---------------------------------
* AMD chromebooks will not currently work with the signed vboot image.
## Issues from the coreboot bugtracker: https://ticket.coreboot.org/
### coreboot-wide or architecture-wide issues
```eval_rst
+-----+-----------------------------------------------------------------+
| # | Subject |
+=====+=================================================================+
| 522 | 'region_overlap()' issues due to an integer overflow. |
+-----+-----------------------------------------------------------------+
| 519 | make gconfig - could not find glade file |
+-----+-----------------------------------------------------------------+
| 518 | make xconfig - g++: fatal error: no input files |
+-----+-----------------------------------------------------------------+
```
### Payload-specific issues
```eval_rst
+-----+-----------------------------------------------------------------+
| # | Subject |
+=====+=================================================================+
| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled |
+-----+-----------------------------------------------------------------+
| 496 | Missing malloc check in libpayload |
+-----+-----------------------------------------------------------------+
| 484 | No USB keyboard support with secondary payloads |
+-----+-----------------------------------------------------------------+
| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
+-----+-----------------------------------------------------------------+
```
### Platform-specific issues
```eval_rst
+-----+-----------------------------------------------------------------+
| # | Subject |
+=====+=================================================================+
| 517 | lenovo x230 boot stuck with connected external monitor |
+-----+-----------------------------------------------------------------+
| 509 | SD Card hotplug not working on Apollo Lake |
+-----+-----------------------------------------------------------------+
| 507 | Windows GPU driver fails on Google guybrush & skyrim boards |
+-----+-----------------------------------------------------------------+
| 506 | APL/GML don't boot OS when CPU microcode included "from tree" |
+-----+-----------------------------------------------------------------+
| 505 | Harcuvar CRB - 15 of 16 cores present in the operating system |
+-----+-----------------------------------------------------------------+
| 499 | T440p - EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled |
+-----+-----------------------------------------------------------------+
| 495 | Stoney Chromebooks not booting PSPSecureOS |
+-----+-----------------------------------------------------------------+
| 478 | X200 booting Linux takes a long time with TSC |
+-----+-----------------------------------------------------------------+
| 474 | X200s crashes after graphic init with 8GB RAM |
+-----+-----------------------------------------------------------------+
| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb |
+-----+-----------------------------------------------------------------+
| 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit |
+-----+-----------------------------------------------------------------+
| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
+-----+-----------------------------------------------------------------+
| 448 | Thinkpad T440P ACPI Battery Value Issues |
+-----+-----------------------------------------------------------------+
| 446 | Optiplex 9010 No Post |
+-----+-----------------------------------------------------------------+
| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz) |
+-----+-----------------------------------------------------------------+
| 427 | x200: Two battery charging issues |
+-----+-----------------------------------------------------------------+
| 412 | x230 reboots on suspend |
+-----+-----------------------------------------------------------------+
| 393 | T500 restarts rather than waking up from suspend |
+-----+-----------------------------------------------------------------+
| 350 | I225 PCIe device not detected on Harcuvar |
+-----+-----------------------------------------------------------------+
```
coreboot Links and Contact Information
--------------------------------------
* Main Web site: https://www.coreboot.org
* Downloads: https://coreboot.org/downloads.html
* Source control: https://review.coreboot.org
* Documentation: https://doc.coreboot.org
* Issue tracker: https://ticket.coreboot.org/projects/coreboot
* Donations: https://coreboot.org/donate.html

View File

@@ -1,7 +1,7 @@
coreboot 4.22 & 4.22.01 releases
Upcoming release - coreboot 4.22
========================================================================
The next release is planned for the 19th of February, 2024
The next release is planned for mid-February, 2024
These notes cover the latest updates and improvements to coreboot over
the past three months. A big thank you to the returning contributors as
@@ -11,17 +11,6 @@ releases, this one reflects a commitment to open source innovation,
security enhancements, and expanding hardware support.
### 4.22.01 release
The week between tagging a release and announcing it publicly is used
to test the tagged version and make sure everything is working as we
expect. This is done instead of freezing the tree and doing release
candidates before the release.
For the 4.22 release cycle we found an uninitialized variable error on
the sandybridge/ivybridge platforms and rolled that into the 4.22.01
release package.
### coreboot version naming update
This release is the last release to use the incrementing 4.xx release
@@ -29,14 +18,14 @@ name scheme. For future releases, coreboot is switching to a
Year.Month.Sub-version naming scheme. As such, the next release,
scheduled for February of 2024 will be numbered 24.02, with the
sub-version of 00 implied. If we need to do a fix or future release of
the 24.02 release, we'll append the values .01, .02 and so on to the
the 24.02 release, well append the values .01, .02 and so on to the
initial release value.
### coreboot default branch update
Immediately after the 4.21 release, the coreboot project changed the
default git branch from 'master' to 'main'. For the first couple of
default git branch from master to main. For the first couple of
months after the change, The master branch was synced with the main
branch several times a day, allowing people time to update any scripts.
As of 2023-11-01, the sync rate has slowed to once a week. This will
@@ -166,7 +155,7 @@ GPU drivers will fail to load with a code 43 error in Device Manager.
Additional coreboot changes
---------------------------
* Move all 'select' statements from Kconfig.name files to Kconfig
* Move all select statements from Kconfig.name files to Kconfig
* acpigen now generates variable-length PkgLength fields instead of a
fixed 3-byte size to improve compatibility and to bring it in line
with IASL
@@ -246,15 +235,15 @@ Platform Updates
Statistics from the 4.21 to the 4.22 release
--------------------------------------------
* Total Commits: 977
* Average Commits per day: 10.98
* Total lines added: 62993
* Average lines added per commit: 64.48
* Number of patches adding more than 100 lines: 60
* Average lines added per small commit: 37.55
* Total lines removed: 30042
* Average lines removed per commit: 30.75
* Total difference between added and removed: 32951
* Total Commits: 885
* Average Commits per day: 10.72
* Total lines added: 58276
* Average lines added per commit: 65.85
* Number of patches adding more than 100 lines: 54
* Average lines added per small commit: 37.77
* Total lines removed: 27790
* Average lines removed per commit: 31.40
* Total difference between added and removed: 30486
* Total authors: 135
* New authors: 14

View File

@@ -3,7 +3,7 @@
## Upcoming release
Please add to the release notes as changes are added:
* [24.02 - February 2024](coreboot-24.02-relnotes.md)
* [4.22 - November 2023](coreboot-4.22-relnotes.md)
The [checklist] contains instructions to ensure that a release covers all
important things and provides a reliable format for tarballs, branch
@@ -15,7 +15,6 @@ important is taken care of.
## Previous releases
* [4.22 - November 2023](coreboot-4.22-relnotes.md)
* [4.21 - August 2023](coreboot-4.21-relnotes.md)
* [4.20.1 - May 2023](coreboot-4.20.1-relnotes.md)
* [4.19 - January 2023](coreboot-4.19-relnotes.md)

View File

@@ -114,7 +114,7 @@ defconfig pointing to your [software-name] generated File.
as part of your software's build process. For example in form of a
Makefile target.
2. Change src/sbom/Makefile.mk (in order to know where to find the
2. Change src/sbom/Makefile.inc (in order to know where to find the
CoSWID/SWID/uSWID file) as well as the Makefile in coreboot which
builds said software. For example for GRUB2 that could mean to add a
Makefile target in payloads/external/GRUB2/Makefile.

View File

@@ -1,8 +1,7 @@
# vboot-enabled devices
## AMD
- Birman for Phoenix SoC using FSP
- Birman for Phoenix SoC using openSIL
- Birman for Phoenix SoC
- Birman for Glinda SoC
- Chausie
- Majolica
@@ -38,7 +37,6 @@
- Agah
- Anahera
- Anahera4ES
- Anraggar
- Aurash
- Banshee
- Brask
@@ -47,7 +45,6 @@
- Craaskov
- Constitution
- Crota
- Dochi
- Felwinter
- Gaelin
- Gimble
@@ -65,11 +62,11 @@
- Moli
- Nivviks
- Nereid
- Nokris
- Omnigul
- Osiris
- Pirrha
- Primus
- Primus4ES
- Pujjo
- Quandiso
- Redrix
@@ -86,7 +83,9 @@
- Yaviks
- Yavilla
- Zydron
- Xol
- Nokris
- Dochi
- Anraggar
- Butterfly (HP Pavilion Chromebook 14)
- Cherry
- Dojo
@@ -221,18 +220,18 @@
- Sand (Acer Chromebook 15 CB515-1HT/1H)
- Snappy (HP Chromebook x360 11 G1 EE)
- Coral
- Deku
- Deku4ES
- Karis
- Karis4ES
- Ovis
- Ovis4ES
- Rex 0
- Rex EC ISH
- Rex4ES
- Rex4ES EC ISH
- Screebo
- Screebo4ES
- Karis
- Karis4ES
- Rex EC ISH
- Ovis
- Ovis4ES
- Deku
- Deku4ES
- Rex4ES
- Rex4ES EC ISH
- Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
- Sarien (Dell Latitude 5400 Chromebook Enterprise)
- Crystaldrift

View File

@@ -68,7 +68,7 @@ specific IBB measurements without hard-coding them.
#### Runtime Data
* CBFS data which changes by external input dynamically. Never stays the same.
* It is identified by TPM_MEASURED_BOOT_RUNTIME_DATA kconfig option and
* It is identified by VBOOT_MEASURED_BOOT_RUNTIME_DATA kconfig option and
measured into a different PCR (PCR_RUNTIME_DATA kconfig option, 3 by default)
in order to avoid PCR pre-calculation issues.

View File

@@ -247,13 +247,13 @@ tests/lib/string-test and tests/device/i2c-test:
│ ├── include
│ │ ├── mocks <- mock headers, which replace original headers
│ │
│ ├── Makefile.mk <- top Makefile for unit tests subsystem
│ ├── Makefile.inc <- top Makefile for unit tests subsystem
│ ├── lib
│ │ ├── Makefile.mk
│ │ ├── Makefile.inc
│ │ ├── string-test.c <- test code for src/lib/string.c
│ │ │
│ ├── device
│ │ ├── Makefile.mk
│ │ ├── Makefile.inc
│ ├── i2c-test.c
├── build

View File

@@ -96,8 +96,8 @@ suffix `-test` to the UUT name when creating a new test harness file.
be registered with the coreboot unit testing infrastructure.
```
Every directory under `tests/` should contain a Makefile.mk, similar to
what can be seen under the `src/`. Register a new test in Makefile.mk,
Every directory under `tests/` should contain a Makefile.inc, similar to
what can be seen under the `src/`. Register a new test in Makefile.inc,
by __appending__ test name to the `tests-y` variable.
```eval_rst
@@ -285,7 +285,7 @@ stimulate UUT as required without changing the source code.
coreboot unit test infrastructure supports overriding of functions at
link time. This is as simple as adding a `name_of_function` to be
mocked into <test_name>-mocks variable in Makefile.mk. The result is
mocked into <test_name>-mocks variable in Makefile.inc. The result is
that the test's implementation of that function is called instead of
coreboot's.

View File

@@ -144,6 +144,7 @@ from the local git repository for auditing or release `Bash`
Does not show variants. `Shell`
* _ucode_h_to_bin.sh_ - Microcode conversion tool `Bash`
* _update_submodules_ - Check all submodules for updates `Bash`
* __showdevicetree__ - Compile and dump the device tree `C`
* __spdtool__ - Dumps SPD ROMs from a given blob to separate files
using known patterns and reserved bits. Useful for analysing firmware
that holds SPDs on boards that have soldered down DRAM. `python`

View File

@@ -1,175 +0,0 @@
GNU LESSER GENERAL PUBLIC LICENSE
Version 2.1, February 1999
Copyright (C) 1991, 1999 Free Software Foundation, Inc.
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.
[This is the first released version of the Lesser GPL. It also counts as the successor of the GNU Library Public License, version 2, hence the version number 2.1.]
Preamble
The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public Licenses are intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users.
This license, the Lesser General Public License, applies to some specially designated software packages--typically libraries--of the Free Software Foundation and other authors who decide to use it. You can use it too, but we suggest you first think carefully about whether this license or the ordinary General Public License is the better strategy to use in any particular case, based on the explanations below.
When we speak of free software, we are referring to freedom of use, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish); that you receive source code or can get it if you want it; that you can change the software and use pieces of it in new free programs; and that you are informed that you can do these things.
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END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Libraries
If you develop a new library, and you want it to be of the greatest possible use to the public, we recommend making it free software that everyone can redistribute and change. You can do so by permitting redistribution under these terms (or, alternatively, under the terms of the ordinary General Public License).
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Copyright (C) year name of author
This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License along with this library; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA Also add information on how to contact you by electronic and paper mail.
You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the library, if necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in
the library `Frob' (a library for tweaking knobs) written
by James Random Hacker.
signature of Ty Coon, 1 April 1990
Ty Coon, President of Vice
That's all there is to it!

View File

@@ -349,7 +349,7 @@ GOOGLE REX MAINBOARDS
M: Subrata Banik <subratabanik@google.com>
M: Tarun Tuli <tstuli@gmail.com>
M: Kapil Porwal <kapilporwal@google.com>
M: Jakub Czapiga <czapiga@google.com>
M: Jakub Czapiga <jacz@semihalf.com>
M: Eran Mitrani <mitrani@google.com>
M: Dinesh Gehlot <digehlot@google.com>
S: Maintained
@@ -359,7 +359,6 @@ GOOGLE BRYA MAINBOARDS
M: Subrata Banik <subratabanik@google.com>
M: Nick Vaccaro <nvaccaro@chromium.org>
M: Eric Lai <ericllai@google.com>
M: Kapil Porwal <kapilporwal@google.com>
S: Maintained
F: src/mainboard/google/brya/
@@ -887,7 +886,7 @@ INTEL METEORLAKE SOC
M: Subrata Banik <subratabanik@google.com>
M: Tarun Tuli <tstuli@gmail.com>
M: Kapil Porwal <kapilporwal@google.com>
M: Jakub Czapiga <czapiga@google.com>
M: Jakub Czapiga <jacz@semihalf.com>
M: Eran Mitrani <mitrani@google.com>
M: Dinesh Gehlot <digehlot@google.com>
S: Maintained
@@ -896,7 +895,6 @@ F: src/soc/intel/meteorlake/
INTEL ALDERLAKE SOC
M: Subrata Banik <subratabanik@google.com>
M: Nick Vaccaro <nvaccaro@chromium.org>
M: Kapil Porwal <kapilporwal@google.com>
S: Maintained
F: src/soc/intel/alderlake/
@@ -941,14 +939,10 @@ M: Johnny Lin <Johnny_Lin@wiwynn.com>
M: Tim Chu <Tim.Chu@quantatw.com>
M: Arthur Heymans <arthur@aheymans.xyz>
M: Christian Walter <christian.walter@9elements.com>
M: Shuo Liu <shuo.liu@intel.com>
M: Patrick Rudolph <patrick.rudolph@9elements.com>
M: Lean Sheng Tan <sheng.tan@9elements.com>
S: Supported
F: src/soc/intel/xeon_sp/
F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp/
F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp/
F: src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/
MEDIATEK SOCS
M: Hung-Te Lin <hungte@chromium.org>
@@ -1186,7 +1180,7 @@ S: Maintained
F: src/drivers/i2c/tas5825m/
TESTS
M: Jakub Czapiga <czapiga@google.com>
M: Jakub Czapiga <jacz@semihalf.com>
S: Maintained
F: tests/
F: payloads/libpayload/tests/

View File

@@ -23,34 +23,27 @@ COREBOOT_EXPORTS += top src srck obj objutil objk
DOTCONFIG ?= $(top)/.config
KCONFIG_CONFIG = $(DOTCONFIG)
KCONFIG_AUTOADS := $(obj)/cb-config.ads
KCONFIG_RUSTCCFG := $(obj)/cb-config.rustcfg
KCONFIG_AUTOHEADER := $(obj)/config.h
KCONFIG_AUTOCONFIG := $(obj)/auto.conf
KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd
KCONFIG_SPLITCONFIG := $(obj)/config/
KCONFIG_TRISTATE := $(obj)/tristate.conf
KCONFIG_NEGATIVES := 1
KCONFIG_WERROR := 1
KCONFIG_WARN_UNKNOWN_SYMBOLS := 1
KCONFIG_STRICT := 1
KCONFIG_PACKAGE := CB.Config
KCONFIG_MAKEFILE_REAL ?= $(objk)/Makefile.real
COREBOOT_EXPORTS += KCONFIG_CONFIG KCONFIG_AUTOHEADER KCONFIG_AUTOCONFIG
COREBOOT_EXPORTS += KCONFIG_DEPENDENCIES KCONFIG_SPLITCONFIG KCONFIG_TRISTATE
COREBOOT_EXPORTS += KCONFIG_NEGATIVES
ifeq ($(filter %config,$(MAKECMDGOALS)),)
COREBOOT_EXPORTS += KCONFIG_WERROR
endif
COREBOOT_EXPORTS += KCONFIG_WARN_UNKNOWN_SYMBOLS
COREBOOT_EXPORTS += KCONFIG_NEGATIVES KCONFIG_STRICT
COREBOOT_EXPORTS += KCONFIG_AUTOADS KCONFIG_PACKAGE
COREBOOT_EXPORTS += KCONFIG_RUSTCCFG
# Make does not offer a recursive wildcard function, so here's one:
rwildcard=$(wildcard $1$2) $(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2))
SYMLINK_LIST = $(call rwildcard,site-local/,symlink.txt)
# Directory containing the toplevel Makefile.mk
# directory containing the toplevel Makefile.inc
TOPLEVEL := .
CONFIG_SHELL := sh
@@ -102,7 +95,7 @@ help_coreboot help::
# This include must come _before_ the pattern rules below!
# Order _does_ matter for pattern rules.
include $(srck)/Makefile.mk
include $(srck)/Makefile.inc
# The cases where we don't need fully populated $(obj) lists:
# 1. when no .config exists
@@ -153,12 +146,11 @@ ifeq ($(NOCOMPILE),1)
HOSTCC ?= $(if $(shell type gcc 2>/dev/null),gcc,cc)
HOSTCXX ?= g++
include $(TOPLEVEL)/Makefile.mk
include $(TOPLEVEL)/payloads/Makefile.mk
include $(TOPLEVEL)/util/testing/Makefile.mk
-include $(TOPLEVEL)/site-local/Makefile.mk
include $(TOPLEVEL)/Makefile.inc
include $(TOPLEVEL)/payloads/Makefile.inc
include $(TOPLEVEL)/util/testing/Makefile.inc
-include $(TOPLEVEL)/site-local/Makefile.inc
include $(TOPLEVEL)/tests/Makefile.mk
include $(TOPLEVEL)/tests/Makefile.inc
printall real-all:
@echo "Error: Trying to build, but NOCOMPILE is set." >&2
@echo " Please file a bug with the following information:"
@@ -199,7 +191,7 @@ endif
export LANG LC_ALL TZ SOURCE_DATE_EPOCH
ifneq ($(UNIT_TEST),1)
include toolchain.mk
include toolchain.inc
endif
strip_quotes = $(strip $(subst ",,$(subst \",,$(1))))
@@ -277,7 +269,7 @@ src-to-ali=\
$(subst .$(1),,\
$(filter %.ads %.adb,$(2)))))))))
# Clean -y variables, include Makefile.mk & Makefile.inc
# Clean -y variables, include Makefile.inc
# Add paths to files in X-y to X-srcs
# Add subdirs-y to subdirs
includemakefiles= \
@@ -296,12 +288,9 @@ includemakefiles= \
# For each path in $(subdirs) call includemakefiles
# Repeat until subdirs is empty
# TODO: Remove Makefile.inc support
evaluate_subdirs= \
$(eval cursubdirs:=$(subdirs)) \
$(eval subdirs:=) \
$(foreach dir,$(cursubdirs), \
$(eval $(call includemakefiles,$(dir)/Makefile.mk))) \
$(foreach dir,$(cursubdirs), \
$(eval $(call includemakefiles,$(dir)/Makefile.inc))) \
$(if $(subdirs),$(eval $(call evaluate_subdirs)))
@@ -310,11 +299,11 @@ evaluate_subdirs= \
subdirs:=$(TOPLEVEL)
postinclude-hooks :=
# Don't iterate through Makefiles under src/ when building tests
# Don't iterate through Makefile.incs under src/ when building tests
ifneq ($(UNIT_TEST),1)
$(eval $(call evaluate_subdirs))
else
include $(TOPLEVEL)/tests/Makefile.mk
include $(TOPLEVEL)/tests/Makefile.inc
endif
ifeq ($(FAILBUILD),1)

View File

@@ -59,36 +59,22 @@ COREBOOT_EXPORTS += CCACHE_EXTRAFILES
#######################################################################
# root rule to resolve if in build mode (ie. configuration exists)
real-target: $(obj)/config.h coreboot files_added show_coreboot show_notices
real-target: $(obj)/config.h coreboot files_added
coreboot: $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool $(obj)/ifwitool $(obj)/cse_fpt $(obj)/cse_serger
# This target can be used to run scripts or additional targets
# after the build completes by creating a target named 'build_complete::'
.PHONY: build_complete
build_complete:: | coreboot
# This target can be used to run rules after all files were added to CBFS,
# for example to process FMAP regions or the entire image.
.PHONY: files_added
files_added:: | build_complete
# This target should come just before the show_notices target. If there
# are no notices, the build should finish with the text of what was just
# built.
.PHONY: show_coreboot
show_coreboot: | files_added
$(CBFSTOOL) $(obj)/coreboot.rom print -r $(subst $(spc),$(comma),$(all-regions))
# This target can be used in site local to run scripts or additional
# targets after the build completes by creating a Makefile.inc in the
# site-local directory with a target named 'build_complete::'
build_complete:: coreboot
printf "\nBuilt %s (%s)\n" $(MAINBOARDDIR) $(CONFIG_MAINBOARD_PART_NUMBER)
if [ -f "$(CCACHE_STATSLOG)" ]; then \
printf "\nccache statistics\n"; \
$(CCACHE) --show-log-stats -v; \
fi
# This is intended to run at the *very end* of the build to show warnings
# notices and the like. If another target needs to be added, add it
# BEFORE this target.
.PHONY: show_notices
show_notices:: | show_coreboot
# This target can be used to run rules after all files were added to CBFS,
# for example to process FMAP regions or the entire image.
files_added:: build_complete
#######################################################################
# our phony targets
@@ -498,7 +484,6 @@ CFLAGS_common += -Wdangling-else -Wmissing-include-dirs
CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie
ifeq ($(CONFIG_COMPILER_GCC),y)
CFLAGS_common += -Wold-style-declaration
# Don't add these GCC specific flags when running scan-build
ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
CFLAGS_common += -Wno-packed-not-aligned
@@ -768,7 +753,7 @@ gitconfig:
install-git-commit-clangfmt:
cp util/scripts/prepare-commit-msg.clang-format .git/hooks/prepare-commit-msg
include util/crossgcc/Makefile.mk
include util/crossgcc/Makefile.inc
.PHONY: tools
tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER) $(AMDFWREAD)
@@ -1158,7 +1143,7 @@ FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE))
endif # ifeq ($(CONFIG_ARCH_X86),y)
$(obj)/fmap.fmd: $(top)/Makefile.mk $(DEFAULT_FLASHMAP) $(obj)/config.h
$(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h
sed -e "s,##ROM_BASE##,$(FMAP_ROM_ADDR)," \
-e "s,##ROM_SIZE##,$(FMAP_ROM_SIZE)," \
-e "s,##BIOS_BASE##,$(FMAP_BIOS_BASE)," \
@@ -1256,6 +1241,7 @@ endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE
@printf " CBFSLAYOUT $(subst $(obj)/,,$(@))\n\n"
$(CBFSTOOL) $@ layout
@printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n"
$(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions))
ifeq ($(CONFIG_CBFS_VERIFICATION),y)
line=$$($(CBFSTOOL) $@ print -kv 2>/dev/null | grep -F '[CBFS VERIFICATION (COREBOOT)]') ;\
if ! printf "$$line" | grep -q 'fully valid'; then \

View File

@@ -30,7 +30,7 @@ Code reviews are done in [the project's Gerrit
instance](https://review.coreboot.org/).
The code may be browsed via [coreboot's Gitiles
instance](https://review.coreboot.org/plugins/gitiles/coreboot/+/HEAD).
instance](https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master).
The coreboot project also maintains a
[mirror](https://github.com/coreboot/coreboot) of the project on github.
@@ -140,10 +140,9 @@ These uncopyrightable files include:
These may be required to exist as part of the build process but are
not needed for the particular project.
- Configuration files either in binary or text form. Examples would be
files such as .vbt files describing graphics configuration, .apcb
files containing configuration parameters for AMD firmware binaries,
and spd files as binary .spd or text \*spd\*.hex representing memory
chip configuration.
files such as .vbt files describing graphics configuration, spd files
as binary .spd or text \*spd\*.hex representing memory chip
configuration.
- Machine-generated files containing version numbers, dates, hash
values or other "non-creative" content.

View File

@@ -8,3 +8,4 @@ CONFIG_DEBUG_PIRQ=y
CONFIG_DEBUG_MALLOC=y
CONFIG_DEBUG_BOOT_STATE=y
CONFIG_DEBUG_ADA_CODE=y
CONFIG_CPU_QEMU_X86_PARALLEL_MP=y

View File

@@ -1,3 +1,5 @@
CONFIG_VENDOR_EMULATION=y
CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y
CONFIG_CPU_QEMU_X86_PARALLEL_MP=y
CONFIG_CPU_QEMU_X86_TSEG_SMM=y
CONFIG_CPU_QEMU_X86_SMMLOADERV2=y

View File

@@ -10,6 +10,7 @@ CONFIG_ANY_TOOLCHAIN=y
# ChromeOS
CONFIG_CHROMEOS=y
CONFIG_HAS_RECOVERY_MRC_CACHE=y
CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN=y
# Event Logging
CONFIG_CMOS_POST=y
@@ -33,5 +34,5 @@ CONFIG_CONSOLE_SERIAL=y
CONFIG_CONSOLE_SERIAL_115200=y
# CONFIG_DRIVERS_UART_8250IO is not set
# GLK specific setting to auto select all the correct settings.
CONFIG_INTEL_LPSS_UART_FOR_CONSOLE=y
CONFIG_UART_DEBUG=y
CONFIG_NO_BOOTBLOCK_CONSOLE=y

View File

@@ -1,4 +1,4 @@
CONFIG_VENDOR_GOOGLE=y
CONFIG_BOARD_GOOGLE_OCTOPUS=y
CONFIG_CONSOLE_SPI_FLASH=y
# CONFIG_TPM_MEASURED_BOOT is not set
# CONFIG_VBOOT_MEASURED_BOOT is not set

View File

@@ -0,0 +1,7 @@
CONFIG_USE_BLOBS=y
CONFIG_VENDOR_INTEL=y
CONFIG_INTEL_GMA_VBT_FILE="3rdparty/fsp/CoffeeLakeFspBinPkg/SampleCode/Vbt/Vbt.bin"
CONFIG_BOARD_INTEL_COFFEELAKE_RVP11=y
CONFIG_USE_CANNONLAKE_FSP_CAR=y
CONFIG_RUN_FSP_GOP=y
CONFIG_PAYLOAD_NONE=y

View File

@@ -6,5 +6,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_PXE=y
CONFIG_BUILD_IPXE=y
CONFIG_PXE_ROM_ID="10ec,8168"
# CONFIG_IPXE_SERIAL_CONSOLE is not set
# CONFIG_PXE_SERIAL_CONSOLE is not set
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

View File

@@ -8,5 +8,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_PXE=y
CONFIG_BUILD_IPXE=y
CONFIG_PXE_ROM_ID="8086,157b"
# CONFIG_IPXE_SERIAL_CONSOLE is not set
# CONFIG_PXE_SERIAL_CONSOLE is not set
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

View File

@@ -8,5 +8,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_PXE=y
CONFIG_BUILD_IPXE=y
CONFIG_PXE_ROM_ID="8086,1539"
# CONFIG_IPXE_SERIAL_CONSOLE is not set
# CONFIG_PXE_SERIAL_CONSOLE is not set
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

View File

@@ -8,5 +8,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_PXE=y
CONFIG_BUILD_IPXE=y
CONFIG_PXE_ROM_ID="8086,1539"
# CONFIG_IPXE_SERIAL_CONSOLE is not set
# CONFIG_PXE_SERIAL_CONSOLE is not set
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

View File

@@ -8,5 +8,5 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_PXE=y
CONFIG_BUILD_IPXE=y
CONFIG_PXE_ROM_ID="8086,1539"
# CONFIG_IPXE_SERIAL_CONSOLE is not set
# CONFIG_PXE_SERIAL_CONSOLE is not set
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
menu "Payload"
config PAYLOAD_NONE
@@ -82,14 +80,13 @@ config COMPRESSED_PAYLOAD_LZ4
endchoice
config PAYLOAD_OPTIONS
string "Additional cbfstool options"
string
default ""
help
Additional cbfstool options for the payload
config PAYLOAD_IS_FLAT_BINARY
bool "Payload is a flat binary"
default n
def_bool n
help
Add the payload to cbfs as a flat binary type instead of as an
elf payload

View File

@@ -50,7 +50,7 @@ print-repo-info-payloads:
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
ifeq ($(CONFIG_PAYLOAD_NONE),y)
show_notices:: warn_no_payload
files_added:: warn_no_payload
endif
warn_no_payload:

View File

@@ -70,7 +70,7 @@ $(obj)/config.h:
$(shell mkdir -p $(objk)/lxdialog $(KCONFIG_SPLITCONFIG))
include $(srck)/Makefile.mk
include $(srck)/Makefile.inc
.PHONY: $(PHONY) prepare all real-all defaultbuild

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
if PAYLOAD_BOOTBOOT
config PAYLOAD_FILE

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
config PAYLOAD_BOOTBOOT
bool "BOOTBOOT"
depends on ARCH_X86 || ARCH_ARM64

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
if PAYLOAD_FILO
choice

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
config PAYLOAD_FILO
bool "FILO"
depends on ARCH_X86

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
config PAYLOAD_BUILD_GRUB2
bool
@@ -17,7 +15,7 @@ choice
default GRUB2_STABLE
config GRUB2_STABLE
bool "2.12"
bool "2.06"
help
Stable GRUB2 version

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
config PAYLOAD_GRUB2
bool "GRUB2"
depends on ARCH_X86 || ARCH_ARM

View File

@@ -1,9 +1,9 @@
TAG-$(CONFIG_GRUB2_MASTER)=origin/HEAD
TAG-$(CONFIG_GRUB2_REVISION)=$(CONFIG_GRUB2_REVISION_ID)
TAG-$(CONFIG_GRUB2_STABLE)=grub-2.12
TAG-$(CONFIG_GRUB2_STABLE)=grub-2.06
NAME-$(CONFIG_GRUB2_MASTER)=HEAD
NAME-$(CONFIG_GRUB2_REVISION)=$(CONFIG_GRUB2_REVISION_ID)
NAME-$(CONFIG_GRUB2_STABLE)=2.12
NAME-$(CONFIG_GRUB2_STABLE)=2.06
project_git_repo=https://git.savannah.gnu.org/git/grub.git/
project_dir=grub2

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
if MEMTEST_SECONDARY_PAYLOAD
comment "Memtest86+"

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
config PAYLOAD_BUILD_SEABIOS
bool
@@ -17,7 +15,7 @@ choice
default SEABIOS_STABLE
config SEABIOS_STABLE
bool "1.16.3"
bool "1.16.2"
help
Stable SeaBIOS version
config SEABIOS_MASTER

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
config PAYLOAD_SEABIOS
bool "SeaBIOS"
depends on ARCH_X86

View File

@@ -1,5 +1,5 @@
TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
TAG-$(CONFIG_SEABIOS_STABLE)=a6ed6b701f0a57db0569ab98b0661c12a6ec3ff8
TAG-$(CONFIG_SEABIOS_STABLE)=ea1b7a0733906b8425d948ae94fba63c32b1d425
TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)
project_git_repo=https://review.coreboot.org/seabios.git

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
if PAYLOAD_UBOOT
config PAYLOAD_SPECIFIC_OPTIONS

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
config PAYLOAD_UBOOT
bool "U-Boot"
depends on ARCH_X86

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
if COREDOOM_SECONDARY_PAYLOAD
config COREDOOM_WAD_FILE

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
if PAYLOAD_DEPTHCHARGE
choice

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
config PAYLOAD_DEPTHCHARGE
bool "Depthcharge"
depends on CHROMEOS

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
if PAYLOAD_EDK2
config PAYLOAD_FILE

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
config PAYLOAD_EDK2
bool "edk2 payload"
depends on ARCH_X86 || ARCH_ARM64

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
if PAYLOAD_LINUX
config PAYLOAD_FILE

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
config PAYLOAD_LINUX
bool "A Linux payload"
depends on ARCH_X86 || ARCH_ARM || ARCH_RISCV

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
##
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.

View File

@@ -56,7 +56,7 @@ export KCONFIG_NEGATIVES := 1
export KBUILD_KCONFIG := Kconfig
export CONFIG_ := CONFIG_LP_
# directory containing the toplevel Makefile.mk
# directory containing the toplevel Makefile.inc
TOPLEVEL := .
CONFIG_LP_SHELL := sh
@@ -103,7 +103,7 @@ endif
# This include must come _before_ the pattern rules below!
# Order _does_ matter for pattern rules.
include $(srck)/Makefile.mk
include $(srck)/Makefile.inc
include $(HAVE_DOTCONFIG)
@@ -127,7 +127,7 @@ ARCH-$(CONFIG_LP_ARCH_MOCK) := mock
# 3. when make distclean is run
# 4. when make help% or make clean% is run
# 5. when make %-test or make %-tests or make %coverage-report is run
# Don't waste time on reading all Makefiles in these cases
# Don't waste time on reading all Makefile.incs in these cases
ifeq ($(strip $(HAVE_DOTCONFIG)),)
NOCOMPILE := 1
endif
@@ -159,8 +159,8 @@ $(xcompile): $(top)/../../util/xcompile/xcompile
\mv -f $@.tmp $@ 2> /dev/null
ifeq ($(NOCOMPILE),1)
include $(TOPLEVEL)/Makefile.mk
include $(TOPLEVEL)/tests/Makefile.mk
include $(TOPLEVEL)/Makefile.inc
include $(TOPLEVEL)/tests/Makefile.inc
real-all: config
else
@@ -285,7 +285,7 @@ add-special-class= \
$(eval $(1):=) \
$(eval special-classes+=$(1))
# Clean -y variables, include Makefile.mk
# Clean -y variables, include Makefile.inc
# Add paths to files in X-y to X-srcs
# Add subdirs-y to subdirs
includemakefiles= \
@@ -308,7 +308,7 @@ evaluate_subdirs= \
$(eval cursubdirs:=$(subdirs)) \
$(eval subdirs:=) \
$(foreach dir,$(cursubdirs), \
$(eval $(call includemakefiles,$(dir)/Makefile.mk))) \
$(eval $(call includemakefiles,$(dir)/Makefile.inc))) \
$(if $(subdirs),$(eval $(call evaluate_subdirs)))
# collect all object files eligible for building or run unit-tests
@@ -316,7 +316,7 @@ ifneq ($(UNIT_TEST),1)
subdirs:=$(TOPLEVEL)
$(eval $(call evaluate_subdirs))
else
include $(TOPLEVEL)/tests/Makefile.mk
include $(TOPLEVEL)/tests/Makefile.inc
endif
# Converts one or more source file paths to the corresponding build/ paths.

View File

@@ -120,16 +120,23 @@ $(obj)/head.o: $(obj)/arch/$(ARCHDIR-y)/head.head.o.o
install: real-target
printf " INSTALL $(DESTDIR)/libpayload/lib\n"
install -m 755 -d $(DESTDIR)/libpayload/lib
install -m 644 $(library-targets) $(DESTDIR)/libpayload/lib/
for lib in $(library-targets); do \
install -m 644 $$lib $(DESTDIR)/libpayload/lib/; \
done
install -m 644 arch/$(ARCHDIR-y)/libpayload.ldscript $(DESTDIR)/libpayload/lib/
install -m 755 -d $(DESTDIR)/libpayload/lib/$(ARCHDIR-y)
install -m 644 $(obj)/head.o $(DESTDIR)/libpayload/lib/$(ARCHDIR-y)
printf " INSTALL $(DESTDIR)/libpayload/include\n"
install -m 755 -d $(DESTDIR)/libpayload/include
find include -type d -exec install -m755 -d $(DESTDIR)/libpayload/{} \;
find include -type f -exec install -m644 {} $(DESTDIR)/libpayload/{} \;
cd $(coreboottop)/src/commonlib/bsd && find include -type d -exec install -m755 -d $(abspath $(DESTDIR))/libpayload/{} \;
cd $(coreboottop)/src/commonlib/bsd && find include -type f -exec install -m644 {} $(abspath $(DESTDIR))/libpayload/{} \;
for file in `find include -name *.h -type f`; do \
install -m 755 -d $(DESTDIR)/libpayload/`dirname $$file`; \
install -m 644 $$file $(DESTDIR)/libpayload/$$file; \
done
for file in `find $(coreboottop)/src/commonlib/bsd/include -name *.h -type f`; do \
dest_file=$$(realpath --relative-to=$(coreboottop)/src/commonlib/bsd/ $$file); \
install -m 755 -d "$(DESTDIR)/libpayload/`dirname $$dest_file`"; \
install -m 644 "$$file" "$(DESTDIR)/libpayload/$$dest_file"; \
done
install -m 644 $(obj)/libpayload-config.h $(DESTDIR)/libpayload/include
$(foreach item,$(includes), \
install -m 755 -d $(DESTDIR)/libpayload/include/$(call extract_nth,2,$(item)); \

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
##
##
## Copyright (c) 2012 Google Inc.

View File

@@ -56,4 +56,4 @@ ENDPROC(_entry)
1:
.word cb_header_ptr
2:
.word _estack
.word _stack

View File

@@ -40,35 +40,29 @@ SECTIONS
_start = .;
.text : {
_text = .;
*(.text._entry)
*(.text)
*(.text.*)
_etext = .;
}
.rodata : {
_rodata = .;
*(.rodata)
*(.rodata.*)
_erodata = .;
}
.data : {
_data = .;
*(.data)
*(.data.*)
_edata = .;
}
_edata = .;
.bss : {
_bss = .;
*(.sbss)
*(.sbss.*)
*(.bss)
*(.bss.*)
*(COMMON)
_ebss = .;
/* Stack and heap */
@@ -78,10 +72,10 @@ SECTIONS
. = ALIGN(16);
_eheap = .;
_stack = .;
_estack = .;
. += CONFIG_LP_STACK_SIZE;
. = ALIGN(16);
_estack = .;
_stack = .;
}
_end = .;

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
##
##
## Copyright (c) 2012 Google Inc.

View File

@@ -55,4 +55,4 @@ ENDPROC(_entry)
1:
.quad cb_header_ptr
2:
.quad _estack
.quad _stack

View File

@@ -40,35 +40,29 @@ SECTIONS
_start = .;
.text : {
_text = .;
*(.text._entry)
*(.text)
*(.text.*)
_etext = .;
}
.rodata : {
_rodata = .;
*(.rodata)
*(.rodata.*)
_erodata = .;
}
.data : {
_data = .;
*(.data)
*(.data.*)
_edata = .;
}
_edata = .;
.bss : {
_bss = .;
*(.sbss)
*(.sbss.*)
*(.bss)
*(.bss.*)
*(COMMON)
_ebss = .;
/* Stack and heap */
@@ -78,10 +72,10 @@ SECTIONS
. = ALIGN(16);
_eheap = .;
_stack = .;
_estack = .;
. += CONFIG_LP_STACK_SIZE;
. = ALIGN(16);
_estack = .;
_stack = .;
}
_end = .;

View File

@@ -41,14 +41,7 @@ static unsigned int max_tables;
static uint64_t *xlat_addr;
static int free_idx;
/*
* We refer to the section ".bss.ttb_buffer" in the linker script for ChromeOS's depthcharge
* payload. Please DO NOT change the section name without discussing with us.
* Please contact: jwerner@chromium.org or yich@chromium.org
*/
static uint8_t ttb_buffer[TTB_DEFAULT_SIZE] __aligned(GRANULE_SIZE)
__section(".bss.ttb_buffer");
static uint8_t ttb_buffer[TTB_DEFAULT_SIZE] __attribute__((aligned(GRANULE_SIZE)));
static const char * const tag_to_string[] = {
[TYPE_NORMAL_MEM] = "normal",
@@ -581,6 +574,8 @@ static struct mmu_memrange *_mmu_add_fb_range(
prop.type = TYPE_DMA_MEM;
/* make sure to allocate a size of multiple of GRANULE_SIZE */
size = ALIGN_UP(size, GRANULE_SIZE);
prop.size = size;
prop.lim_excl = MIN_64_BIT_ADDR;
prop.align = MB_SIZE;
@@ -638,9 +633,6 @@ static void mmu_add_fb_range(struct mmu_ranges *mmu_ranges)
if (!fb_size)
return;
/* make sure to allocate a size of multiple of GRANULE_SIZE */
fb_size = ALIGN_UP(fb_size, GRANULE_SIZE);
/* framebuffer address has been set already, so just add it as DMA */
if (framebuffer->physical_address) {
if (mmu_add_memrange(mmu_ranges,

View File

@@ -1,5 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
##
##
## Copyright (c) 2012 Google Inc.

View File

@@ -73,7 +73,7 @@ _init:
/* Store current stack pointer and set up new stack. */
movl %esp, %eax
movl $_estack, %esp
movl $_stack, %esp
pushl %eax
/* Enable special x86 functions if present. */

View File

@@ -39,35 +39,29 @@ SECTIONS
_start = .;
.text : {
_text = .;
*(.text._entry)
*(.text)
*(.text.*)
_etext = .;
}
.rodata : {
_rodata = .;
*(.rodata)
*(.rodata.*)
_erodata = .;
}
.data : {
_data = .;
*(.data)
*(.data.*)
_edata = .;
}
_edata = .;
.bss : {
_bss = .;
*(.sbss)
*(.sbss.*)
*(.bss)
*(.bss.*)
*(COMMON)
_ebss = .;
/* Stack and heap */
@@ -77,10 +71,10 @@ SECTIONS
. = ALIGN(16);
_eheap = .;
_stack = .;
_estack = .;
. += CONFIG_LP_STACK_SIZE;
. = ALIGN(16);
_estack = .;
_stack = .;
}
_end = .;

View File

@@ -1,2 +1,2 @@
CONFIG_LP_ARCH_MOCK=y
CONFIG_LP_ARCH_MOCK_BIG_ENDIAN=n
CONFIG_LP_ARCH_BIG_ENDIAN=n

View File

@@ -32,7 +32,7 @@
#include <arch/lib_helpers.h>
#include <libpayload.h>
uint64_t timer_hz(void)
uint32_t timer_hz(void)
{
return raw_read_cntfrq_el0();
}

View File

@@ -33,8 +33,10 @@
#include <assert.h>
#include <libpayload.h>
uint64_t timer_hz(void)
uint32_t timer_hz(void)
{
/* libc/time.c currently requires all timers to be at least 1MHz. */
assert(CONFIG_LP_TIMER_GENERIC_HZ >= 1000000);
return CONFIG_LP_TIMER_GENERIC_HZ;
}

View File

@@ -35,9 +35,10 @@
#include <arch/rdtsc.h>
#include <assert.h>
uint64_t timer_hz(void)
uint32_t timer_hz(void)
{
return (uint64_t)lib_sysinfo.cpu_khz * 1000;
assert(UINT32_MAX / 1000 >= lib_sysinfo.cpu_khz);
return lib_sysinfo.cpu_khz * 1000;
}
uint64_t timer_raw_value(void)

View File

@@ -30,7 +30,7 @@
#define _COREBOOT_TABLES_H
#include <arch/types.h>
#include <commonlib/bsd/ipchksum.h>
#include <ipchksum.h>
#include <stdint.h>
enum {

View File

@@ -0,0 +1,39 @@
/*
*
* Copyright (c) 2012 The ChromiumOS Authors.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef __IPCHKSUM_H__
#define __IPCHKSUM_H__
/**
* @defgroup ipchecksum IP checksum functions
* @{
*/
unsigned short ipchksum(const void *ptr, unsigned long nbytes);
/** @} */
#endif

View File

@@ -48,12 +48,12 @@
#include <commonlib/bsd/elog.h>
#include <commonlib/bsd/fmap_serialized.h>
#include <commonlib/bsd/helpers.h>
#include <commonlib/bsd/ipchksum.h>
#include <commonlib/bsd/mem_chip_info.h>
#include <ctype.h>
#include <die.h>
#include <endian.h>
#include <fmap.h>
#include <ipchksum.h>
#include <kconfig.h>
#include <stddef.h>
#include <stdio.h>
@@ -519,7 +519,7 @@ void lib_sysinfo_get_memranges(struct memrange **ranges,
/* Timer functions. */
/* Defined by each architecture. */
uint64_t timer_hz(void);
uint32_t timer_hz(void);
uint64_t timer_raw_value(void);
uint64_t timer_us(uint64_t base);
/* Generic. */

View File

@@ -137,7 +137,6 @@ void print_malloc_map(void);
void init_dma_memory(void *start, u32 size);
int dma_initialized(void);
int dma_coherent(const void *ptr);
void dma_allocator_range(void **start_out, size_t *size_out);
static inline void *xmalloc_work(size_t size, const char *file,
const char *func, int line)

View File

@@ -28,7 +28,7 @@
##
libc-$(CONFIG_LP_LIBC) += malloc.c printf.c console.c string.c
libc-$(CONFIG_LP_LIBC) += memory.c ctype.c lib.c libgcc.c
libc-$(CONFIG_LP_LIBC) += memory.c ctype.c ipchecksum.c lib.c libgcc.c
libc-$(CONFIG_LP_LIBC) += rand.c time.c exec.c
libc-$(CONFIG_LP_LIBC) += readline.c getopt_long.c sysinfo.c
libc-$(CONFIG_LP_LIBC) += args.c
@@ -47,5 +47,4 @@ endif
ifeq ($(CONFIG_LP_LIBC),y)
libc-srcs += $(coreboottop)/src/commonlib/bsd/elog.c
libc-srcs += $(coreboottop)/src/commonlib/bsd/gcd.c
libc-srcs += $(coreboottop)/src/commonlib/bsd/ipchksum.c
endif

View File

@@ -122,7 +122,7 @@ permute_args(int panonopt_start, int panonopt_end, int opt_end,
*/
nnonopts = panonopt_end - panonopt_start;
nopts = opt_end - panonopt_end;
ncycle = gcd(nnonopts, nopts);
ncycle = gcd32(nnonopts, nopts);
cyclelen = (opt_end - panonopt_start) / ncycle;
for (i = 0; i < ncycle; i++) {

View File

@@ -0,0 +1,52 @@
/*
*
* It has originally been taken from the FreeBSD project.
*
* Copyright (c) 2001 Charles Mott <cm@linktel.net>
* Copyright (c) 2008 coresystems GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <libpayload.h>
unsigned short ipchksum(const void *vptr, unsigned long nbytes)
{
int sum, oddbyte;
const unsigned short *ptr = vptr;
sum = 0;
while (nbytes > 1) {
sum += *ptr++;
nbytes -= 2;
}
if (nbytes == 1) {
oddbyte = 0;
((u8 *) & oddbyte)[0] = *(u8 *) ptr;
((u8 *) & oddbyte)[1] = 0;
sum += oddbyte;
}
sum = (sum >> 16) + (sum & 0xffff);
sum += (sum >> 16);
return (~sum);
}

View File

@@ -123,18 +123,6 @@ int dma_coherent(const void *ptr)
return !dma_initialized() || (dma->start <= ptr && dma->end > ptr);
}
/* Get the range of memory that can be allocated by the dma allocator. */
void dma_allocator_range(void **start_out, size_t *size_out)
{
if (dma_initialized()) {
*start_out = dma->start;
*size_out = dma->end - dma->start;
} else {
*start_out = NULL;
*size_out = 0;
}
}
/* Find free block of size >= len */
static hdrtype_t volatile *find_free_block(int len, struct memory_type *type)
{

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