mb/system76: Enable S0ix support but prefer S3

Enable S0ix support but continue using S3 by default as it is not
tested on most boards. TGL-U boards continue to only use S0ix as S3 is
not supported on them.

Change-Id: Idc881d30009e3ef170e5430596652548aa434fda
Signed-off-by: Tim Crawford <tcrawford@system76.com>

src/mainboard/system76/addw1/devicetree.cb

@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"
 

src/mainboard/system76/adl/devicetree.cb

@@ -11,6 +11,10 @@ chip soc/intel/alderlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 	# Enable C6 DRAM
 	register "enable_c6dram" = "1"
 

src/mainboard/system76/bonw14/devicetree.cb

@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"
 

src/mainboard/system76/cml-u/devicetree.cb

@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "SaGv" = "SaGv_Enabled"
 	register "enable_c6dram" = "1"

src/mainboard/system76/gaze15/devicetree.cb

@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"
 

src/mainboard/system76/oryp5/devicetree.cb

@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"
 

src/mainboard/system76/oryp6/devicetree.cb

@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"
 

src/mainboard/system76/rpl/devicetree.cb

@@ -11,6 +11,10 @@ chip soc/intel/alderlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 	# Enable C6 DRAM
 	register "enable_c6dram" = "1"
 

src/mainboard/system76/tgl-h/devicetree.cb

@@ -12,6 +12,10 @@ chip soc/intel/tigerlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # CPU (soc/intel/tigerlake/cpu.c)
 	# Power limits
 	register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{

src/mainboard/system76/whl-u/devicetree.cb

@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "SaGv" = "SaGv_Enabled"
 	register "enable_c6dram" = "1"