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system76-4
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system76
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b57f87fb9a | ||
|
ec1a880c51 | ||
|
193e9e8529 | ||
|
b558758554 | ||
|
a56ff9087b | ||
|
58a5374d5f | ||
|
61f22cff59 | ||
|
4c4d1948ef |
249
.clang-format
249
.clang-format
@@ -1,21 +1,228 @@
|
||||
BasedOnStyle: LLVM
|
||||
Language: Cpp
|
||||
IndentWidth: 8
|
||||
UseTab: Always
|
||||
BreakBeforeBraces: Linux
|
||||
AllowShortIfStatementsOnASingleLine: false
|
||||
IndentCaseLabels: false
|
||||
SortIncludes: false
|
||||
ContinuationIndentWidth: 8
|
||||
ColumnLimit: 96
|
||||
AlwaysBreakBeforeMultilineStrings: true
|
||||
AllowShortLoopsOnASingleLine: false
|
||||
AllowShortFunctionsOnASingleLine: false
|
||||
AlignEscapedNewlinesLeft: false
|
||||
AlignTrailingComments: true
|
||||
AllowAllParametersOfDeclarationOnNextLine: false
|
||||
AlignAfterOpenBracket: true
|
||||
SpaceAfterCStyleCast: false
|
||||
MaxEmptyLinesToKeep: 2
|
||||
BreakBeforeBinaryOperators: NonAssignment
|
||||
BreakStringLiterals: false
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
# clang-format configuration file. Intended for clang-format >= 16.
|
||||
#
|
||||
# For more information, see:
|
||||
#
|
||||
# https://clang.llvm.org/docs/ClangFormat.html
|
||||
# https://clang.llvm.org/docs/ClangFormatStyleOptions.html
|
||||
# https://clang-format-configurator.site/
|
||||
#
|
||||
|
||||
---
|
||||
Language: Cpp
|
||||
AccessModifierOffset: -4
|
||||
AlignAfterOpenBracket: Align
|
||||
AlignArrayOfStructures: Left
|
||||
AlignConsecutiveAssignments:
|
||||
Enabled: false
|
||||
AcrossEmptyLines: false
|
||||
AcrossComments: true
|
||||
AlignCompound: false
|
||||
PadOperators: true
|
||||
AlignConsecutiveBitFields:
|
||||
Enabled: true
|
||||
AcrossEmptyLines: false
|
||||
AcrossComments: false
|
||||
AlignCompound: false
|
||||
PadOperators: true
|
||||
AlignConsecutiveDeclarations:
|
||||
Enabled: false
|
||||
AcrossEmptyLines: false
|
||||
AcrossComments: false
|
||||
AlignCompound: false
|
||||
PadOperators: true
|
||||
AlignConsecutiveMacros:
|
||||
Enabled: true
|
||||
AcrossEmptyLines: false
|
||||
AcrossComments: false
|
||||
AlignCompound: false
|
||||
PadOperators: true
|
||||
AlignEscapedNewlines: Left
|
||||
AlignOperands: Align
|
||||
AlignTrailingComments:
|
||||
Kind: Always
|
||||
OverEmptyLines: 0
|
||||
AllowAllArgumentsOnNextLine: true
|
||||
AllowAllParametersOfDeclarationOnNextLine: false
|
||||
AllowShortBlocksOnASingleLine: Never
|
||||
AllowShortCaseLabelsOnASingleLine: false
|
||||
AllowShortEnumsOnASingleLine: true
|
||||
AllowShortFunctionsOnASingleLine: None
|
||||
AllowShortIfStatementsOnASingleLine: Never
|
||||
AllowShortLambdasOnASingleLine: All
|
||||
AllowShortLoopsOnASingleLine: false
|
||||
AlwaysBreakAfterDefinitionReturnType: None
|
||||
AlwaysBreakAfterReturnType: None
|
||||
AlwaysBreakBeforeMultilineStrings: false
|
||||
AlwaysBreakTemplateDeclarations: MultiLine
|
||||
|
||||
# git grep '^#define [^[:space:]]*__.*[^[:space:]]*__attribute__' | grep -v "vendorcode\|payloads\|util" | sed "s|.*:||;s|^#define \([^[:space:]]*__[^([:space:]]*\).*$| - '\1'|" | LC_ALL=C sort -u
|
||||
AttributeMacros:
|
||||
- '__aligned'
|
||||
- '__always_inline'
|
||||
- '__always_unused'
|
||||
- '__cpu_driver'
|
||||
- '__fallthrough'
|
||||
- '__maybe_unused'
|
||||
- '__must_check'
|
||||
- '__noreturn'
|
||||
- '__packed'
|
||||
- '__pci_driver'
|
||||
- '__printf'
|
||||
- '__weak'
|
||||
BinPackArguments: true
|
||||
BinPackParameters: true
|
||||
BitFieldColonSpacing: Both
|
||||
BraceWrapping:
|
||||
AfterCaseLabel: false
|
||||
AfterClass: false
|
||||
AfterControlStatement: Never
|
||||
AfterEnum: false
|
||||
AfterExternBlock: false
|
||||
AfterFunction: true
|
||||
AfterNamespace: true
|
||||
AfterObjCDeclaration: false
|
||||
AfterStruct: false
|
||||
AfterUnion: false
|
||||
BeforeCatch: false
|
||||
BeforeElse: false
|
||||
BeforeLambdaBody: false
|
||||
BeforeWhile: false
|
||||
IndentBraces: false
|
||||
SplitEmptyFunction: true
|
||||
SplitEmptyRecord: true
|
||||
SplitEmptyNamespace: true
|
||||
BreakAfterAttributes: Never
|
||||
BreakAfterJavaFieldAnnotations: false
|
||||
BreakArrays: false
|
||||
BreakBeforeBinaryOperators: None
|
||||
BreakBeforeConceptDeclarations: Always
|
||||
BreakBeforeBraces: Custom
|
||||
BreakBeforeInlineASMColon: OnlyMultiline
|
||||
BreakBeforeTernaryOperators: false
|
||||
BreakConstructorInitializers: AfterColon
|
||||
BreakInheritanceList: AfterColon
|
||||
BreakStringLiterals: false
|
||||
ColumnLimit: 96
|
||||
CommentPragmas: '^ IWYU pragma:'
|
||||
CompactNamespaces: false
|
||||
ConstructorInitializerIndentWidth: 8
|
||||
ContinuationIndentWidth: 8
|
||||
Cpp11BracedListStyle: true
|
||||
DerivePointerAlignment: false
|
||||
DisableFormat: false
|
||||
EmptyLineAfterAccessModifier: Never
|
||||
EmptyLineBeforeAccessModifier: LogicalBlock
|
||||
ExperimentalAutoDetectBinPacking: false
|
||||
FixNamespaceComments: false
|
||||
|
||||
# git grep '^#define [^[:space:]]*for_each[^[:space:]]*(' | grep -v "vendorcode\|payloads\|util" | sed "s|.*:||;s|^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$| - '\1'|" | LC_ALL=C sort -u
|
||||
ForEachMacros:
|
||||
- 'list_for_each'
|
||||
|
||||
# git grep -i '^#define \+if[^[:space:]]*(' | grep -v "vendorcode\|payloads\|util" | sed "s|.*:||;s|^#define \([^[:space:]]*if[^[:space:]]*\)(.*$| - '\1'|I" | grep -v IFIX | LC_ALL=C sort -u
|
||||
IfMacros:
|
||||
- 'IF_CHANNEL_POPULATED'
|
||||
- 'IF_DIMM_POPULATED'
|
||||
- 'IF_RANK_POPULATED'
|
||||
- 'IfBit0'
|
||||
IncludeBlocks: Preserve
|
||||
IncludeIsMainSourceRegex: ''
|
||||
IndentAccessModifiers: false
|
||||
IndentCaseBlocks: false
|
||||
IndentCaseLabels: false
|
||||
IndentExternBlock: AfterExternBlock
|
||||
IndentGotoLabels: false
|
||||
IndentPPDirectives: None
|
||||
IndentRequiresClause: true
|
||||
IndentWidth: 8
|
||||
IndentWrappedFunctionNames: false
|
||||
InsertBraces: false
|
||||
InsertNewlineAtEOF: true
|
||||
InsertTrailingCommas: None
|
||||
IntegerLiteralSeparator:
|
||||
Binary: 0
|
||||
BinaryMinDigits: 0
|
||||
Decimal: 0
|
||||
DecimalMinDigits: 0
|
||||
Hex: 0
|
||||
HexMinDigits: 0
|
||||
JavaScriptQuotes: Leave
|
||||
JavaScriptWrapImports: true
|
||||
KeepEmptyLinesAtTheStartOfBlocks: false
|
||||
LambdaBodyIndentation: Signature
|
||||
LineEnding: LF
|
||||
MacroBlockBegin: ''
|
||||
MacroBlockEnd: ''
|
||||
MaxEmptyLinesToKeep: 1
|
||||
NamespaceIndentation: None
|
||||
ObjCBinPackProtocolList: Auto
|
||||
ObjCBlockIndentWidth: 8
|
||||
ObjCBreakBeforeNestedBlockParam: true
|
||||
ObjCSpaceAfterProperty: true
|
||||
ObjCSpaceBeforeProtocolList: true
|
||||
PackConstructorInitializers: BinPack
|
||||
PenaltyBreakAssignment: 10
|
||||
PenaltyBreakBeforeFirstCallParameter: 30
|
||||
PenaltyBreakComment: 10
|
||||
PenaltyBreakFirstLessLess: 0
|
||||
PenaltyBreakOpenParenthesis: 0
|
||||
PenaltyBreakString: 10
|
||||
PenaltyBreakTemplateDeclaration: 10
|
||||
PenaltyExcessCharacter: 100
|
||||
PenaltyIndentedWhitespace: 0
|
||||
PenaltyReturnTypeOnItsOwnLine: 60
|
||||
PointerAlignment: Right
|
||||
PPIndentWidth: -1
|
||||
QualifierAlignment: Left
|
||||
ReferenceAlignment: Pointer
|
||||
ReflowComments: false
|
||||
RemoveBracesLLVM: false
|
||||
RemoveSemicolon: false
|
||||
RequiresClausePosition: OwnLine
|
||||
RequiresExpressionIndentation: OuterScope
|
||||
SeparateDefinitionBlocks: Leave
|
||||
ShortNamespaceLines: 1
|
||||
SortIncludes: Never
|
||||
SortJavaStaticImport: Before
|
||||
SortUsingDeclarations: Never
|
||||
SpaceAfterCStyleCast: false
|
||||
SpaceAfterLogicalNot: false
|
||||
SpaceAfterTemplateKeyword: true
|
||||
SpaceAroundPointerQualifiers: Default
|
||||
SpaceBeforeAssignmentOperators: true
|
||||
SpaceBeforeCaseColon: false
|
||||
SpaceBeforeCpp11BracedList: false
|
||||
SpaceBeforeCtorInitializerColon: true
|
||||
SpaceBeforeInheritanceColon: true
|
||||
SpaceBeforeParens: ControlStatementsExceptControlMacros
|
||||
SpaceBeforeParensOptions:
|
||||
AfterControlStatements: true
|
||||
AfterForeachMacros: false
|
||||
AfterFunctionDefinitionName: false
|
||||
AfterFunctionDeclarationName: false
|
||||
AfterIfMacros: false
|
||||
AfterOverloadedOperator: false
|
||||
AfterRequiresInClause: false
|
||||
AfterRequiresInExpression: false
|
||||
BeforeNonEmptyParentheses: false
|
||||
SpaceBeforeRangeBasedForLoopColon: true
|
||||
SpaceBeforeSquareBrackets: false
|
||||
SpaceInEmptyBlock: false
|
||||
SpaceInEmptyParentheses: false
|
||||
SpacesBeforeTrailingComments: 1
|
||||
SpacesInAngles: Never
|
||||
SpacesInConditionalStatement: false
|
||||
SpacesInContainerLiterals: false
|
||||
SpacesInCStyleCastParentheses: false
|
||||
SpacesInLineCommentPrefix:
|
||||
Minimum: 1
|
||||
Maximum: 1
|
||||
SpacesInParentheses: false
|
||||
SpacesInSquareBrackets: false
|
||||
Standard: c++17
|
||||
TabWidth: 8
|
||||
UseTab: ForContinuationAndIndentation
|
||||
...
|
||||
|
||||
|
@@ -9,3 +9,7 @@ charset = utf-8
|
||||
insert_final_newline = true
|
||||
end_of_line = lf
|
||||
trim_trailing_whitespace = true
|
||||
|
||||
[*.sh]
|
||||
indent_style = space
|
||||
indent_size = 2
|
||||
|
1
.gitignore
vendored
1
.gitignore
vendored
@@ -9,6 +9,7 @@ defconfig
|
||||
build/
|
||||
coreboot-builds/
|
||||
coreboot-builds*/
|
||||
generated/
|
||||
|
||||
site-local
|
||||
|
||||
|
5
.gitmodules
vendored
5
.gitmodules
vendored
@@ -13,9 +13,6 @@
|
||||
[submodule "arm-trusted-firmware"]
|
||||
path = 3rdparty/arm-trusted-firmware
|
||||
url = https://review.coreboot.org/arm-trusted-firmware.git
|
||||
[submodule "3rdparty/chromeec"]
|
||||
path = 3rdparty/chromeec
|
||||
url = https://review.coreboot.org/chrome-ec.git
|
||||
[submodule "libhwbase"]
|
||||
path = 3rdparty/libhwbase
|
||||
url = https://review.coreboot.org/libhwbase.git
|
||||
@@ -63,7 +60,7 @@
|
||||
branch = stmpe
|
||||
[submodule "util/goswid"]
|
||||
path = util/goswid
|
||||
url = https://review.coreboot.org/goswid.git
|
||||
url = https://review.coreboot.org/goswid
|
||||
branch = trunk
|
||||
[submodule "src/vendorcode/amd/opensil/genoa_poc/opensil"]
|
||||
path = src/vendorcode/amd/opensil/genoa_poc/opensil
|
||||
|
@@ -2,4 +2,4 @@
|
||||
host=review.coreboot.org
|
||||
port=29418
|
||||
project=coreboot
|
||||
defaultbranch=master
|
||||
defaultbranch=main
|
||||
|
2
3rdparty/amd_blobs
vendored
2
3rdparty/amd_blobs
vendored
Submodule 3rdparty/amd_blobs updated: e4519efca7...26c572974b
2
3rdparty/arm-trusted-firmware
vendored
2
3rdparty/arm-trusted-firmware
vendored
Submodule 3rdparty/arm-trusted-firmware updated: 88b2d81345...c5b8de86c8
2
3rdparty/blobs
vendored
2
3rdparty/blobs
vendored
Submodule 3rdparty/blobs updated: a8db7dfe82...45f1b75740
1
3rdparty/chromeec
vendored
1
3rdparty/chromeec
vendored
Submodule 3rdparty/chromeec deleted from e486b388a7
2
3rdparty/cmocka
vendored
2
3rdparty/cmocka
vendored
Submodule 3rdparty/cmocka updated: 8931845c35...8be3737209
2
3rdparty/fsp
vendored
2
3rdparty/fsp
vendored
Submodule 3rdparty/fsp updated: 481ea7cf0b...800c85770b
2
3rdparty/intel-microcode
vendored
2
3rdparty/intel-microcode
vendored
Submodule 3rdparty/intel-microcode updated: 6788bb07eb...2f5650548f
2
3rdparty/libgfxinit
vendored
2
3rdparty/libgfxinit
vendored
Submodule 3rdparty/libgfxinit updated: a4be8a21b0...17cfc92f40
2
3rdparty/vboot
vendored
2
3rdparty/vboot
vendored
Submodule 3rdparty/vboot updated: 24cb127a5e...f1f70f46dc
34
AUTHORS
34
AUTHORS
@@ -39,7 +39,9 @@ Alexandru Gagniuc
|
||||
Alexey Buyanov
|
||||
Alexey Vazhnov
|
||||
Alice Sell
|
||||
Alicja Michalska
|
||||
Allen-KH Cheng
|
||||
Alper Nebi Yasak
|
||||
Amanda Hwang
|
||||
American Megatrends International, LLC
|
||||
Amersel
|
||||
@@ -62,6 +64,7 @@ Anna Karaś
|
||||
Annie Chen
|
||||
Anton Kochkov
|
||||
Ao Zhong
|
||||
Appukuttan V K
|
||||
Arashk Mahshidfar
|
||||
Arec Kao
|
||||
Ariel Fang
|
||||
@@ -93,6 +96,7 @@ Bora Guvendik
|
||||
Boris Barbulovski
|
||||
Boris Mittelberg
|
||||
Brandon Breitenstein
|
||||
Brandon Weeks
|
||||
Brian Norris
|
||||
Bryant Ou
|
||||
Carl-Daniel Hailfinger
|
||||
@@ -101,6 +105,7 @@ Caveh Jalali
|
||||
Cavium Inc.
|
||||
Chao Gui
|
||||
Chen-Tsung Hsieh
|
||||
Chen. Gang C
|
||||
Chia-Ling Hou
|
||||
Chien-Chih Tseng
|
||||
Chris Wang
|
||||
@@ -128,6 +133,7 @@ Da Lao
|
||||
Daisuke Nojiri
|
||||
Damien Zammit
|
||||
Dan Callaghan
|
||||
Dan Campbell
|
||||
Daniel Campello
|
||||
Daniel Gröber
|
||||
Daniel Kang
|
||||
@@ -181,6 +187,7 @@ Eltan B.V
|
||||
Eltan B.V.
|
||||
Elyes Haouas
|
||||
Eran Mitrani
|
||||
Eren Peng
|
||||
Eric Biederman
|
||||
Eric Lai
|
||||
Eric Peers
|
||||
@@ -194,13 +201,16 @@ Evan Green
|
||||
Evgeny Zinoviev
|
||||
Fabian Groffen
|
||||
Fabian Kunkel
|
||||
Fabian Meyer
|
||||
Fabio Aiuto
|
||||
Fabrice Bellard
|
||||
Facebook, Inc.
|
||||
Fei Yan
|
||||
Felix Friedlander
|
||||
Felix Held
|
||||
Felix Singer
|
||||
Fengquan Chen
|
||||
Filip Lewiński
|
||||
Flora Fu
|
||||
Florian Laufenböck
|
||||
Francois Toguo Fotso
|
||||
@@ -214,7 +224,7 @@ Free Software Foundation, Inc.
|
||||
Freescale Semiconductor, Inc.
|
||||
Furquan Shaikh
|
||||
Gaggery Tsai
|
||||
Gang C Chen
|
||||
Gang C Chen
|
||||
Garmin Chang
|
||||
Gary Jennejohn
|
||||
George Trudeau
|
||||
@@ -234,6 +244,7 @@ HardenedLinux
|
||||
Harsha B R
|
||||
Harshit Sharma
|
||||
Henry C Chen
|
||||
Herbert Wu
|
||||
Hewlett Packard Enterprise Development LP
|
||||
Hewlett-Packard Development Company, L.P.
|
||||
Himanshu Sahdev
|
||||
@@ -286,6 +297,7 @@ Jason Zhao
|
||||
jason-ch chen
|
||||
Jason-jh Lin
|
||||
Jay Patel
|
||||
Jean Lucas
|
||||
Jeff Chase
|
||||
Jeff Daly
|
||||
Jeff Li
|
||||
@@ -307,6 +319,7 @@ Jitao Shi
|
||||
Joe Pillow
|
||||
Joe Tessler
|
||||
Joel Kitching
|
||||
Joel Linn
|
||||
Joey Peng
|
||||
Johanna Schander
|
||||
John Su
|
||||
@@ -325,6 +338,7 @@ Jordan Crouse
|
||||
Jörg Mische
|
||||
Joseph Smith
|
||||
Josie Nordrum
|
||||
Juan José García-Castro Crespo
|
||||
Julia Tsai
|
||||
Julian Schroeder
|
||||
Julian Stecklina
|
||||
@@ -337,6 +351,7 @@ Kangheui Won
|
||||
Kapil Porwal
|
||||
Karol Zmyslowski
|
||||
Karthik Ramasubramanian
|
||||
Kei Hiroyoshi
|
||||
Keith Hui
|
||||
Keith Packard
|
||||
Kenneth Chan
|
||||
@@ -367,9 +382,11 @@ Lawrence Chang
|
||||
Leah Rowe
|
||||
Lean Sheng Tan
|
||||
Lei Wen
|
||||
Lennart Eichhorn
|
||||
Lenovo Group Ltd
|
||||
Leo Chou
|
||||
Li-Ta Lo
|
||||
Li1 Feng
|
||||
Liam Flaherty
|
||||
Libra Li
|
||||
Libretrend LDA
|
||||
@@ -397,6 +414,7 @@ Marc Bertens
|
||||
Marc Jones
|
||||
Marco Chen
|
||||
Marek Kasiewicz
|
||||
Marek Maślanka
|
||||
Marek Vasut
|
||||
Mario Scheithauer
|
||||
Marius Gröger
|
||||
@@ -465,10 +483,12 @@ Myles Watson
|
||||
Nancy.Lin
|
||||
Naresh Solanki
|
||||
Nathan Lu
|
||||
Naveen R. Iyer
|
||||
Neill Corlett
|
||||
Network Appliance Inc.
|
||||
Nicholas Chin
|
||||
Nicholas Sielicki
|
||||
Nicholas Sudsgaard
|
||||
Nick Barker
|
||||
Nick Chen
|
||||
Nick Vaccaro
|
||||
@@ -502,6 +522,7 @@ Paul Fagerburg
|
||||
Paul Menzel
|
||||
Paul2 Huang
|
||||
Paulo Alcantara
|
||||
Pavan Holla
|
||||
Pavel Sayekat
|
||||
Paz Zcharya
|
||||
PC Engines GmbH
|
||||
@@ -520,6 +541,7 @@ Philipp Deppenwiese
|
||||
Philipp Hug
|
||||
Piotr Kleinschmidt
|
||||
Po Xu
|
||||
Poornima Tom
|
||||
Prasad Malisetty
|
||||
Prashant Malani
|
||||
Pratik Vishwakarma
|
||||
@@ -529,6 +551,7 @@ Protectli
|
||||
Purism SPC
|
||||
Purism, SPC
|
||||
Qii Wang
|
||||
Qinghong Zeng
|
||||
Qualcomm Technologies, Inc.
|
||||
Quanta Computer INC
|
||||
Raihow Shi
|
||||
@@ -572,6 +595,7 @@ Robinson P. Tryon
|
||||
Rockchip, Inc.
|
||||
Rocky Phagura
|
||||
Roger Lu
|
||||
Roger Wang
|
||||
Roja Rani Yarubandi
|
||||
Romain Lievin
|
||||
Roman Zippel
|
||||
@@ -745,12 +769,14 @@ Wojciech Macek
|
||||
Wolfgang Denk
|
||||
Won Chung
|
||||
Wonkyu Kim
|
||||
Wuxy
|
||||
Wuxy
|
||||
Xiang W
|
||||
Xin Ji
|
||||
Xixi Chen
|
||||
Xuxin Xiong
|
||||
YADRO
|
||||
Yan Liu
|
||||
Yang Wu
|
||||
Yann Collet
|
||||
Yaroslav Kurlaev
|
||||
YH Lin
|
||||
@@ -767,6 +793,7 @@ Yuanliding
|
||||
Yuchen He
|
||||
Yuchen Huang
|
||||
Yunlong Jia
|
||||
Yuval Peress
|
||||
Zachary Yedidia
|
||||
Zanxi Chen
|
||||
Zhanyong Wang
|
||||
@@ -776,10 +803,11 @@ Zhi7 Li
|
||||
Zhiqiang Ma
|
||||
Zhixing Ma
|
||||
Zhiyong Tao
|
||||
zhongtian wu
|
||||
Zhongtian Wu
|
||||
Zhuohao Lee
|
||||
Ziang Wang
|
||||
Zoey Wu
|
||||
Zoltan Baldaszti
|
||||
小田喜陽彦
|
||||
忧郁沙茶
|
||||
陳建宏
|
@@ -31,8 +31,7 @@ livesphinx: $(BUILDDIR)
|
||||
|
||||
test:
|
||||
@echo "Test for logging purposes - Failing tests will not fail the build"
|
||||
-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx html
|
||||
-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx doctest
|
||||
-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -k -f Makefile.sphinx html
|
||||
|
||||
help:
|
||||
@echo "all - Builds all documentation targets"
|
||||
|
@@ -1,60 +1,20 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
# Makefile for Sphinx documentation
|
||||
# Minimal makefile for Sphinx documentation
|
||||
#
|
||||
|
||||
# You can set these variables from the command line.
|
||||
SPHINXOPTS ?=
|
||||
SPHINXBUILD = sphinx-build
|
||||
SPHINXAUTOBUILD = sphinx-autobuild
|
||||
PAPER =
|
||||
BUILDDIR = _build
|
||||
# You can set these variables from the command line, and also
|
||||
# from the environment for the first two.
|
||||
SPHINXOPTS ?=
|
||||
SPHINXBUILD ?= sphinx-build
|
||||
SPHINXAUTOBUILD = sphinx-autobuild
|
||||
SOURCEDIR = .
|
||||
BUILDDIR = _build
|
||||
|
||||
# Internal variables.
|
||||
PAPEROPT_a4 = -D latex_paper_size=a4
|
||||
PAPEROPT_letter = -D latex_paper_size=letter
|
||||
ALLSPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) .
|
||||
# the i18n builder cannot share the environment and doctrees with the others
|
||||
I18NSPHINXOPTS = $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) .
|
||||
|
||||
.PHONY: help
|
||||
# Put it first so that "make" without argument is like "make help".
|
||||
help:
|
||||
@echo "Please use \`make <target>' where <target> is one of"
|
||||
@echo " html to make standalone HTML files"
|
||||
@echo " dirhtml to make HTML files named index.html in directories"
|
||||
@echo " singlehtml to make a single large HTML file"
|
||||
@echo " pickle to make pickle files"
|
||||
@echo " json to make JSON files"
|
||||
@echo " htmlhelp to make HTML files and a HTML help project"
|
||||
@echo " qthelp to make HTML files and a qthelp project"
|
||||
@echo " applehelp to make an Apple Help Book"
|
||||
@echo " devhelp to make HTML files and a Devhelp project"
|
||||
@echo " epub to make an epub"
|
||||
@echo " epub3 to make an epub3"
|
||||
@echo " latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter"
|
||||
@echo " latexpdf to make LaTeX files and run them through pdflatex"
|
||||
@echo " latexpdfja to make LaTeX files and run them through platex/dvipdfmx"
|
||||
@echo " text to make text files"
|
||||
@echo " man to make manual pages"
|
||||
@echo " texinfo to make Texinfo files"
|
||||
@echo " info to make Texinfo files and run them through makeinfo"
|
||||
@echo " gettext to make PO message catalogs"
|
||||
@echo " changes to make an overview of all changed/added/deprecated items"
|
||||
@echo " xml to make Docutils-native XML files"
|
||||
@echo " pseudoxml to make pseudoxml-XML files for display purposes"
|
||||
@echo " linkcheck to check all external links for integrity"
|
||||
@echo " doctest to run all doctests embedded in the documentation (if enabled)"
|
||||
@echo " coverage to run coverage check of the documentation (if enabled)"
|
||||
@echo " dummy to check syntax errors of document sources"
|
||||
@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
rm -rf $(BUILDDIR)
|
||||
|
||||
.PHONY: html
|
||||
html:
|
||||
$(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html
|
||||
@echo
|
||||
@echo "Build finished. The HTML pages are in $(BUILDDIR)/html."
|
||||
.PHONY: help Makefile.sphinx
|
||||
|
||||
.PHONY: livehtml
|
||||
livehtml:
|
||||
@@ -63,172 +23,7 @@ livehtml:
|
||||
@echo
|
||||
$(SPHINXAUTOBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)
|
||||
|
||||
.PHONY: dirhtml
|
||||
dirhtml:
|
||||
$(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml
|
||||
@echo
|
||||
@echo "Build finished. The HTML pages are in $(BUILDDIR)/dirhtml."
|
||||
|
||||
.PHONY: singlehtml
|
||||
singlehtml:
|
||||
$(SPHINXBUILD) -b singlehtml $(ALLSPHINXOPTS) $(BUILDDIR)/singlehtml
|
||||
@echo
|
||||
@echo "Build finished. The HTML page is in $(BUILDDIR)/singlehtml."
|
||||
|
||||
.PHONY: pickle
|
||||
pickle:
|
||||
$(SPHINXBUILD) -b pickle $(ALLSPHINXOPTS) $(BUILDDIR)/pickle
|
||||
@echo
|
||||
@echo "Build finished; now you can process the pickle files."
|
||||
|
||||
.PHONY: json
|
||||
json:
|
||||
$(SPHINXBUILD) -b json $(ALLSPHINXOPTS) $(BUILDDIR)/json
|
||||
@echo
|
||||
@echo "Build finished; now you can process the JSON files."
|
||||
|
||||
.PHONY: htmlhelp
|
||||
htmlhelp:
|
||||
$(SPHINXBUILD) -b htmlhelp $(ALLSPHINXOPTS) $(BUILDDIR)/htmlhelp
|
||||
@echo
|
||||
@echo "Build finished; now you can run HTML Help Workshop with the" \
|
||||
".hhp project file in $(BUILDDIR)/htmlhelp."
|
||||
|
||||
.PHONY: qthelp
|
||||
qthelp:
|
||||
$(SPHINXBUILD) -b qthelp $(ALLSPHINXOPTS) $(BUILDDIR)/qthelp
|
||||
@echo
|
||||
@echo "Build finished; now you can run "qcollectiongenerator" with the" \
|
||||
".qhcp project file in $(BUILDDIR)/qthelp, like this:"
|
||||
@echo "# qcollectiongenerator $(BUILDDIR)/qthelp/coreboot.qhcp"
|
||||
@echo "To view the help file:"
|
||||
@echo "# assistant -collectionFile $(BUILDDIR)/qthelp/coreboot.qhc"
|
||||
|
||||
.PHONY: applehelp
|
||||
applehelp:
|
||||
$(SPHINXBUILD) -b applehelp $(ALLSPHINXOPTS) $(BUILDDIR)/applehelp
|
||||
@echo
|
||||
@echo "Build finished. The help book is in $(BUILDDIR)/applehelp."
|
||||
@echo "N.B. You won't be able to view it unless you put it in" \
|
||||
"~/Library/Documentation/Help or install it in your application" \
|
||||
"bundle."
|
||||
|
||||
.PHONY: devhelp
|
||||
devhelp:
|
||||
$(SPHINXBUILD) -b devhelp $(ALLSPHINXOPTS) $(BUILDDIR)/devhelp
|
||||
@echo
|
||||
@echo "Build finished."
|
||||
@echo "To view the help file:"
|
||||
@echo "# mkdir -p $$HOME/.local/share/devhelp/coreboot"
|
||||
@echo "# ln -s $(BUILDDIR)/devhelp $$HOME/.local/share/devhelp/coreboot"
|
||||
@echo "# devhelp"
|
||||
|
||||
.PHONY: epub
|
||||
epub:
|
||||
$(SPHINXBUILD) -b epub $(ALLSPHINXOPTS) $(BUILDDIR)/epub
|
||||
@echo
|
||||
@echo "Build finished. The epub file is in $(BUILDDIR)/epub."
|
||||
|
||||
.PHONY: epub3
|
||||
epub3:
|
||||
$(SPHINXBUILD) -b epub3 $(ALLSPHINXOPTS) $(BUILDDIR)/epub3
|
||||
@echo
|
||||
@echo "Build finished. The epub3 file is in $(BUILDDIR)/epub3."
|
||||
|
||||
.PHONY: latex
|
||||
latex:
|
||||
$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
|
||||
@echo
|
||||
@echo "Build finished; the LaTeX files are in $(BUILDDIR)/latex."
|
||||
@echo "Run \`make' in that directory to run these through (pdf)latex" \
|
||||
"(use \`make latexpdf' here to do that automatically)."
|
||||
|
||||
.PHONY: latexpdf
|
||||
latexpdf:
|
||||
$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
|
||||
@echo "Running LaTeX files through pdflatex..."
|
||||
$(MAKE) -C $(BUILDDIR)/latex all-pdf
|
||||
@echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex."
|
||||
|
||||
.PHONY: latexpdfja
|
||||
latexpdfja:
|
||||
$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
|
||||
@echo "Running LaTeX files through platex and dvipdfmx..."
|
||||
$(MAKE) -C $(BUILDDIR)/latex all-pdf-ja
|
||||
@echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex."
|
||||
|
||||
.PHONY: text
|
||||
text:
|
||||
$(SPHINXBUILD) -b text $(ALLSPHINXOPTS) $(BUILDDIR)/text
|
||||
@echo
|
||||
@echo "Build finished. The text files are in $(BUILDDIR)/text."
|
||||
|
||||
.PHONY: man
|
||||
man:
|
||||
$(SPHINXBUILD) -b man $(ALLSPHINXOPTS) $(BUILDDIR)/man
|
||||
@echo
|
||||
@echo "Build finished. The manual pages are in $(BUILDDIR)/man."
|
||||
|
||||
.PHONY: texinfo
|
||||
texinfo:
|
||||
$(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo
|
||||
@echo
|
||||
@echo "Build finished. The Texinfo files are in $(BUILDDIR)/texinfo."
|
||||
@echo "Run \`make' in that directory to run these through makeinfo" \
|
||||
"(use \`make info' here to do that automatically)."
|
||||
|
||||
.PHONY: info
|
||||
info:
|
||||
$(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo
|
||||
@echo "Running Texinfo files through makeinfo..."
|
||||
make -C $(BUILDDIR)/texinfo info
|
||||
@echo "makeinfo finished; the Info files are in $(BUILDDIR)/texinfo."
|
||||
|
||||
.PHONY: gettext
|
||||
gettext:
|
||||
$(SPHINXBUILD) -b gettext $(I18NSPHINXOPTS) $(BUILDDIR)/locale
|
||||
@echo
|
||||
@echo "Build finished. The message catalogs are in $(BUILDDIR)/locale."
|
||||
|
||||
.PHONY: changes
|
||||
changes:
|
||||
$(SPHINXBUILD) -b changes $(ALLSPHINXOPTS) $(BUILDDIR)/changes
|
||||
@echo
|
||||
@echo "The overview file is in $(BUILDDIR)/changes."
|
||||
|
||||
.PHONY: linkcheck
|
||||
linkcheck:
|
||||
$(SPHINXBUILD) -b linkcheck $(ALLSPHINXOPTS) $(BUILDDIR)/linkcheck
|
||||
@echo
|
||||
@echo "Link check complete; look for any errors in the above output " \
|
||||
"or in $(BUILDDIR)/linkcheck/output.txt."
|
||||
|
||||
.PHONY: doctest
|
||||
doctest:
|
||||
$(SPHINXBUILD) -b doctest $(ALLSPHINXOPTS) $(BUILDDIR)/doctest
|
||||
@echo "Testing of doctests in the sources finished, look at the " \
|
||||
"results in $(BUILDDIR)/doctest/output.txt."
|
||||
|
||||
.PHONY: coverage
|
||||
coverage:
|
||||
$(SPHINXBUILD) -b coverage $(ALLSPHINXOPTS) $(BUILDDIR)/coverage
|
||||
@echo "Testing of coverage in the sources finished, look at the " \
|
||||
"results in $(BUILDDIR)/coverage/python.txt."
|
||||
|
||||
.PHONY: xml
|
||||
xml:
|
||||
$(SPHINXBUILD) -b xml $(ALLSPHINXOPTS) $(BUILDDIR)/xml
|
||||
@echo
|
||||
@echo "Build finished. The XML files are in $(BUILDDIR)/xml."
|
||||
|
||||
.PHONY: pseudoxml
|
||||
pseudoxml:
|
||||
$(SPHINXBUILD) -b pseudoxml $(ALLSPHINXOPTS) $(BUILDDIR)/pseudoxml
|
||||
@echo
|
||||
@echo "Build finished. The pseudo-XML files are in $(BUILDDIR)/pseudoxml."
|
||||
|
||||
.PHONY: dummy
|
||||
dummy:
|
||||
$(SPHINXBUILD) -b dummy $(ALLSPHINXOPTS) $(BUILDDIR)/dummy
|
||||
@echo
|
||||
@echo "Build finished. Dummy builder generates no files."
|
||||
# Catch-all target: route all unknown targets to Sphinx using the new
|
||||
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
|
||||
%: Makefile.sphinx
|
||||
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
|
||||
|
@@ -5,18 +5,34 @@ backwards support for ACPI 1.0 and is only compatible to ACPI version 2.0 and
|
||||
upwards.
|
||||
|
||||
|
||||
- [SSDT UID generation](uid.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
SSDT UID generation <uid.md>
|
||||
```
|
||||
|
||||
## GPIO
|
||||
|
||||
- [GPIO toggling in ACPI AML](gpio.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
GPIO toggling in ACPI AML <gpio.md>
|
||||
```
|
||||
|
||||
## Windows-specific ACPI documentation
|
||||
|
||||
- [Windows-specific documentation](windows.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Windows-specific documentation <windows.md>
|
||||
```
|
||||
|
||||
## ACPI specification - Useful links
|
||||
|
||||
- [ACPI Specification 6.5](https://uefi.org/specs/ACPI/6.5/index.html)
|
||||
- [ASL 2.0 Syntax](https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-operators-and-expressions)
|
||||
- [Predefined ACPI Names](https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#predefined-acpi-names)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
ACPI Specification 6.5 <https://uefi.org/specs/ACPI/6.5/index.html>
|
||||
ASL 2.0 Syntax <https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-operators-and-expressions>
|
||||
Predefined ACPI Names <https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#predefined-acpi-names>
|
||||
```
|
||||
|
@@ -1141,4 +1141,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
|
||||
|
||||
## References:
|
||||
* [AMD Glossary of terms](https://www.amd.com/system/files/documents/glossary-of-terms-20220505-for-web.pdf)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
AMD Glossary of terms <https://www.amd.com/system/files/documents/glossary-of-terms-20220505-for-web.pdf>
|
||||
```
|
||||
|
@@ -5,7 +5,15 @@ architectures.
|
||||
|
||||
## RISC-V
|
||||
|
||||
- [RISC-V documentation](riscv/index.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
RISC-V documentation <riscv/index.md>
|
||||
```
|
||||
|
||||
## x86
|
||||
- [x86 documentation](x86/index.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
x86 documentation <x86/index.md>
|
||||
```
|
||||
|
@@ -2,12 +2,14 @@
|
||||
|
||||
This section contains documentation about coreboot on x86 architecture.
|
||||
|
||||
* [x86 PAE support](pae.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
x86 PAE support <pae.md>
|
||||
```
|
||||
|
||||
## State of x86_64 support
|
||||
At the moment there's only experimental x86_64 support.
|
||||
The `emulation/qemu-i440fx` and `emulation/qemu-q35` boards do support
|
||||
*ARCH_RAMSTAGE_X86_64* , *ARCH_POSTCAR_X86_64* and *ARCH_ROMSTAGE_X86_64*.
|
||||
Some SOCs now support 64bit mode. Search for HAVE_X86_64_SUPPORT in Kconfig.
|
||||
|
||||
In order to add support for x86_64 the following assumptions were made:
|
||||
* The CPU supports long mode
|
||||
@@ -15,7 +17,6 @@ In order to add support for x86_64 the following assumptions were made:
|
||||
* All code that is to be run must be below 4GiB in physical memory
|
||||
* The high dword of pointers is always zero
|
||||
* The reference implementation is qemu
|
||||
* The CPU supports 1GiB hugepages
|
||||
* x86 payloads are loaded below 4GiB in physical memory and are jumped
|
||||
to in *protected mode*
|
||||
|
||||
@@ -43,8 +44,12 @@ Basic support for x86_64 has been implemented for QEMU mainboard target.
|
||||
|
||||
## Reference implementation
|
||||
The reference implementation is
|
||||
* [QEMU i440fx](../../mainboard/emulation/qemu-i440fx.md)
|
||||
* [QEMU Q35](../../mainboard/emulation/qemu-q35.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
QEMU i440fx <../../mainboard/emulation/qemu-i440fx.md>
|
||||
QEMU Q35 <../../mainboard/emulation/qemu-q35.md>
|
||||
```
|
||||
|
||||
## TODO
|
||||
* Identity map memory above 4GiB in ramstage
|
||||
@@ -54,7 +59,6 @@ The reference implementation is
|
||||
1. Fine grained page tables for SMM:
|
||||
* Must not have execute and write permissions for the same page.
|
||||
* Must allow only that TSEG pages can be marked executable
|
||||
* Must reside in SMRAM
|
||||
2. Support 64bit PCI BARs above 4GiB
|
||||
3. Place and run code above 4GiB
|
||||
|
||||
@@ -62,13 +66,10 @@ The reference implementation is
|
||||
* Fix compilation errors
|
||||
* Test how well CAR works with x86_64 and paging
|
||||
* Improve mode switches
|
||||
* Test libgfxinit / VGA Option ROMs / FSP
|
||||
|
||||
## Known bugs on real hardware
|
||||
## Known problems on real hardware
|
||||
|
||||
According to Intel x86_64 mode hasn't been validated in CAR environments.
|
||||
Until now it could be verified on various Intel platforms and no issues have
|
||||
been found.
|
||||
Running VGA rom directly fails. Yabel works fine though.
|
||||
|
||||
## Known bugs on KVM enabled qemu
|
||||
|
||||
|
@@ -1,6 +1,10 @@
|
||||
# Community
|
||||
|
||||
* [Code of Conduct](code_of_conduct.md)
|
||||
* [Language style](language_style.md)
|
||||
* [Community forums](forums.md)
|
||||
* [coreboot at conferences](conferences.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Code of Conduct <code_of_conduct.md>
|
||||
Language style <language_style.md>
|
||||
Community forums <forums.md>
|
||||
coreboot at conferences <conferences.md>
|
||||
```
|
||||
|
@@ -1,46 +1,34 @@
|
||||
# -*- coding: utf-8 -*-
|
||||
import subprocess
|
||||
from recommonmark.parser import CommonMarkParser
|
||||
import sphinx
|
||||
|
||||
# Get Sphinx version
|
||||
major = 0
|
||||
minor = 0
|
||||
patchlevel = 0
|
||||
version = sphinx.__version__.split(".")
|
||||
if len(version) > 1:
|
||||
major = int(version[0])
|
||||
minor = int(version[1])
|
||||
if len(version) > 2:
|
||||
patchlevel = int(version[2])
|
||||
|
||||
# Add any paths that contain templates here, relative to this directory.
|
||||
templates_path = ['_templates']
|
||||
|
||||
# The suffix(es) of source filenames.
|
||||
source_suffix = ['.md']
|
||||
|
||||
# The master toctree document.
|
||||
master_doc = 'index'
|
||||
|
||||
# General information about the project.
|
||||
project = u'coreboot'
|
||||
copyright = u'CC-by 4.0 the coreboot project'
|
||||
author = u'the coreboot project'
|
||||
|
||||
# The version info for the project you're documenting, acts as replacement for
|
||||
# |version| and |release|, also used in various other places throughout the
|
||||
# built documents.
|
||||
# Configuration file for the Sphinx documentation builder.
|
||||
#
|
||||
# The full version, including alpha/beta/rc tags.
|
||||
# For the full list of built-in configuration values, see the documentation:
|
||||
# https://www.sphinx-doc.org/en/master/usage/configuration.html
|
||||
|
||||
# -- Project information -----------------------------------------------------
|
||||
# https://www.sphinx-doc.org/en/master/usage/configuration.html#project-information
|
||||
|
||||
import subprocess
|
||||
|
||||
project = 'coreboot'
|
||||
copyright = 'CC-by 4.0 the coreboot project'
|
||||
author = 'the coreboot project'
|
||||
|
||||
release = subprocess.check_output(('git', 'describe')).decode("utf-8")
|
||||
# The short X.Y version.
|
||||
version = release.split("-")[0]
|
||||
|
||||
extensions = []
|
||||
# Load recommonmark, supported since 1.8+
|
||||
if major >= 2 or (major == 1 and minor >= 8):
|
||||
extensions += ['recommonmark']
|
||||
|
||||
# -- General configuration ---------------------------------------------------
|
||||
# https://www.sphinx-doc.org/en/master/usage/configuration.html#general-configuration
|
||||
|
||||
extensions = ["myst_parser"]
|
||||
|
||||
myst_heading_anchors = 5
|
||||
|
||||
templates_path = ['_templates']
|
||||
exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
|
||||
|
||||
# The name of the Pygments (syntax highlighting) style to use.
|
||||
pygments_style = 'sphinx'
|
||||
|
||||
# Try to load DITAA
|
||||
try:
|
||||
@@ -57,62 +45,11 @@ else:
|
||||
# Usually you set "language" from the command line for these cases.
|
||||
language = 'en'
|
||||
|
||||
# List of patterns, relative to source directory, that match files and
|
||||
# directories to ignore when looking for source files.
|
||||
# This patterns also effect to html_static_path and html_extra_path
|
||||
exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
|
||||
# -- Options for HTML output -------------------------------------------------
|
||||
# https://www.sphinx-doc.org/en/master/usage/configuration.html#options-for-html-output
|
||||
|
||||
# The name of the Pygments (syntax highlighting) style to use.
|
||||
pygments_style = 'sphinx'
|
||||
|
||||
# A list of ignored prefixes for module index sorting.
|
||||
# modindex_common_prefix = []
|
||||
|
||||
# If true, keep warnings as "system message" paragraphs in the built documents.
|
||||
# keep_warnings = False
|
||||
|
||||
# If true, `todo` and `todoList` produce output, else they produce nothing.
|
||||
todo_include_todos = False
|
||||
|
||||
|
||||
# -- Options for HTML output ----------------------------------------------
|
||||
|
||||
# The theme to use for HTML and HTML Help pages. See the documentation for
|
||||
# a list of builtin themes.
|
||||
#
|
||||
html_theme = 'sphinx_rtd_theme'
|
||||
|
||||
# Add any paths that contain custom static files (such as style sheets) here,
|
||||
# relative to this directory. They are copied after the builtin static files,
|
||||
# so a file named "default.css" will overwrite the builtin "default.css".
|
||||
html_static_path = ['_static']
|
||||
|
||||
html_css_files = [
|
||||
'theme_overrides.css', # override wide tables in RTD theme
|
||||
]
|
||||
|
||||
# Output file base name for HTML help builder.
|
||||
htmlhelp_basename = 'corebootdoc'
|
||||
|
||||
enable_auto_toc_tree = True
|
||||
|
||||
class MyCommonMarkParser(CommonMarkParser):
|
||||
# remove this hack once upstream RecommonMark supports inline code
|
||||
def visit_code(self, mdnode):
|
||||
from docutils import nodes
|
||||
n = nodes.literal(mdnode.literal, mdnode.literal)
|
||||
self.current_node.append(n)
|
||||
|
||||
def setup(app):
|
||||
from recommonmark.transform import AutoStructify
|
||||
# Load recommonmark on old Sphinx
|
||||
if major == 1 and minor < 8:
|
||||
app.add_source_parser('.md', MyCommonMarkParser)
|
||||
|
||||
app.add_config_value('recommonmark_config', {
|
||||
'enable_auto_toc_tree': True,
|
||||
'enable_auto_doc_ref': False, # broken in Sphinx 1.6+
|
||||
'enable_eval_rst': True,
|
||||
'url_resolver': lambda url: '/' + url
|
||||
}, True)
|
||||
app.add_transform(AutoStructify)
|
||||
|
@@ -808,7 +808,7 @@ eDP display panel encounters an I2C error, it should print a "cannot read EDID"
|
||||
message and return an error code. The calling display initialization function
|
||||
knows that without the EDID there is no way to initialize the display correctly,
|
||||
so it will also immediately return with an error code without running its
|
||||
remaining code that would initialize the SoC's display controller. Exeuction
|
||||
remaining code that would initialize the SoC's display controller. Execution
|
||||
returns further up the function stack to the mainboard initialization code
|
||||
which continues booting despite the failed display initialization, since
|
||||
display functionality is non-essential to the system. (Code is encouraged but
|
||||
|
@@ -395,8 +395,8 @@ Gerrit user roles
|
||||
There are a few relevant roles a user can have on Gerrit:
|
||||
|
||||
- The anonymous user can check out source code.
|
||||
- A registered user can also comment and give "+1" and "-1" code reviews.
|
||||
- A reviewer can also give "+2" code reviews.
|
||||
- A registered user can also comment and give "+1" code reviews.
|
||||
- A reviewer can give "-1" and "+2" code reviews.
|
||||
- A core developer can also give "-2" (that is, blocking) code reviews
|
||||
and submit changes.
|
||||
|
||||
|
@@ -1,7 +1,11 @@
|
||||
# Contributing
|
||||
|
||||
* [Coding Style](coding_style.md)
|
||||
* [Gerrit Guidelines](gerrit_guidelines.md)
|
||||
* [Project Ideas](project_ideas.md)
|
||||
* [Documentation Ideas](documentation_ideas.md)
|
||||
* [Google Summer of Code](gsoc.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Coding Style <coding_style.md>
|
||||
Gerrit Guidelines <gerrit_guidelines.md>
|
||||
Project Ideas <project_ideas.md>
|
||||
Documentation Ideas <documentation_ideas.md>
|
||||
Google Summer of Code <gsoc.md>
|
||||
```
|
||||
|
@@ -29,7 +29,7 @@ sealings are sent via encrypted email.
|
||||
|
||||
### NovaCustom laptops
|
||||
|
||||
[NovaCustom](https://configurelaptop.eu/) sells configurable laptops with
|
||||
[NovaCustom](https://novacustom.com) sells configurable laptops with
|
||||
[Dasharo](https://dasharo.com/) coreboot based firmware on board, maintained by
|
||||
[3mdeb](https://3mdeb.com/). NovaCustom offers full GNU/Linux and Microsoft
|
||||
Windows compatibility. NovaCustom ensures security updates via fwupd for 5 years
|
||||
@@ -43,6 +43,16 @@ ships with coreboot and support upstream maintenance for the devices through a
|
||||
third party, [3mdeb](https://3mdeb.com). They provide current and tested
|
||||
firmware binaries on [GitHub](https://pcengines.github.io).
|
||||
|
||||
### Protectli
|
||||
|
||||
[Protectli](https://protectli.com) is dedicated to providing reliable,
|
||||
cost-effective, and secure computer equipment with coreboot-based firmware
|
||||
tailored for their hardware. It comes with the [Dasharo](#dasharo)
|
||||
firmware, maintained by [3mdeb](https://3mdeb.com/). Protectli hardware has
|
||||
verified support for many popular operating systems, such as Linux distributions,
|
||||
FreeBSD, and Windows. Support includes Debian, Ubuntu, OPNsense, pfSense,
|
||||
ProxMox VE, VMware ESXi, Windows 10 and 11, and many more.
|
||||
|
||||
### Purism
|
||||
|
||||
[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and
|
||||
|
@@ -8,10 +8,14 @@ For details on how to connect device drivers to a mainboard, see [Driver Devicet
|
||||
|
||||
Some of the drivers currently available include:
|
||||
|
||||
* [Intel DPTF](dptf.md)
|
||||
* [IPMI KCS](ipmi_kcs.md)
|
||||
* [SMMSTORE](smmstore.md)
|
||||
* [SMMSTOREv2](smmstorev2.md)
|
||||
* [SoundWire](soundwire.md)
|
||||
* [USB4 Retimer](retimer.md)
|
||||
* [CBFS SMBIOS hooks](cbfs_smbios.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Intel DPTF <dptf.md>
|
||||
IPMI KCS <ipmi_kcs.md>
|
||||
SMMSTORE <smmstore.md>
|
||||
SMMSTOREv2 <smmstorev2.md>
|
||||
SoundWire <soundwire.md>
|
||||
USB4 Retimer <retimer.md>
|
||||
CBFS SMBIOS hooks <cbfs_smbios.md>
|
||||
```
|
||||
|
@@ -128,7 +128,11 @@ data or modify the currently running kernel.*
|
||||
|
||||
## External links
|
||||
|
||||
* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI <https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf>
|
||||
```
|
||||
Note, this differs significantly from coreboot's implementation.
|
||||
|
||||
[SMM]: ../security/smm.md
|
||||
|
@@ -124,25 +124,9 @@ additional calling arguments are passed via `%ebx`.
|
||||
**NOTE**: The size of the struct entries are in the native word size of
|
||||
smihandler. This means 32 bits in almost all cases.
|
||||
|
||||
#### - SMMSTORE_CMD_INIT = 4
|
||||
#### - SMMSTORE_CMD_INIT_DEPRECATED = 4
|
||||
|
||||
This installs the communication buffer to use and thus enables the
|
||||
SMMSTORE handler. This command can only be executed once and is done
|
||||
by the firmware. Calling this function at runtime has no effect.
|
||||
|
||||
The additional parameter buffer `%ebx` contains a pointer to the
|
||||
following struct:
|
||||
|
||||
```C
|
||||
struct smmstore_params_init {
|
||||
uint32_t com_buffer;
|
||||
uint32_t com_buffer_size;
|
||||
} __packed;
|
||||
```
|
||||
|
||||
INPUT:
|
||||
- `com_buffer`: Physical address of the communication buffer (CBMEM)
|
||||
- `com_buffer_size`: Size in bytes of the communication buffer
|
||||
Unused, returns SMMSTORE_REG_UNSUPPORTED.
|
||||
|
||||
#### - SMMSTORE_CMD_RAW_READ = 5
|
||||
|
||||
@@ -215,7 +199,11 @@ running kernel.
|
||||
|
||||
## External links
|
||||
|
||||
* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI <https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf>
|
||||
```
|
||||
Note that this differs significantly from coreboot's implementation.
|
||||
|
||||
[SMM]: ../security/smm.md
|
||||
|
@@ -17,13 +17,21 @@ Please add any helpful or informational links and sections as you see fit.
|
||||
* [Part 1: PCI-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-in-x86x64-architecture-part-1-pci-based-systems/)
|
||||
* [Part 2: PCI express-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-x86x64-architecture-part-2-pci-express-based-systems/)
|
||||
* [PCIe elastic buffer](https://www.mindshare.com/files/resources/mindshare_pcie_elastic_buffer.pdf)
|
||||
* [Boot Guard and PSB have user-hostile defaults](https://mjg59.dreamwidth.org/58424.html)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Boot Guard and PSB have user-hostile defaults <https://mjg59.dreamwidth.org/58424.html>
|
||||
```
|
||||
|
||||
|
||||
## General Information
|
||||
|
||||
* [OS Dev](https://wiki.osdev.org/Categorized_Main_Page)
|
||||
* [Interface BUS](http://www.interfacebus.com/)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
OS Dev <https://wiki.osdev.org/Categorized_Main_Page>
|
||||
Interface BUS <http://www.interfacebus.com/>
|
||||
```
|
||||
|
||||
## OpenSecurityTraining2
|
||||
|
||||
@@ -43,10 +51,14 @@ modified works back to the community.
|
||||
Below is a list of currently available courses that can help understand the
|
||||
inner workings of coreboot and other firmware-related topics:
|
||||
|
||||
* [coreboot design principles and boot process](https://ost2.fyi/Arch4031)
|
||||
* [x86-64 Assembly](https://ost2.fyi/Arch1001)
|
||||
* [x86-64 OS Internals](https://ost2.fyi/Arch2001)
|
||||
* [x86-64 Intel Firmware Attack & Defense](https://ost2.fyi/Arch4001)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
coreboot design principles and boot process <https://ost2.fyi/Arch4031>
|
||||
x86-64 Assembly <https://ost2.fyi/Arch1001>
|
||||
x86-64 OS Internals <https://ost2.fyi/Arch2001>
|
||||
x86-64 Intel Firmware Attack & Defense <https://ost2.fyi/Arch4001>
|
||||
```
|
||||
|
||||
There are [additional security courses](https://p.ost2.fyi/courses) at the site
|
||||
as well (such as
|
||||
@@ -54,47 +66,79 @@ as well (such as
|
||||
|
||||
## Firmware Specifications & Information
|
||||
|
||||
* [System Management BIOS - SMBIOS](https://www.dmtf.org/standards/smbios)
|
||||
* [Desktop and Mobile Architecture for System Hardware - DASH](https://www.dmtf.org/standards/dash)
|
||||
* [PNP BIOS](https://www.intel.com/content/dam/support/us/en/documents/motherboards/desktop/sb/pnpbiosspecificationv10a.pdf)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
System Management BIOS - SMBIOS <https://www.dmtf.org/standards/smbios>
|
||||
Desktop and Mobile Architecture for System Hardware - DASH <https://www.dmtf.org/standards/dash>
|
||||
PNP BIOS <https://www.intel.com/content/dam/support/us/en/documents/motherboards/desktop/sb/pnpbiosspecificationv10a.pdf>
|
||||
```
|
||||
|
||||
|
||||
### ACPI
|
||||
|
||||
* [ACPI Specs](https://uefi.org/acpi/specs)
|
||||
* [ACPI in Linux](https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf)
|
||||
* [ACPI 5 Linux](https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-ACPI5.pdf)
|
||||
* [ACPI 6 Linux](https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_Linux_0.pdf)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
ACPI Specs <https://uefi.org/acpi/specs>
|
||||
ACPI in Linux <https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf>
|
||||
ACPI 5 Linux <https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-ACPI5.pdf>
|
||||
ACPI 6 Linux <https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_Linux_0.pdf>
|
||||
```
|
||||
|
||||
|
||||
### Security
|
||||
|
||||
* [Intel Boot Guard](https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Intel Boot Guard <https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard>
|
||||
```
|
||||
|
||||
|
||||
## Hardware information
|
||||
|
||||
* [WikiChip](https://en.wikichip.org/wiki/WikiChip)
|
||||
* [Sandpile](https://www.sandpile.org/)
|
||||
* [CPU-World](https://www.cpu-world.com/index.html)
|
||||
* [CPU-Upgrade](https://www.cpu-upgrade.com/index.html)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
WikiChip <https://en.wikichip.org/wiki/WikiChip>
|
||||
Sandpile <https://www.sandpile.org/>
|
||||
CPU-World <https://www.cpu-world.com/index.html>
|
||||
CPU-Upgrade <https://www.cpu-upgrade.com/index.html>
|
||||
```
|
||||
|
||||
|
||||
### Hardware Specifications & Standards
|
||||
|
||||
* [Bluetooth](https://www.bluetooth.com/specifications/specs/) - Bluetooth SIG
|
||||
* [eMMC](https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
eMMC <https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED>
|
||||
```
|
||||
* [eSPI](https://cdrdv2.intel.com/v1/dl/getContent/645987) - Intel
|
||||
* [I2c Spec](https://web.archive.org/web/20170704151406/https://www.nxp.com/docs/en/user-guide/UM10204.pdf),
|
||||
[Appnote](https://www.nxp.com/docs/en/application-note/AN10216.pdf) - NXP
|
||||
* [I2S](https://www.nxp.com/docs/en/user-manual/UM11732.pdf) - NXP
|
||||
* [I3C](https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED)
|
||||
* [Memory](https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
I3C <https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED>
|
||||
Memory <https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED>
|
||||
```
|
||||
* [NVMe](https://nvmexpress.org/developers/) - NVMe Specifications
|
||||
* [LPC](https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf) - Intel
|
||||
* [PCI / PCIe / M.2](https://pcisig.com/specifications) - PCI-SIG - (LOGIN REQUIRED)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
PCI / PCIe / M.2 <https://pcisig.com/specifications) - PCI-SIG - (LOGIN REQUIRED>
|
||||
```
|
||||
* [Power Delivery](https://www.usb.org/documents) - USB Implementers Forum
|
||||
* [SATA](https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
SATA <https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED>
|
||||
```
|
||||
* [SMBus](http://www.smbus.org/specs/) - System Management Interface Forum
|
||||
* [Smart Battery](http://smartbattery.org/specs/) - Smart Battery System Implementers Forum
|
||||
* [USB](https://www.usb.org/documents) - USB Implementers Forum
|
||||
@@ -133,5 +177,9 @@ as well (such as
|
||||
|
||||
## Infrastructure software
|
||||
|
||||
* [Kconfig](https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html)
|
||||
* [GNU Make](https://www.gnu.org/software/make/manual/)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Kconfig <https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html>
|
||||
GNU Make <https://www.gnu.org/software/make/manual/>
|
||||
```
|
||||
|
@@ -7,10 +7,10 @@ to the point of providing its own custom language.
|
||||
The overhead of learning this new syntax is (hopefully) offset by its lower
|
||||
complexity.
|
||||
|
||||
The build system is defined in the toplevel `Makefile` and `toolchain.inc`
|
||||
The build system is defined in the toplevel `Makefile` and `toolchain.mk`
|
||||
and is supposed to be generic (and is in fact used with a number of other
|
||||
projects). Project specific configuration should reside in files called
|
||||
`Makefile.inc`.
|
||||
`Makefile.mk`.
|
||||
|
||||
In general, the build system provides a number of "classes" that describe
|
||||
various parts of the build. These cover the various build targets in coreboot
|
||||
@@ -36,7 +36,7 @@ TODO: explain how to create new classes and how to evaluate them.
|
||||
### subdirs
|
||||
`subdirs` contains subdirectories (relative to the current directory) that
|
||||
should also be handled by the build system. The build system expects these
|
||||
directories to contain a file called `Makefile.inc`.
|
||||
directories to contain a file called `Makefile.mk`.
|
||||
|
||||
Subdirectories are not read at the point where the `subdirs` statement
|
||||
resides but later, after the current directory is handled (and potentially
|
||||
@@ -66,7 +66,7 @@ supported options are:
|
||||
|
||||
You can use the `add_intermediate` helper to add new post-processing steps for
|
||||
the final `coreboot.rom` image. For example you can add new files to CBFS by
|
||||
adding something like this to `site-local/Makefile.inc`
|
||||
adding something like this to `site-local/Makefile.mk`
|
||||
|
||||
```
|
||||
$(call add_intermediate, add_mrc_data)
|
||||
@@ -75,7 +75,7 @@ $(call add_intermediate, add_mrc_data)
|
||||
|
||||
Note that the second line must start with a tab, not spaces.
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
See also :doc:`../tutorial/managing_local_additions`.
|
||||
```
|
||||
|
||||
@@ -100,4 +100,4 @@ The default implementation just returns `COREBOOT` (the default region) for
|
||||
all files.
|
||||
|
||||
vboot provides its own implementation of `regions-for-file` that can be used
|
||||
as reference in `src/vboot/Makefile.inc`.
|
||||
as reference in `src/vboot/Makefile.mk`.
|
||||
|
312
Documentation/getting_started/faq.md
Normal file
312
Documentation/getting_started/faq.md
Normal file
@@ -0,0 +1,312 @@
|
||||
# coreboot FAQ
|
||||
|
||||
## General coreboot questions
|
||||
|
||||
|
||||
### What is coreboot?
|
||||
|
||||
coreboot is a free and open software project designed to initialize
|
||||
computers and embedded systems in a fast, secure, and auditable fashion.
|
||||
The focus is on minimal hardware initialization: to do only what is
|
||||
absolutely needed, then pass control to other software (a payload, in
|
||||
coreboot parlance) in order to boot the operating system securely.
|
||||
|
||||
|
||||
### What is a coreboot payload?
|
||||
|
||||
coreboot itself does not deal with boot media such as hard-drives,
|
||||
SSDs, or USB flash-drives, beyond initializing the underlying hardware.
|
||||
So in order to actually boot an operating system, another piece of
|
||||
software which does do those things must be used. coreboot supports
|
||||
a large number of diverse payloads; see below for more details.
|
||||
|
||||
|
||||
### Is coreboot the same as UEFI?
|
||||
|
||||
No. coreboot and UEFI are both system firmware that handle the
|
||||
initialization of the hardware, but are otherwise not similar.
|
||||
coreboot’s goal is to **just** initialize the hardware and exit.
|
||||
This makes coreboot smaller and simpler, leading to faster boot times,
|
||||
and making it easier to find and fix bugs. The result is a higher
|
||||
overall security.
|
||||
|
||||
|
||||
### What's the difference between coreboot and UEFI?
|
||||
|
||||
UEFI is actually a firmware specification, not a specific software
|
||||
implementation. Intel, along with the rest of the Tianocore project,
|
||||
has released an open-source implementation of the overall framework,
|
||||
EDK2, but it does not come with hardware support. Most hardware running
|
||||
UEFI uses a proprietary implementation built on top of EDK2.
|
||||
|
||||
coreboot does not implement the UEFI specification, but it can be used to
|
||||
initialize the system, then launch a UEFI payload such as EDK2 in order
|
||||
to provide UEFI boot services.
|
||||
|
||||
The UEFI specification also defines and allows for many things that are
|
||||
outside of coreboot’s scope, including (but not limited to):
|
||||
|
||||
* Boot device selection
|
||||
* Updating the firmware
|
||||
* A CLI shell
|
||||
* Network communication
|
||||
* An integrated setup menu
|
||||
|
||||
|
||||
### Can coreboot boot operating systems that require UEFI?
|
||||
|
||||
Yes, but... again, coreboot **just** initializes the hardware. coreboot
|
||||
itself doesn’t load operating systems from storage media other than the
|
||||
flash chip. Unlike UEFI, coreboot does not, and will not contain a Wi-Fi
|
||||
driver or communicate directly with any sort of network. That sort of
|
||||
functionality is not related to hardware initialization.
|
||||
|
||||
To boot operating systems that require UEFI, coreboot can be compiled with
|
||||
EDK2 as the payload. This allows coreboot to perform the hardware init,
|
||||
with EDK2 supplying the UEFI boot interface and runtime services to
|
||||
the operating system.
|
||||
|
||||
|
||||
### What non-UEFI payloads does coreboot support?
|
||||
|
||||
* SeaBIOS, behaves like a classic BIOS, allowing you to boot operating
|
||||
systems that rely on the legacy interrupts.
|
||||
|
||||
* GRUB can be used as a coreboot payload, and is currently the most
|
||||
common approach to full disk encryption (FDE).
|
||||
|
||||
* A Linux kernel and initramfs stored alongside coreboot in the boot
|
||||
ROM can also be used as a payload. In this scenario coreboot
|
||||
initializes hardware, loads Linux from boot ROM into RAM, and
|
||||
executes it. The embedded Linux environment can look for a target OS
|
||||
kernel to load from local storage or over a network and execute it
|
||||
using kexec. This is sometimes called LinuxBoot.
|
||||
|
||||
* U-boot, depthcharge, FILO, etc.
|
||||
|
||||
There’s [https://doc.coreboot.org/payloads.html](https://doc.coreboot.org/payloads.html)
|
||||
with a list, although it’s not complete.
|
||||
|
||||
|
||||
### What does coreboot leave in memory after it's done initializing the hardware?
|
||||
|
||||
While coreboot tries to remove itself completely from memory after
|
||||
finishing, some tables and data need to remain for the OS. coreboot
|
||||
reserves an area in memory known as CBMEM, to save this data after it
|
||||
has finished booting. This contains things such as the boot log, tables
|
||||
that get passed to the payload, SMBIOS, and ACPI tables for the OS.
|
||||
|
||||
In addition to CBMEM, on X86 systems, coreboot will typically set up
|
||||
SMM, which will remain resident after coreboot exits.
|
||||
|
||||
|
||||
## Platforms
|
||||
|
||||
### What’s the best coreboot platform for a user?
|
||||
|
||||
The choice of the best coreboot platform for a user can vary depending
|
||||
on their specific needs, preferences, and use cases.
|
||||
|
||||
Typically, people who want a system with a minimum of proprietary
|
||||
firmware are restricted to older systems like the Lenovo X220, or more
|
||||
expensive, non-x86 solutions like TALOS, from Raptor Engineering.
|
||||
|
||||
There are a number of companies selling modern systems, but those all
|
||||
require more proprietary binaries in addition to coreboot (e.g., Intel
|
||||
FSP). However, unlike the older ThinkPads, many of these newer devices
|
||||
use open-source embedded controller (EC) firmware, so there are
|
||||
tradeoffs with either option.
|
||||
|
||||
The coreboot project mantains a list of companies selling machines
|
||||
which use coreboot on the [website](https://coreboot.org/users.html).
|
||||
|
||||
|
||||
### What’s the best platform for coreboot development?
|
||||
|
||||
Similar to the best platform for users, the best platform for
|
||||
developers very much depends on what a developer is trying to do.
|
||||
|
||||
* QEMU is generally the easiest platform for coreboot development, just
|
||||
because it’s easy to run anywhere. However, it’s possible for things
|
||||
to work properly in QEMU but fail miserably on actual hardware.
|
||||
|
||||
While laptops tend to be harder to develop than desktop platforms, a
|
||||
majority of newer platforms on coreboot tend to be laptops. The
|
||||
development difficulty is due to a few different factors:
|
||||
|
||||
1. The EC (Embedded Controller) is a specialized microcontroller that
|
||||
typically handles keyboard and sometimes mouse input for a laptop.
|
||||
It also controls many power management functions such as fans, USB-C
|
||||
power delivery, etc. ECs run mainboard-specific firmware, which is
|
||||
typically undocumented.
|
||||
2. ThinkPads (X230, 30-series, 20-series, T430, T540, T520). Sandy
|
||||
Bridge and Ivy Bridge are well-supported. Some may have
|
||||
difficult-to-reach SPI flash chips. Boards with two flash chips (e.g.
|
||||
30-series ThinkPads) are harder to externally reflash as one needs to
|
||||
make sure the non-targeted flash chip remains disabled at all times.
|
||||
The X230 is notoriously sensitive to external reflashing issues.
|
||||
3. Laptops often lack a convenient method to obtain firmware boot logs.
|
||||
One can use EHCI debug on older systems and Chromebook-specific
|
||||
solutions for Chromebooks, but one often has to resort to flashconsole
|
||||
(writing coreboot logs to the flash chip where coreboot resides). On
|
||||
the other hand, several desktop mainboards still have a RS-232 serial
|
||||
port.
|
||||
|
||||
Some of the easiest physical systems to use for coreboot development
|
||||
are Chromebooks. Newer Chromebooks allow for debug without opening the
|
||||
case. Look for SuzyQ Cables or SuzyQables or instructions on how to
|
||||
build one. These cables only work on a specific port in a specific
|
||||
orientation. Google [supplies
|
||||
specifications](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/master/docs/ccd.md#SuzyQ-SuzyQable)
|
||||
for these cables.
|
||||
|
||||
|
||||
### What platforms does coreboot support?
|
||||
|
||||
The most accurate way to determine what systems coreboot supports is by
|
||||
browsing the src/mainboard tree or running “make menuconfig” and going
|
||||
through the “Mainboard” submenu. You can also search Gerrit to see if
|
||||
there are any unmerged ports for your board.
|
||||
|
||||
There is also the board status page
|
||||
([https://coreboot.org/status/board-status.html](https://coreboot.org/status/board-status.html)),
|
||||
however this does not currently show supported board variants.
|
||||
|
||||
|
||||
## coreboot Development
|
||||
|
||||
### Can coreboot be ported to [this board]?
|
||||
|
||||
The best way to determine if coreboot can be ported to a system is to
|
||||
see if the processor and chipset is supported. The next step is to see
|
||||
whether the system is locked to the proprietary firmware which comes
|
||||
with the board.
|
||||
|
||||
Intel Platforms:
|
||||
|
||||
* coreboot only supports a few northbridges (back when northbridges
|
||||
were on a separate package), and there's next to no support for
|
||||
"server" platforms (multi-socket and similar things). Here's a list
|
||||
of more recent supported Intel processors:
|
||||
* Alder Lake (2021 - Core Gen 12)
|
||||
* Apollo Lake (2016 - Atom)
|
||||
* Baytrail (2014 - Atom)
|
||||
* Braswell (2016 - Atom)
|
||||
* Broadwell (2014 - Core Gen 5)
|
||||
* Comet Lake (2019 - Core Gen 10)
|
||||
* Cannon Lake (2018 - Core Gen 8/9)
|
||||
* Denverton (2017)
|
||||
* Elkhart lake (2021 - Atom)
|
||||
* Haswell (2013 - Core Gen 4)
|
||||
* Ivy Bridge (2012 - Core Gen 3)
|
||||
* Jasper Lake (2021 - Atom)
|
||||
* Kaby Lake (2016 - Core Gen 7/8)
|
||||
* Meteor Lake (2023 - Gen 1 Ultra-mobile)
|
||||
* Sandy Bridge (2011 - Core Gen 2)
|
||||
* Sky Lake (2015 - Core Gen 6)
|
||||
* Tiger Lake (2020 - Core Gen 11)
|
||||
* Whiskey Lake (2018 - Core Gen 8)
|
||||
|
||||
* Intel Boot Guard is a security feature which tries to prevent loading
|
||||
unauthorized firmware by the mainboard. If supported by the platform,
|
||||
and the platform is supported by intelmetool, you should check if Boot
|
||||
Guard is enabled. If it is, then getting coreboot to run will be
|
||||
difficult or impossible even if it is ported. You can run
|
||||
`intelmetool -b` on supported platforms to see if Boot Guard is
|
||||
enabled (although it can fail because it wants to probe the ME
|
||||
beforehand).
|
||||
|
||||
AMD Ryzen-based platforms:
|
||||
|
||||
* The AMD platforms Ryzen-based platforms unfortunately are currently
|
||||
not well supported outside of the Chromebooks (and AMD reference
|
||||
boards) currently in the tree.
|
||||
The responsible teams are trying to fix this, but currently it's
|
||||
**very** difficult to do a new port. Recent supported SoCs:
|
||||
* Stoney Ridge
|
||||
* Picasso
|
||||
* Cezanne
|
||||
* Mendocino
|
||||
* Phoenix
|
||||
|
||||
General notes:
|
||||
|
||||
* Check the output of `lspci` to determine what processor/chipset
|
||||
family your system has. Processor/chipset support is the most
|
||||
important to determine if a board can be ported.
|
||||
* Check the output of `superiotool` to see if it detects the Super I/O
|
||||
on the system. You can also check board schematics and/or boardviews
|
||||
if you can find them, or physically look at the mainboard for a chip
|
||||
from one of the common superio vendors.
|
||||
* Check what EC your system has (mostly applicable to laptops, but some
|
||||
desktops have EC-like chips). You will likely need to refer to the
|
||||
actual board or schematics/boardviews for this. Physical observation
|
||||
is the most accurate identification procedure; software detection can
|
||||
then be used to double-check if the chip is correct, but one should
|
||||
not rely on software detection alone to identify an EC.
|
||||
|
||||
|
||||
### How do I port coreboot to [this board]?
|
||||
|
||||
A critical piece for anyone attempting to do a board port is to make
|
||||
sure that you have a method to recover your system from a failed flash.
|
||||
|
||||
We need an updated motherboard porting guide, but currently the guide
|
||||
on the [wiki](https://www.coreboot.org/Motherboard_Porting_Guide) looks
|
||||
to be the best reference.
|
||||
|
||||
At the moment, the best answer to this question is to ask for help on
|
||||
one of the [various community
|
||||
forums](https://doc.coreboot.org/community/forums.html).
|
||||
|
||||
|
||||
### What about the Intel ME?
|
||||
|
||||
There seems to be a lot of FUD about what the ME can and can’t do.
|
||||
coreboot currently does not have a clear recommendation on how to
|
||||
handle the ME. We understand that there are serious concerns about the
|
||||
ME, and would like to flatly recommend removing as much as possible,
|
||||
however modifying the ME can cause serious stability issues.
|
||||
|
||||
Additionally, coreboot and the Intel ME are completely separate entites
|
||||
which in many cases simply happen to occupy the same flash chip. It is
|
||||
not necessary to run coreboot to modify the ME, and running coreboot
|
||||
does not imply anything about the ME's operational state.
|
||||
|
||||
|
||||
#### A word of caution about the modifying ME
|
||||
|
||||
Messing with the ME firmware can cause issues, and this is outside the
|
||||
scope of the coreboot project.
|
||||
|
||||
If you do decide to modify the ME firmware, please make sure coreboot
|
||||
works **before** messing with it. Even if the vendor boot firmware
|
||||
works when the ME isn't operating normally, it's possible that coreboot
|
||||
doesn't handle it the same way and something breaks. If someone asks
|
||||
for help with coreboot and we think the ME state may be a factor, we'll
|
||||
ask them to try reproducing the issue with the ME running normally to
|
||||
reduce the number of variables involved. This is especially important
|
||||
when flashing coreboot for the first time, as it's best for newbies to
|
||||
start with small steps: start by flashing coreboot to the BIOS region
|
||||
and leaving the remaining regions untouched, then tinker around with
|
||||
coreboot options (e.g. other payloads, bootsplash, RAM overclock...),
|
||||
or try messing with the ME firmware **without changing coreboot**.
|
||||
|
||||
Most people don't understand the implications of messing with the ME
|
||||
firmware, especially the use of `me_cleaner`. We admit that we don't
|
||||
know everything about the ME, but we try to understand it as much as
|
||||
possible. The ME is designed to operate correctly with the HAP (or
|
||||
AltMeDisable) bit set, and it will gracefully enter a debug state (not
|
||||
normal, but not an error). However, when using `me_cleaner` to remove
|
||||
parts of the ME firmware, the ME will often end up in an error state
|
||||
because parts of its FW are missing. It is known that removing some of
|
||||
these parts ([`EFFS` and `FCRS` on Cougar Point,
|
||||
c.f.](https://review.coreboot.org/c/coreboot/+/27798/6/src/mainboard/asus/p8h61-m_lx/Kconfig#63))
|
||||
can cause problems. We do not know whether the state the ME ends up in
|
||||
after applying `me_cleaner` is as secure as the state the ME goes to
|
||||
when only the HAP bit is set: the removed FW modules could contain
|
||||
steps to lock down important settings for security reasons.
|
||||
|
||||
To sum up, **we do not recommend messing with the ME firmware**. But if
|
||||
you have to, please use `ifdtool` to set the HAP bit initially before
|
||||
progressing to `me_cleaner` if necessary.
|
@@ -167,7 +167,7 @@ could cause catastrophic failures, up to and including your mainboard!
|
||||
As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register
|
||||
supports four different types of GPIO reset as:
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------------+----------------+-------------+-------------+
|
||||
| | | PAD Reset ? |
|
||||
+ PAD Reset Config + Platform Reset +-------------+-------------+
|
||||
|
@@ -1,9 +1,14 @@
|
||||
# Getting Started
|
||||
|
||||
* [coreboot architecture](architecture.md)
|
||||
* [Build System](build_system.md)
|
||||
* [Submodules](submodules.md)
|
||||
* [Kconfig](kconfig.md)
|
||||
* [Writing Documentation](writing_documentation.md)
|
||||
* [Setting up GPIOs](gpio.md)
|
||||
* [Adding devices to a device tree](devicetree.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
coreboot architecture <architecture.md>
|
||||
Build System <build_system.md>
|
||||
Submodules <submodules.md>
|
||||
Kconfig <kconfig.md>
|
||||
Writing Documentation <writing_documentation.md>
|
||||
Setting up GPIOs <gpio.md>
|
||||
Adding devices to a device tree <devicetree.md>
|
||||
Frequently Asked Questions <faq.md>
|
||||
```
|
||||
|
@@ -11,8 +11,12 @@ configuration front end in coreboot today.
|
||||
|
||||
The official Kconfig source and documentation is kept at kernel.org:
|
||||
|
||||
- [Kconfig source](https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/scripts/kconfig)
|
||||
- [Kconfig Language Documentation](https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Kconfig source <https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/scripts/kconfig>
|
||||
Kconfig Language Documentation <https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt>
|
||||
```
|
||||
|
||||
The advantage to using Kconfig is that it allows users to easily select the
|
||||
high level features of the project to be enabled or disabled at build time.
|
||||
@@ -69,9 +73,6 @@ These variables are typically set in the makefiles or on the make command line.
|
||||
These variables were added to Kconfig specifically for coreboot and are not
|
||||
included in the Linux version.
|
||||
|
||||
- KCONFIG_STRICT=value. Define to enable warnings as errors. This is enabled
|
||||
in coreboot, and should not be changed.
|
||||
|
||||
- KCONFIG_NEGATIVES=value. Define to show negative values in the autoconf.h file
|
||||
(build/config.h). This is enabled in coreboot, and should not be changed.
|
||||
|
||||
@@ -102,6 +103,9 @@ included in the Linux version.
|
||||
- KCONFIG_SPLITCONFIG=”directory name for individual SYMBOL.h files”.
|
||||
coreboot sets this to $(obj)/config.
|
||||
|
||||
- KCONFIG_WERROR=value. Define to enable warnings as errors. This is enabled
|
||||
in coreboot, and should not be changed.
|
||||
|
||||
#### Used only for ‘make menuconfig’
|
||||
- MENUCONFIG_MODE=single_menu. Set to "single_menu" to enable. All other
|
||||
values disable the option. This makes submenus appear below the menu option
|
||||
@@ -196,9 +200,9 @@ values to be set based on other values.
|
||||
visible in the front end.
|
||||
|
||||
|
||||
## Keywords
|
||||
### Keywords
|
||||
|
||||
### bool
|
||||
#### bool
|
||||
|
||||
The 'bool' keyword assigns a boolean type to a symbol. The allowable values for
|
||||
a boolean type are 'n' or 'y'. The keyword can be followed by an optional prompt
|
||||
@@ -234,7 +238,7 @@ bool \[prompt\] \[if <expr>\]
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### choice
|
||||
#### choice
|
||||
|
||||
This creates a selection list of one or more boolean symbols. For bools, only
|
||||
one of the symbols can be selected, and one will be be forced to be selected,
|
||||
@@ -297,7 +301,7 @@ choice \[symbol\]
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### comment
|
||||
#### comment
|
||||
|
||||
This keyword defines a line of text that is displayed to the user in the
|
||||
configuration frontend and is additionally written to the output files.
|
||||
@@ -322,7 +326,7 @@ comment <prompt>
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### config
|
||||
#### config
|
||||
|
||||
This is the keyword that starts a block defining a Kconfig symbol. The symbol
|
||||
modifiers follow the 'config' statement.
|
||||
@@ -359,7 +363,7 @@ config <symbol>
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### default
|
||||
#### default
|
||||
|
||||
The ‘default’ keyword assigns a value to a symbol in the case where no preset
|
||||
value exists, i.e. the symbol is not present and assigned in .config. If there
|
||||
@@ -399,7 +403,7 @@ default <expr> \[if <expr>\]
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### def_bool
|
||||
#### def_bool
|
||||
|
||||
‘def_bool’ is similar to the 'bool' keyword in that it sets a symbol’s type to
|
||||
boolean. It lets you set the type and default value at the same time, instead
|
||||
@@ -433,7 +437,7 @@ def_bool <expr> \[if <expr>\]
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### depends on
|
||||
#### depends on
|
||||
|
||||
This defines a dependency for a menu entry, including symbols and comments. It
|
||||
behaves the same as surrounding the menu entry with an if/endif block. If the
|
||||
@@ -462,28 +466,28 @@ depends on <expr>
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### endchoice
|
||||
#### endchoice
|
||||
|
||||
This ends a choice block. See the 'choice' keyword for more information and an
|
||||
example.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### endif
|
||||
#### endif
|
||||
|
||||
This ends a block started by the 'if' keyword. See the 'if' keyword for more
|
||||
information and an example.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### endmenu
|
||||
#### endmenu
|
||||
|
||||
This ends a menu block. See the 'menu' keyword for more information and an
|
||||
example.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### help
|
||||
#### help
|
||||
|
||||
The 'help' keyword defines the subsequent block of text as help for a config or
|
||||
choice block. The help block is started by the 'help' keyword on a line by
|
||||
@@ -515,7 +519,7 @@ help <help text>
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### hex
|
||||
#### hex
|
||||
|
||||
This is another symbol type specifier, specifying an unsigned integer value
|
||||
formatted as hexadecimal.
|
||||
@@ -551,7 +555,7 @@ hex <expr> \[if <expr>\]
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### if
|
||||
#### if
|
||||
|
||||
The 'if' keyword is overloaded, used in two different ways. The first definition
|
||||
enables and disables various other keywords, and follows the other keyword
|
||||
@@ -592,7 +596,7 @@ endif
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### int
|
||||
#### int
|
||||
|
||||
A type setting keyword, defines a symbol as an integer, accepting only signed
|
||||
numeric values. The values can be further restricted with the ‘range’ keyword.
|
||||
@@ -628,7 +632,7 @@ int <expr> \[if <expr>\]
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### mainmenu
|
||||
#### mainmenu
|
||||
|
||||
The 'mainmenu' keyword sets the title or title bar of the configuration front
|
||||
end, depending on how the configuration program decides to use it. It can only
|
||||
@@ -648,7 +652,7 @@ mainmenu "coreboot configuration"
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### menu
|
||||
#### menu
|
||||
|
||||
The 'menu' and 'endmenu' keywords tell the configuration front end that the
|
||||
enclosed statements are part of a group of related pieces.
|
||||
@@ -695,7 +699,7 @@ endmenu
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### prompt
|
||||
#### prompt
|
||||
|
||||
The 'prompt' keyword sets the text displayed for a config symbol or choice in
|
||||
configuration front end.
|
||||
@@ -748,7 +752,7 @@ prompt <prompt> \[if <expr>\]
|
||||
prompt "Prompt value 2"
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### range
|
||||
#### range
|
||||
|
||||
This sets the allowable minimum and maximum entries for hex or int type config
|
||||
symbols.
|
||||
@@ -770,7 +774,7 @@ range <symbol> <symbol> \[if <expr>\]
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### select
|
||||
#### select
|
||||
|
||||
The ‘select’ keyword is used within a bool type config block. In coreboot (and
|
||||
other projects that don't use modules), the 'select' keyword can force an
|
||||
@@ -814,7 +818,7 @@ select <symbol> \[if <expr>\]
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### source
|
||||
#### source
|
||||
|
||||
The 'source' keyword functions much the same as an 'include' statement in c.
|
||||
This pulls one or more files into Kconfig at the location of the 'source'
|
||||
@@ -873,7 +877,7 @@ statements that generate a list of all the platform names:
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
### string
|
||||
#### string
|
||||
|
||||
The last of the symbol type assignment keywords. 'string' allows a text value to
|
||||
be entered.
|
||||
@@ -919,7 +923,7 @@ keyword later. See the prompt keyword for more notes.
|
||||
|
||||
|
||||
|
||||
## Keywords not used in coreboot at the time of writing:
|
||||
### Keywords not used in coreboot at the time of writing:
|
||||
|
||||
- allnoconfig_y:
|
||||
- defconfig_list
|
||||
@@ -944,7 +948,7 @@ statements:
|
||||
#define SYMBOL NAME XXX
|
||||
|
||||
|
||||
##### Symbol types:
|
||||
#### Symbol types:
|
||||
- bool, int, and hex types - Every symbol of one of these types created in the
|
||||
Kconfig tree is defined. It doesn’t matter whether they’re in an if/endif
|
||||
block, or have a ‘depends on’ statement - they ALL end up being defined in
|
||||
@@ -963,7 +967,7 @@ variable. This is not set in coreboot, which uses the default CONFIG_ prefix
|
||||
for all of its symbols.
|
||||
|
||||
The coreboot makefile forces the config.h file to be included into all coreboot
|
||||
C files. This is done in Makefile.inc on the compiler command line using the
|
||||
C files. This is done in Makefile.mk on the compiler command line using the
|
||||
“-include $(obj)/config.h” command line option.
|
||||
|
||||
Example of various symbol types in the config.h file:
|
||||
@@ -1160,27 +1164,23 @@ saved .config file. As always, a 'select' statement overrides any specified
|
||||
- coreboot has added the glob operator '*' for the 'source' keyword.
|
||||
- coreboot’s Kconfig always defines variables except for strings. In other
|
||||
Kconfig implementations, bools set to false/0/no are not defined.
|
||||
- coreboot’s version of Kconfig adds the KCONFIG_STRICT environment variable to
|
||||
error out if there are any issues in the Kconfig files. In the Linux kernel,
|
||||
Kconfig will generate a warning, but will still output an updated .config or
|
||||
config.h file.
|
||||
|
||||
|
||||
## Kconfig Editor Highlighting
|
||||
|
||||
#### vim:
|
||||
### vim:
|
||||
|
||||
vim has syntax highlighting for Kconfig built in (or at least as a part of
|
||||
vim-common), but most editors do not.
|
||||
|
||||
|
||||
#### ultraedit:
|
||||
### ultraedit:
|
||||
|
||||
https://github.com/martinlroth/wordfiles/blob/master/kconfig.uew
|
||||
|
||||
|
||||
|
||||
#### atom:
|
||||
### atom:
|
||||
|
||||
https://github.com/martinlroth/language-kconfig
|
||||
|
||||
|
@@ -99,7 +99,7 @@ To reference documents use the TOC tree or inline RST code.
|
||||
Under Sphinx markdown tables are not supported. Therefore you can use following
|
||||
code block to write tables in reStructuredText and embed them into the markdown:
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------+------------+-----------+
|
||||
| Header 1 | Header 2 | Header 3 |
|
||||
+============+============+===========+
|
||||
@@ -144,7 +144,7 @@ you'll see the following warning:
|
||||
You can import CSV files and let sphinx automatically convert them to human
|
||||
readable tables, using the following reStructuredText snipped:
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
.. csv-table::
|
||||
:header: "Key", "Value"
|
||||
:file: keyvalues.csv
|
||||
|
@@ -22,7 +22,7 @@ the power sequence timing parameters, which are usually named T[N] and also
|
||||
referenced in Intel's respective registers listing. You need the values for
|
||||
`PP_ON_DELAYS`, `PP_OFF_DELAYS` and `PP_DIVISOR` for your `devicetree.cb`:
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+-----------------------------+---------------------------------------+-----+
|
||||
| Intel docs | devicetree.cb | eDP |
|
||||
+-----------------------------+---------------------------------------+-----+
|
||||
|
@@ -139,6 +139,45 @@ Every now and then, coreboot is present in one way or another at
|
||||
[conferences](community/conferences.md). If you're around, come and
|
||||
say hello!
|
||||
|
||||
## Blob policy in the coreboot project
|
||||
|
||||
The goal of the coreboot project is to provide a FOSS firmware solution across
|
||||
multiple CPU architectures, such as ARM, x86, and RISC-V. While fully open
|
||||
source implementations for these architectures are encouraged and preferred,
|
||||
we understand that a fully open implementation whereby every firmware component
|
||||
is available as source code for modern platforms is not always feasible.
|
||||
Different reasons inhibit the availability of fully open implementations,
|
||||
including limited development resources, 3rd party license constraints of
|
||||
IP blocks, or a legacy mindset of the silicon vendors.
|
||||
|
||||
It is important for the coreboot project to have support for modern CPU
|
||||
platforms in order to provide a viable alternative for proprietary firmware
|
||||
implementations. We do not have direct control over how hardware vendors design
|
||||
their products, however we can provide an attractive alternative to the
|
||||
expensive and complicated proprietary firmware model that exists today.
|
||||
For modern platforms, we are largely dependent on the silicon
|
||||
vendor to provide additional information on how to properly initialize the
|
||||
hardware, as the required datasheets are often only available with an NDA.
|
||||
Therefore, one possible way to have coreboot support for the latest platforms
|
||||
is binary code (aka, a blob) provided by the silicon vendor. While we do
|
||||
discourage this solution, it can be a door opener for coreboot’s support of a
|
||||
given platform and thus keep coreboot functional on modern platforms. It is
|
||||
clearly not the goal of the project to accept every blob a silicon vendor wishes
|
||||
to use without question. On the contrary, each new blob needs to be examined
|
||||
critically by the community, evaluating the need, risk, and alternative options.
|
||||
|
||||
Wherever possible, introducing new blobs should be avoided. That said, there
|
||||
can be situations where a piece of code provided as a blob will enable the rest
|
||||
of the fully open source firmware stack on a brand new platform. If blocking
|
||||
this blob would lead to no support at all for the platform in question in
|
||||
coreboot, this situation needs to be examined carefully. While these kinds
|
||||
of discussion will be coordinated closely with the community (e.g. on the
|
||||
mailing list or dedicated meetings), ultimately it is up to the leadership to
|
||||
decide if there is no agreement between the community and the vendor pushing for
|
||||
the new blob. This decision will be communicated on the mailing list.
|
||||
Please see additionally
|
||||
[coreboot binary policy](https://github.com/coreboot/blobs/blob/master/README.md).
|
||||
|
||||
## Getting the source code
|
||||
|
||||
coreboot is primarily developed in the
|
||||
@@ -170,34 +209,38 @@ for example OpenBSD, is probably the closest cousin of our approach.
|
||||
|
||||
Contents:
|
||||
|
||||
* [Getting Started](getting_started/index.md)
|
||||
* [Tutorial](tutorial/index.md)
|
||||
* [Contributing](contributing/index.md)
|
||||
* [Community](community/index.md)
|
||||
* [Payloads](payloads.md)
|
||||
* [Distributions](distributions.md)
|
||||
* [Technotes](technotes/index.md)
|
||||
* [ACPI](acpi/index.md)
|
||||
* [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md)
|
||||
* [Display panel](gfx/display-panel.md)
|
||||
* [CPU Architecture](arch/index.md)
|
||||
* [Platform independent drivers](drivers/index.md)
|
||||
* [Northbridge](northbridge/index.md)
|
||||
* [System on Chip](soc/index.md)
|
||||
* [Mainboard](mainboard/index.md)
|
||||
* [Payloads](lib/payloads/index.md)
|
||||
* [Libraries](lib/index.md)
|
||||
* [Options](lib/option.md)
|
||||
* [Security](security/index.md)
|
||||
* [SuperIO](superio/index.md)
|
||||
* [Vendorcode](vendorcode/index.md)
|
||||
* [Utilities](util.md)
|
||||
* [Software Bill of Materials](sbom/sbom.md)
|
||||
* [Project infrastructure & services](infrastructure/index.md)
|
||||
* [Boards supported in each release directory](releases/boards_supported_on_branches.md)
|
||||
* [Release notes](releases/index.md)
|
||||
* [Acronyms & Definitions](acronyms.md)
|
||||
* [External Resources](external_docs.md)
|
||||
* [Documentation License](documentation_license.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Getting Started <getting_started/index.md>
|
||||
Tutorial <tutorial/index.md>
|
||||
Contributing <contributing/index.md>
|
||||
Community <community/index.md>
|
||||
Payloads <payloads.md>
|
||||
Distributions <distributions.md>
|
||||
Technotes <technotes/index.md>
|
||||
ACPI <acpi/index.md>
|
||||
Native Graphics Initialization with libgfxinit <gfx/libgfxinit.md>
|
||||
Display panel <gfx/display-panel.md>
|
||||
CPU Architecture <arch/index.md>
|
||||
Platform independent drivers <drivers/index.md>
|
||||
Northbridge <northbridge/index.md>
|
||||
System on Chip <soc/index.md>
|
||||
Mainboard <mainboard/index.md>
|
||||
Payloads <lib/payloads/index.md>
|
||||
Libraries <lib/index.md>
|
||||
Options <lib/option.md>
|
||||
Security <security/index.md>
|
||||
SuperIO <superio/index.md>
|
||||
Vendorcode <vendorcode/index.md>
|
||||
Utilities <util.md>
|
||||
Software Bill of Materials <sbom/sbom.md>
|
||||
Project infrastructure & services <infrastructure/index.md>
|
||||
Boards supported in each release directory <releases/boards_supported_on_branches.md>
|
||||
Release notes <releases/index.md>
|
||||
Acronyms & Definitions <acronyms.md>
|
||||
External Resources <external_docs.md>
|
||||
Documentation License <documentation_license.md>
|
||||
```
|
||||
|
||||
[Documentation]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/Documentation/
|
||||
|
52
Documentation/infrastructure/admin.md
Normal file
52
Documentation/infrastructure/admin.md
Normal file
@@ -0,0 +1,52 @@
|
||||
# Operating our services
|
||||
|
||||
## Mailing list moderation
|
||||
|
||||
Our [mailing lists] experience the same barrage of spam mails than any
|
||||
other email address. We do have a spam filter in front of it, and
|
||||
since the lists require registration, spam ends up in the moderation
|
||||
queue. But not only spam ends up there, sometimes users send inquiries
|
||||
without registering first. It's a custom of the project to let these
|
||||
through, so that such emails can be discussed. This requires manual
|
||||
intervention.
|
||||
|
||||
This section describes the tasks related to mailing list management.
|
||||
|
||||
### Registration
|
||||
|
||||
To participate in mailing list moderation, you need to become a list
|
||||
moderator or owner. This is up for the existing owners to handle and
|
||||
if you want to contribute in that area, it might be best to bring it
|
||||
up at the leadership meeting.
|
||||
|
||||
After gaining leadership approval, list admins can add you to the
|
||||
appropriate group in the [mailing list backend] by selecting the list,
|
||||
then User / group-name, and add your email address there.
|
||||
|
||||
### Regular tasks
|
||||
|
||||
Most of our lists are auto-subscribing, so users can register
|
||||
themselves and finish the process by responding to the double-opt-in
|
||||
email. Some lists are manually managed though. The [mailing list
|
||||
backend] shows the number of open subscription requests for these
|
||||
lists on the mailing list's main page.
|
||||
|
||||
It also provides a list of held messages, where they can be accepted,
|
||||
rejected or dropped. Spam should be dropped, that's clear. Emails with
|
||||
huge attachments (e.g. screenshots) should be rejected, which gives
|
||||
you an opportunity to explain the reason (in case of large
|
||||
attachments, something like "Please re-send without attachments, offer
|
||||
the files through some other mechanism please: Our emails are
|
||||
distributed to hundreds of readers, and sending the files to everybody
|
||||
is inconsiderate of traffic and storage constraints.")
|
||||
|
||||
Legit emails (often simple requests of the form "is this or that
|
||||
supported") can be accepted, which means they'll be sent out.
|
||||
|
||||
If you notice recurring spam sources (e.g. marketers) you can put them
|
||||
on the [global ban list] to filter them out across all lists. It takes
|
||||
entries in regular expression format.
|
||||
|
||||
[mailing lists]: https://mail.coreboot.org/hyperkitty/
|
||||
[mailing list backend]: https://mail.coreboot.org/postorius/
|
||||
[global ban list]: https://mail.coreboot.org/postorius/bans/
|
@@ -93,11 +93,19 @@ You can see all the builds in the main jenkins interface:
|
||||
Most of the time on the builders is taken up by the coreboot main and
|
||||
coreboot gerrit builds.
|
||||
|
||||
* [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
coreboot gerrit build <https://qa.coreboot.org/job/coreboot-gerrit/>
|
||||
```
|
||||
([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend))
|
||||
|
||||
|
||||
* [coreboot main build](https://qa.coreboot.org/job/coreboot/)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
coreboot main build <https://qa.coreboot.org/job/coreboot/>
|
||||
```
|
||||
([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend))
|
||||
|
||||
|
||||
|
@@ -4,9 +4,17 @@ This section contains documentation about our infrastructure
|
||||
|
||||
## Services
|
||||
|
||||
* [Project services](services.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Project services <services.md>
|
||||
Administrator's handbook <admin.md>
|
||||
```
|
||||
|
||||
## Jenkins builders and builds
|
||||
* [Setting up Jenkins build machines](builders.md)
|
||||
* [Coverity Scan integration](coverity.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Setting up Jenkins build machines <builders.md>
|
||||
Coverity Scan integration <coverity.md>
|
||||
```
|
||||
|
@@ -3,7 +3,11 @@
|
||||
This section contains documentation about coreboot internal technical
|
||||
information and libraries.
|
||||
|
||||
- [Flashmap and Flashmap Descriptor](flashmap.md)
|
||||
- [ABI data consumption](abi-data-consumption.md)
|
||||
- [Timestamps](timestamp.md)
|
||||
- [Firmware Configuration Interface](fw_config.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Flashmap and Flashmap Descriptor <flashmap.md>
|
||||
ABI data consumption <abi-data-consumption.md>
|
||||
Timestamps <timestamp.md>
|
||||
Firmware Configuration Interface <fw_config.md>
|
||||
```
|
||||
|
@@ -8,4 +8,8 @@ selected mainboard.
|
||||
|
||||
## FIT
|
||||
|
||||
- [uImage.FIT support](fit.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
uImage.FIT support <fit.md>
|
||||
```
|
||||
|
@@ -5,7 +5,7 @@ Acer models Aspire M3800, Aspire M5800 and possibly more.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | Intel G43 (called x4x in coreboot code) |
|
||||
+------------------+--------------------------------------------------+
|
||||
@@ -69,7 +69,7 @@ Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+-------------------+---------------------+
|
||||
| Type | Value |
|
||||
+===================+=====================+
|
||||
@@ -122,7 +122,7 @@ $ sudo flashrom \
|
||||
-w coreboot.rom
|
||||
```
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
In addition to the information here, please see the
|
||||
:doc:`../../tutorial/flashing_firmware/index`.
|
||||
```
|
||||
|
@@ -33,7 +33,7 @@ Three items are marked in this picture
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+--------------------+
|
||||
| Type | Value |
|
||||
+=====================+====================+
|
||||
@@ -53,7 +53,7 @@ Three items are marked in this picture
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------+------------------------------+
|
||||
| Fan control | Using fintek F81803A |
|
||||
+---------------+------------------------------+
|
||||
@@ -63,7 +63,7 @@ Three items are marked in this picture
|
||||
|
||||
## Description of pictures within this document
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+----------------------------+----------------------------------------+
|
||||
|pademelon.jpg | Motherboard with components identified |
|
||||
+----------------------------+----------------------------------------+
|
||||
|
@@ -11,7 +11,7 @@ Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/inde
|
||||
|
||||
FSP Information:
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+-----------------------------+-------------------+-------------------+
|
||||
| FSP Project Name | Directory | Specification |
|
||||
+-----------------------------+-------------------+-------------------+
|
||||
@@ -114,7 +114,7 @@ facing towards the bottom of the board.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| CPU | Intel Skylake/Kaby Lake (LGA1151) |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -5,7 +5,7 @@ Bridge and Ivy Bridge CPUs.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
|
||||
+------------------+--------------------------------------------------+
|
||||
@@ -71,7 +71,7 @@ extlinux
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+------------+
|
||||
| Type | Value |
|
||||
+=====================+============+
|
||||
@@ -115,7 +115,7 @@ $ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom
|
||||
The use of `--noverify-all` is required since the Management Engine
|
||||
region is not readable even by the host.
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
In addition to the information here, please see the
|
||||
:doc:`../../tutorial/flashing_firmware/index`.
|
||||
```
|
||||
|
@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASRock H81M-HDS].
|
||||
|
||||
## Required proprietary blobs
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
|
||||
```
|
||||
|
||||
@@ -75,7 +75,7 @@ facing towards the bottom of the board.
|
||||
in coreboot. The `coretemp` driver can still be used for accurate CPU
|
||||
temperature readings from an OS.
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
|
||||
```
|
||||
|
||||
@@ -111,7 +111,7 @@ Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | :doc:`../../northbridge/intel/haswell/index` |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -14,7 +14,7 @@ and their GPU is [Sea Islands] (GCN2-based).
|
||||
|
||||
A10 Richland is recommended for the best performance and working IOMMU.
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| A88XM-E | |
|
||||
+------------------+--------------------------------------------------+
|
||||
@@ -36,7 +36,7 @@ A10 Richland is recommended for the best performance and working IOMMU.
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+------------+
|
||||
| Type | Value |
|
||||
+=====================+============+
|
||||
|
@@ -15,7 +15,7 @@ Both "Trinity" and "Richland" desktop processing units are working,
|
||||
the CPU architecture in these CPUs/APUs is [Piledriver],
|
||||
and their GPU is [TeraScale 3] (VLIW4-based).
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| F2A85-M | |
|
||||
+------------------+--------------------------------------------------+
|
||||
@@ -35,7 +35,7 @@ and their GPU is [TeraScale 3] (VLIW4-based).
|
||||
+------------------+--------------------------------------------------+
|
||||
```
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| F2A85-M LE | |
|
||||
+------------------+--------------------------------------------------+
|
||||
@@ -55,7 +55,7 @@ and their GPU is [TeraScale 3] (VLIW4-based).
|
||||
+------------------+--------------------------------------------------+
|
||||
```
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| F2A85-M PRO | |
|
||||
+------------------+--------------------------------------------------+
|
||||
@@ -77,7 +77,7 @@ and their GPU is [TeraScale 3] (VLIW4-based).
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+------------+
|
||||
| Type | Value |
|
||||
+=====================+============+
|
||||
|
@@ -10,7 +10,7 @@ This page describes how to run coreboot on the ASUS P2B-LS mainboard.
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+---------------------------+
|
||||
| Type | Value |
|
||||
+=====================+===========================+
|
||||
@@ -90,7 +90,7 @@ for only CPU models that the board will actually be run with.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | Intel I440BX |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -4,7 +4,7 @@ This page describes how to run coreboot on the ASUS P3B-F mainboard.
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+---------------------------+
|
||||
| Type | Value |
|
||||
+=====================+===========================+
|
||||
@@ -88,7 +88,7 @@ for only CPU models that the board will actually be run with.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | Intel I440BX |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -32,7 +32,7 @@ This page describes how to run coreboot on the [ASUS P5Q] desktop board.
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+-------------------+----------------+
|
||||
| Type | Value |
|
||||
+===================+================+
|
||||
@@ -56,7 +56,7 @@ You can flash coreboot into your motherboard using [this guide].
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+---------------------------------------------------+
|
||||
| Northbridge | Intel P45 (called x4x in coreboot code) |
|
||||
+------------------+---------------------------------------------------+
|
||||
|
@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8H77-V].
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+----------------+
|
||||
| Type | Value |
|
||||
+=====================+================+
|
||||
@@ -69,7 +69,7 @@ flash externally.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8H61-M LX].
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+------------+
|
||||
| Type | Value |
|
||||
+=====================+============+
|
||||
@@ -84,7 +84,7 @@ region is not readable even by the host.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8H61-M Pro].
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+------------+
|
||||
| Type | Value |
|
||||
+=====================+============+
|
||||
@@ -78,7 +78,7 @@ region is not readable even by the host.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8H77-V].
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+----------------+
|
||||
| Type | Value |
|
||||
+=====================+================+
|
||||
@@ -56,7 +56,7 @@ work. The flash chip is socketed, so it's easy to remove and reflash.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8Z77-M].
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+----------------+
|
||||
| Type | Value |
|
||||
+=====================+================+
|
||||
@@ -112,7 +112,7 @@ therefore they currently do nothing under coreboot.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8Z77-M PRO]
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+----------------+
|
||||
| Type | Value |
|
||||
+=====================+================+
|
||||
@@ -143,7 +143,7 @@ easy to remove and reflash.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8Z77-V].
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+----------------+
|
||||
| Type | Value |
|
||||
+=====================+================+
|
||||
@@ -86,7 +86,7 @@ See [Asus Wi-Fi Go! v1].
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -8,7 +8,7 @@ through a proprietary 16-1 pin connector.
|
||||
I managed to grope the most pinout of the proprietary connector.
|
||||
See [Mini PCIe pinout] for more info.
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------+----------+-----------+------------+----------+-----------+
|
||||
| WIFIGO Pin | Usage | mPCIe pin | WIFIGO Pin | Usage | mPCIe pin |
|
||||
+============+==========+===========+============+==========+===========+
|
||||
|
@@ -17,7 +17,7 @@
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+----------------+
|
||||
| Type | Value |
|
||||
+=====================+================+
|
||||
@@ -58,7 +58,7 @@
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------+----------------------------------------+
|
||||
| SoC | :doc:`../../soc/cavium/cn81xx/index` |
|
||||
+---------------+----------------------------------------+
|
||||
|
@@ -2,7 +2,7 @@
|
||||
|
||||
## Hardware
|
||||
### Technology
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------+
|
||||
| CPU | Intel i7-8550U |
|
||||
+------------------+--------------------------------+
|
||||
@@ -15,7 +15,7 @@
|
||||
```
|
||||
|
||||
### Flash chip
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+-----------------+
|
||||
| Type | Value |
|
||||
+=====================+=================+
|
||||
|
83
Documentation/mainboard/dell/e7240.md
Normal file
83
Documentation/mainboard/dell/e7240.md
Normal file
@@ -0,0 +1,83 @@
|
||||
# Dell Latitude E7240
|
||||
|
||||
This page is about the notebook [Dell Latitude E7240].
|
||||
|
||||
## Release status
|
||||
|
||||
Dell Latitude E7240 was released in 2013 and is now end of life.
|
||||
It can be bought from a secondhand market like Taobao or eBay.
|
||||
|
||||
## Required proprietary blobs
|
||||
|
||||
The following blobs are required to operate the hardware:
|
||||
1. mrc.bin
|
||||
2. Intel ME firmware
|
||||
|
||||
Memory reference code in mrc.bin is used to initialize the Haswell platform.
|
||||
You need this blob to build a working coreboot image. Please read
|
||||
[mrc.bin](../../northbridge/intel/haswell/mrc.bin) for instructions on
|
||||
retrieving and using it.
|
||||
|
||||
Intel ME firmware is in the flash chip. It is not needed when building coreboot.
|
||||
It can be extracted from the OEM firmware. You can also flash only the BIOS
|
||||
region to leave Intel ME firmware untouched.
|
||||
|
||||
## Programming
|
||||
|
||||
The laptop can be flashed internally under OEM firmware using [dell-flash-unlock].
|
||||
|
||||
To flash with an external programmer, you need to remove the battery and the base cover.
|
||||
|
||||

|
||||
|
||||
For more details have a look at the general [flashing tutorial].
|
||||
|
||||
It is also possible to flash internally under coreboot.
|
||||
|
||||
## Debugging
|
||||
|
||||
The board can be debugged with EHCI debug. The EHCI debug port is next to the miniDP port.
|
||||
|
||||
There's a serial port on dock, but it's not yet supported in coreboot.
|
||||
|
||||
Schematic of this laptop can be found online. The board name is Compal LA-9431P.
|
||||
|
||||
## Test status
|
||||
|
||||
### Not working
|
||||
|
||||
- EC ACPI
|
||||
- SD/MMC card reader (kernel reports "Timeout waiting for hardware cmd interrupt.")
|
||||
- No internal display before booting to OS when connected with a dock
|
||||
|
||||
### Working
|
||||
|
||||
- Integrated graphics init with libgfxinit
|
||||
- mSATA
|
||||
- WLAN
|
||||
- USB
|
||||
- Keyboard
|
||||
- Touchpad and the buttons on it
|
||||
- Dock: all USB ports, DisplayPort, eSATA
|
||||
- Internal flashing
|
||||
|
||||
|
||||
## Technology
|
||||
|
||||
```{eval-rst}
|
||||
+------------------+-----------------------------+
|
||||
| CPU | Intel Haswell-ULT |
|
||||
+------------------+-----------------------------+
|
||||
| PCH | Intel Lynx Point Low Power |
|
||||
+------------------+-----------------------------+
|
||||
| EC | SMSC MEC5075 |
|
||||
+------------------+-----------------------------+
|
||||
| Super I/O | SMSC ECE5048 |
|
||||
+------------------+-----------------------------+
|
||||
| Coprocessor | Intel Management Engine |
|
||||
+------------------+-----------------------------+
|
||||
```
|
||||
|
||||
[Dell Latitude E7240]: https://www.dell.com/support/home/en-us/product-support/product/latitude-e7240-ultrabook/docs
|
||||
[dell-flash-unlock]: https://github.com/nic3-14159/dell-flash-unlock
|
||||
[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
|
BIN
Documentation/mainboard/dell/e7240.webp
Normal file
BIN
Documentation/mainboard/dell/e7240.webp
Normal file
Binary file not shown.
After Width: | Height: | Size: 97 KiB |
@@ -6,7 +6,7 @@ This page describes how to run coreboot on Dell OptiPlex 9010 SFF.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------+---------------------------------------------------------------+
|
||||
| CPU | Intel Core 2nd Gen (Sandybridge) or 3rd Gen (Ivybridge) |
|
||||
+------------+---------------------------------------------------------------+
|
||||
@@ -28,7 +28,7 @@ More specifications on [Dell OptiPlex 9010 specifications].
|
||||
|
||||
## Required proprietary blobs
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+---------------------------------+---------------------+
|
||||
| Binary file | Apply | Required / Optional |
|
||||
+==================+=================================+=====================+
|
||||
@@ -50,7 +50,7 @@ signature `SMSCUBIM`. The easiest way to do this is to use [UEFITool] and
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+--------------------------+
|
||||
| Type | Value |
|
||||
+=====================+==========================+
|
||||
|
@@ -3,6 +3,9 @@
|
||||
## Building coreboot and running it in QEMU
|
||||
|
||||
- Configure coreboot and run `make` as usual
|
||||
- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to
|
||||
convert coreboot to an ELF that QEMU can load
|
||||
- Run `qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf`
|
||||
|
||||
Run QEMU
|
||||
```
|
||||
qemu-system-riscv64 -M virt -m 1G -nographic -bios build/coreboot.rom \
|
||||
-drive if=pflash,file=./build/coreboot.rom,format=raw
|
||||
```
|
||||
|
42
Documentation/mainboard/emulation/qemu-sbsa.md
Normal file
42
Documentation/mainboard/emulation/qemu-sbsa.md
Normal file
@@ -0,0 +1,42 @@
|
||||
# QEMU SBSA emulator
|
||||
This page describes how to build and run ```coreboot``` for QEMU's sbsa-ref machine.
|
||||
The qemu-sbsa ```coreboot``` image acts as BL-3.3 for Arm Trusted Firmware (```TF-A```) and
|
||||
mainly takes care of setting up SMBIOS and ACPI tables, hence, in order to boot,
|
||||
you also need to supply a ```TF-A``` image.
|
||||
|
||||
## Building TF-A
|
||||
|
||||
You can build ```TF-A``` from source by fetching
|
||||
```
|
||||
https://github.com/ARM-software/arm-trusted-firmware
|
||||
```
|
||||
and building the qemu-sbsa platform
|
||||
```
|
||||
PLAT=qemu_sbsa
|
||||
```
|
||||
Upon entry, ```coreboot``` expects a FDT pointer in x0, so make sure to compile ```TF-A``` with
|
||||
```
|
||||
ARM_LINUX_KERNEL_AS_BL33=1
|
||||
```
|
||||
This will force ```TF-A``` to pass a pointer to the FDT in x0.
|
||||
|
||||
## Building coreboot
|
||||
|
||||
Simply select the qemu-sbsa board and, optionally, configure a payload. We recommend
|
||||
the ```leanefi``` payload. ```leanefi``` will setup a minimal set of UEFI services, just enough
|
||||
to boot into a linux kernel.
|
||||
|
||||
## Running coreboot in QEMU
|
||||
|
||||
Once you have obtained ```TF-A``` and ```coreboot``` images, launch qemu via
|
||||
|
||||
```bash
|
||||
qemu-system-aarch64 -nographic -m 1024 -M sbsa-ref -pflash <path/to/TFA.fd> \
|
||||
-pflash <path/to/coreboot.rom>
|
||||
```
|
||||
|
||||
## LBBR bootflow
|
||||
|
||||
arm and 9elements worked together in order to create a LBBR compliant bootflow
|
||||
consisting of ```TF-A```, ```coreboot```, ```leanefi``` and ```LinuxBoot```. A proof of concept
|
||||
can be found here https://gitlab.arm.com/systemready/firmware-build/linuxboot/lbbr-coreboot-poc
|
@@ -63,7 +63,7 @@ Specifically, it's a Winbond W25Q64FV (3.3V), whose datasheet can be found
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| SoC | Intel Atom Processor N3710 |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -14,7 +14,7 @@ Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/inde
|
||||
|
||||
FSP Information:
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+-----------------------------+-------------------+-------------------+
|
||||
| FSP Project Name | Directory | Specification |
|
||||
+-----------------------------+-------------------+-------------------+
|
||||
@@ -116,7 +116,7 @@ output.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| SoC | Intel Kaby Lake U |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -14,7 +14,7 @@ The default options for this board should result in a fully working image:
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+--------+
|
||||
| Type | Value |
|
||||
+=====================+========+
|
||||
@@ -56,7 +56,7 @@ To do this gently take the SPI flash out of its socket and flash with your progr
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+------------------+
|
||||
| Northbridge | Intel Pinevew |
|
||||
+------------------+------------------+
|
||||
|
@@ -6,7 +6,7 @@ This motherboard [also works with Libreboot](https://libreboot.org/docs/install/
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Type | Value |
|
||||
+==================+==================================================+
|
||||
@@ -30,7 +30,7 @@ This motherboard [also works with Libreboot](https://libreboot.org/docs/install/
|
||||
|
||||
## Preparation
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
For more datails how to get sources and build the toolchain, see :doc:`../../tutorial/part1`.
|
||||
```
|
||||
|
||||
@@ -140,7 +140,7 @@ Built gigabyte/ga-g41m-es2l (GA-G41M-ES2L)
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
In addition to the information here, please see the
|
||||
:doc:`../../tutorial/flashing_firmware/index`.
|
||||
```
|
||||
|
@@ -5,7 +5,7 @@ from [Gigabyte].
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+------------+
|
||||
| Type | Value |
|
||||
+=====================+============+
|
||||
@@ -59,7 +59,7 @@ However, this makes DualBIOS unable to recover from a bad flash for some reason.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -74,7 +74,7 @@ The EHCI debug port is the left USB3 port.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| CPU | Intel Sandy/Ivy Bridge (FCPGA988) |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -80,7 +80,7 @@ Schematic of this laptop can be found on [Lab One].
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| CPU | Intel Sandy/Ivy Bridge (FCPGA988) |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
80
Documentation/mainboard/hp/8560w.md
Normal file
80
Documentation/mainboard/hp/8560w.md
Normal file
@@ -0,0 +1,80 @@
|
||||
# HP EliteBook 8560w
|
||||
|
||||
This page describes how to run coreboot on the [HP EliteBook 8560w].
|
||||
|
||||
## Required proprietary blobs
|
||||
|
||||
- Intel Firmware Descriptor, ME and GbE firmware
|
||||
- EC: please read [HP Laptops with KBC1126 Embedded Controller](hp_kbc1126_laptops)
|
||||
|
||||
## Flashing instructions
|
||||
|
||||
When running vendor firmware, external flashing is needed.
|
||||
|
||||
HP EliteBook 8560w has an 8MiB SOIC-8 flash chip on the bottom of the
|
||||
mainboard. You just need to remove the service cover, and use an SOIC-8
|
||||
clip to read and flash the chip.
|
||||
|
||||

|
||||
|
||||
```{eval-rst}
|
||||
+---------------------+------------+
|
||||
| Type | Value |
|
||||
+=====================+============+
|
||||
| Socketed flash | no |
|
||||
+---------------------+------------+
|
||||
| Model | MX25L6406E |
|
||||
+---------------------+------------+
|
||||
| Size | 8 MiB |
|
||||
+---------------------+------------+
|
||||
| Package | SOIC-8 |
|
||||
+---------------------+------------+
|
||||
| Write protection | no |
|
||||
+---------------------+------------+
|
||||
| Dual BIOS feature | no |
|
||||
+---------------------+------------+
|
||||
| In circuit flashing | yes |
|
||||
+---------------------+------------+
|
||||
| Internal flashing | yes |
|
||||
+---------------------+------------+
|
||||
```
|
||||
|
||||
## Working
|
||||
|
||||
- i7-2720QM, 8G+8G
|
||||
- Arch Linux boot from SeaBIOS payload
|
||||
- EHCI debug: the port is beside the eSATA port
|
||||
- SATA
|
||||
- eSATA
|
||||
- USB2 and USB3
|
||||
- keyboard
|
||||
- Gigabit Ethernet
|
||||
- WLAN
|
||||
- WWAN
|
||||
- VGA and DisplayPort
|
||||
- audio
|
||||
- EC ACPI
|
||||
- Using `me_cleaner`
|
||||
- dock: PS/2 keyboard, USB, DisplayPort
|
||||
- TPM
|
||||
- S3 suspend/resume
|
||||
|
||||
## Technology
|
||||
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
|
||||
+------------------+--------------------------------------------------+
|
||||
| Southbridge | bd82x6x |
|
||||
+------------------+--------------------------------------------------+
|
||||
| CPU | model_206ax |
|
||||
+------------------+--------------------------------------------------+
|
||||
| Super I/O | SMSC LPC47n217 |
|
||||
+------------------+--------------------------------------------------+
|
||||
| EC | SMSC KBC1126 |
|
||||
+------------------+--------------------------------------------------+
|
||||
| Coprocessor | Intel Management Engine |
|
||||
+------------------+--------------------------------------------------+
|
||||
```
|
||||
|
||||
[HP EliteBook 8560w]: https://support.hp.com/us-en/product/hp-elitebook-8560w-mobile-workstation/5071171
|
BIN
Documentation/mainboard/hp/8560w_flash.webp
Normal file
BIN
Documentation/mainboard/hp/8560w_flash.webp
Normal file
Binary file not shown.
After Width: | Height: | Size: 50 KiB |
@@ -7,7 +7,7 @@ checkout the [code on gerrit] to build coreboot for the laptop.
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+------------+
|
||||
| Type | Value |
|
||||
+=====================+============+
|
||||
@@ -66,7 +66,7 @@ clip to read and flash the chip.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -13,7 +13,7 @@ The following things are still missing from this coreboot port:
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+-------------------------+
|
||||
| Type | Value |
|
||||
+=====================+=========================+
|
||||
@@ -128,7 +128,7 @@ as otherwise there's not enough space near the flash.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -5,7 +5,7 @@ from [HP].
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+-------------+
|
||||
| Type | Value |
|
||||
+=====================+=============+
|
||||
@@ -42,7 +42,7 @@ Wake on LAN is active works great.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -124,7 +124,7 @@ The board can be debugged with EHCI debug. The EHCI debug port is the USB port o
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+-----------------------------+
|
||||
| SoC | Intel Broadwell |
|
||||
+------------------+-----------------------------+
|
||||
|
@@ -138,7 +138,7 @@ The board can be debugged with EHCI debug. The EHCI debug port is the USB port o
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+-----------------------------+
|
||||
| CPU | Intel Haswell-ULT |
|
||||
+------------------+-----------------------------+
|
||||
|
103
Documentation/mainboard/hp/pro_3500_series.md
Normal file
103
Documentation/mainboard/hp/pro_3500_series.md
Normal file
@@ -0,0 +1,103 @@
|
||||
# HP Pro 3500 Series
|
||||
|
||||
This page describes how to run coreboot on the [Pro 3500 Series]
|
||||
desktop from [HP].
|
||||
|
||||
## State
|
||||
|
||||
All peripherals should work. Automatic fan control as well as S3 are
|
||||
working. The board was tested to boot Linux and Windows. EHCI debug
|
||||
is untested. When using MrChromebox edk2 with secure boot build in, the
|
||||
board will hang on each boot for about 20 seconds before continuing.
|
||||
With disabled ME, the SuperIO will not get CPU temperatures via PECI and
|
||||
therefore the automatic fan control will not increase the fan speed.
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```{eval-rst}
|
||||
+---------------------+-------------------------+
|
||||
| Type | Value |
|
||||
+=====================+=========================+
|
||||
| Socketed flash | No |
|
||||
+---------------------+-------------------------+
|
||||
| Model | W25Q64FVSIG |
|
||||
+---------------------+-------------------------+
|
||||
| Size | 8 MiB |
|
||||
+---------------------+-------------------------+
|
||||
| In circuit flashing | Yes |
|
||||
+---------------------+-------------------------+
|
||||
| Package | SOIC-8 |
|
||||
+---------------------+-------------------------+
|
||||
| Write protection | See below |
|
||||
+---------------------+-------------------------+
|
||||
| Dual BIOS feature | No |
|
||||
+---------------------+-------------------------+
|
||||
| Internal flashing | Yes |
|
||||
+---------------------+-------------------------+
|
||||
```
|
||||
|
||||
### Flash layout
|
||||
The original layout of the flash should look like this:
|
||||
```
|
||||
00000000:00000fff fd
|
||||
00400000:007fffff bios
|
||||
00001000:003fffff me
|
||||
00fff000:00000fff gbe
|
||||
00fff000:00000fff pd
|
||||
```
|
||||
|
||||
### Internal programming
|
||||
|
||||
The SPI flash can be accessed using [flashrom] (although it reports as
|
||||
"N25Q064..3E", it works fine).
|
||||
|
||||
With a missing FDO jumper, `fd` region is read-only, `bios` region is
|
||||
read-write and `me` region is locked. Vendor firmware will additionally
|
||||
protect the flash chip. After shorting the FDO jumper (E2) full
|
||||
read-write access is granted.
|
||||
|
||||
Do **NOT shutdown** the operating system **after flashing** coreboot
|
||||
from the vendor firmware! This will brick your device because the bios
|
||||
region will be modified on shutdown. Cut the AC power or do a restart
|
||||
from the OS.
|
||||
|
||||
**Position of FDO jumper (E2) close to the F_USB3**
|
||||
![][pro_3500_jumper]
|
||||
|
||||
[pro_3500_jumper]: pro_3500_series_jumper.avif
|
||||
|
||||
### External programming
|
||||
|
||||
External programming with an SPI adapter and [flashrom] does work, but
|
||||
it powers the whole southbridge complex. The average current will be
|
||||
400mA but spikes may be higher. Connect the power to the flash or the
|
||||
programming header next to the flash otherwise programming is unstable.
|
||||
The supply needs to quickly reach 3V3 or else the chip is also unstable
|
||||
until cleanly power cycled.
|
||||
|
||||
**Position of SOIC-8 flash and pin-header near ATX power connector**
|
||||
![][pro_3500_flash]
|
||||
|
||||
[pro_3500_flash]: pro_3500_series_flash.avif
|
||||
|
||||
## Technology
|
||||
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
|
||||
+------------------+--------------------------------------------------+
|
||||
| Southbridge | bd82x6x (bd82h61) |
|
||||
+------------------+--------------------------------------------------+
|
||||
| CPU | model_206ax |
|
||||
+------------------+--------------------------------------------------+
|
||||
| SuperIO | IT8779E (identifies as IT8772F via register) |
|
||||
+------------------+--------------------------------------------------+
|
||||
| EC | Fixed function as part of SuperIO |
|
||||
+------------------+--------------------------------------------------+
|
||||
| Coprocessor | Intel ME |
|
||||
+------------------+--------------------------------------------------+
|
||||
```
|
||||
|
||||
[Pro 3500 Series]: https://support.hp.com/us-en/document/c03364089
|
||||
[HP]: https://www.hp.com/
|
||||
[flashrom]: https://flashrom.org/Flashrom
|
BIN
Documentation/mainboard/hp/pro_3500_series_flash.avif
Normal file
BIN
Documentation/mainboard/hp/pro_3500_series_flash.avif
Normal file
Binary file not shown.
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BIN
Documentation/mainboard/hp/pro_3500_series_jumper.avif
Normal file
BIN
Documentation/mainboard/hp/pro_3500_series_jumper.avif
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Binary file not shown.
After Width: | Height: | Size: 35 KiB |
@@ -13,7 +13,7 @@ The following things are still missing from this coreboot port:
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+-------------+
|
||||
| Type | Value |
|
||||
+=====================+=============+
|
||||
@@ -58,7 +58,7 @@ even interchangeable, so should do coreboot images built for them.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
@@ -4,240 +4,397 @@ This section contains documentation about coreboot on specific mainboards.
|
||||
|
||||
## 51NB
|
||||
|
||||
- [X210](51nb/x210.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
X210 <51nb/x210.md>
|
||||
```
|
||||
|
||||
## Acer
|
||||
|
||||
- [G43T-AM3](acer/g43t-am3.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
G43T-AM3 <acer/g43t-am3.md>
|
||||
```
|
||||
|
||||
## AMD
|
||||
- [pademelon](amd/pademelon/pademelon.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
pademelon <amd/pademelon/pademelon.md>
|
||||
```
|
||||
|
||||
## ASRock
|
||||
|
||||
- [H77 Pro4-M](asrock/h77pro4-m.md)
|
||||
- [H81M-HDS](asrock/h81m-hds.md)
|
||||
- [H110M-DVS](asrock/h110m-dvs.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
H77 Pro4-M <asrock/h77pro4-m.md>
|
||||
H81M-HDS <asrock/h81m-hds.md>
|
||||
H110M-DVS <asrock/h110m-dvs.md>
|
||||
```
|
||||
|
||||
## ASUS
|
||||
|
||||
- [A88XM-E](asus/a88xm-e.md)
|
||||
- [F2A85-M](asus/f2a85-m.md)
|
||||
- [P2B-LS](asus/p2b-ls.md)
|
||||
- [P3B-F](asus/p3b-f.md)
|
||||
- [P5Q](asus/p5q.md)
|
||||
- [P8C WS](asus/p8c_ws.md)
|
||||
- [P8H61-M LX](asus/p8h61-m_lx.md)
|
||||
- [P8H61-M Pro](asus/p8h61-m_pro.md)
|
||||
- [P8H77-V](asus/p8h77-v.md)
|
||||
- [P8Z77-M](asus/p8z77-m.md)
|
||||
- [P8Z77-M Pro](asus/p8z77-m_pro.md)
|
||||
- [P8Z77-V](asus/p8z77-v.md)
|
||||
- [wifigo_v1](asus/wifigo_v1.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
A88XM-E <asus/a88xm-e.md>
|
||||
F2A85-M <asus/f2a85-m.md>
|
||||
P2B-LS <asus/p2b-ls.md>
|
||||
P3B-F <asus/p3b-f.md>
|
||||
P5Q <asus/p5q.md>
|
||||
P8C WS <asus/p8c_ws.md>
|
||||
P8H61-M LX <asus/p8h61-m_lx.md>
|
||||
P8H61-M Pro <asus/p8h61-m_pro.md>
|
||||
P8H77-V <asus/p8h77-v.md>
|
||||
P8Z77-M <asus/p8z77-m.md>
|
||||
P8Z77-M Pro <asus/p8z77-m_pro.md>
|
||||
P8Z77-V <asus/p8z77-v.md>
|
||||
wifigo_v1 <asus/wifigo_v1.md>
|
||||
```
|
||||
|
||||
## Cavium
|
||||
|
||||
- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
CN81XX EVB SFF <cavium/cn8100_sff_evb.md>
|
||||
```
|
||||
|
||||
## Clevo
|
||||
|
||||
- [N130WU / N131WU](clevo/n130wu/index.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
N130WU / N131WU <clevo/n130wu/index.md>
|
||||
```
|
||||
|
||||
## Dell
|
||||
|
||||
- [OptiPlex 9010 SFF](dell/optiplex_9010.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Latitude E7240 <dell/e7240.md>
|
||||
OptiPlex 9010 SFF <dell/optiplex_9010.md>
|
||||
```
|
||||
|
||||
## Emulation
|
||||
|
||||
The boards in this section are not real mainboards, but emulators.
|
||||
|
||||
- [Spike RISC-V emulator](emulation/spike-riscv.md)
|
||||
- [QEMU RISC-V emulator](emulation/qemu-riscv.md)
|
||||
- [QEMU AArch64 emulator](emulation/qemu-aarch64.md)
|
||||
- [QEMU x86 Q35](emulation/qemu-q35.md)
|
||||
- [QEMU x86 PC](emulation/qemu-i440fx.md)
|
||||
- [QEMU POWER9](emulation/qemu-power9.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Spike RISC-V emulator <emulation/spike-riscv.md>
|
||||
QEMU RISC-V emulator <emulation/qemu-riscv.md>
|
||||
QEMU AArch64 emulator <emulation/qemu-aarch64.md>
|
||||
QEMU SBSA emulator <emulation/qemu-sbsa.md>
|
||||
QEMU x86 Q35 <emulation/qemu-q35.md>
|
||||
QEMU x86 PC <emulation/qemu-i440fx.md>
|
||||
QEMU POWER9 <emulation/qemu-power9.md>
|
||||
```
|
||||
|
||||
## Facebook
|
||||
|
||||
- [FBG-1701](facebook/fbg1701.md)
|
||||
- [Monolith](facebook/monolith.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
FBG-1701 <facebook/fbg1701.md>
|
||||
Monolith <facebook/monolith.md>
|
||||
```
|
||||
|
||||
## Foxconn
|
||||
|
||||
- [D41S](foxconn/d41s.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
D41S <foxconn/d41s.md>
|
||||
```
|
||||
|
||||
## Gigabyte
|
||||
|
||||
- [GA-G41M-ES2L](gigabyte/ga-g41m-es2l.md)
|
||||
- [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
GA-G41M-ES2L <gigabyte/ga-g41m-es2l.md>
|
||||
GA-H61M-S2PV <gigabyte/ga-h61m-s2pv.md>
|
||||
```
|
||||
|
||||
## HP
|
||||
|
||||
- [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
|
||||
- [Compaq Elite 8300 USDT](hp/compaq_8300_usdt.md)
|
||||
- [Z220 Workstation SFF](hp/z220_sff.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Compaq 8200 Elite SFF <hp/compaq_8200_sff.md>
|
||||
Compaq Elite 8300 USDT <hp/compaq_8300_usdt.md>
|
||||
Pro 3500 Series <hp/pro_3500_series.md>
|
||||
Z220 Workstation SFF <hp/z220_sff.md>
|
||||
```
|
||||
|
||||
### EliteBook series
|
||||
|
||||
- [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md)
|
||||
- [HP Sure Start](hp/hp_sure_start.md)
|
||||
- [EliteBook 2170p](hp/2170p.md)
|
||||
- [EliteBook 2560p](hp/2560p.md)
|
||||
- [EliteBook 8760w](hp/8760w.md)
|
||||
- [EliteBook Folio 9480m](hp/folio_9480m.md)
|
||||
- [EliteBook 820 G2](hp/elitebook_820_g2.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
HP Laptops with KBC1126 EC <hp/hp_kbc1126_laptops.md>
|
||||
HP Sure Start <hp/hp_sure_start.md>
|
||||
EliteBook 2170p <hp/2170p.md>
|
||||
EliteBook 2560p <hp/2560p.md>
|
||||
EliteBook 8560w <hp/8560w.md>
|
||||
EliteBook 8760w <hp/8760w.md>
|
||||
EliteBook Folio 9480m <hp/folio_9480m.md>
|
||||
EliteBook 820 G2 <hp/elitebook_820_g2.md>
|
||||
```
|
||||
|
||||
## Intel
|
||||
|
||||
- [DG43GT](intel/dg43gt.md)
|
||||
- [DQ67SW](intel/dq67sw.md)
|
||||
- [KBLRVP11](intel/kblrvp11.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
DG43GT <intel/dg43gt.md>
|
||||
DQ67SW <intel/dq67sw.md>
|
||||
KBLRVP11 <intel/kblrvp11.md>
|
||||
```
|
||||
|
||||
## Kontron
|
||||
|
||||
- [mAL-10](kontron/mal10.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
mAL-10 <kontron/mal10.md>
|
||||
```
|
||||
|
||||
## Lenovo
|
||||
|
||||
- [Mainboard codenames](lenovo/codenames.md)
|
||||
- [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md)
|
||||
- [R60](lenovo/r60.md)
|
||||
- [T4xx common](lenovo/t4xx_series.md)
|
||||
- [X2xx common](lenovo/x2xx_series.md)
|
||||
- [vboot](lenovo/vboot.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Mainboard codenames <lenovo/codenames.md>
|
||||
Hardware Maintenance Manual of ThinkPads <lenovo/thinkpad_hmm.md>
|
||||
R60 <lenovo/r60.md>
|
||||
T4xx common <lenovo/t4xx_series.md>
|
||||
X2xx common <lenovo/x2xx_series.md>
|
||||
vboot <lenovo/vboot.md>
|
||||
```
|
||||
|
||||
### GM45 series
|
||||
|
||||
- [X200 / T400 / T500 / X301 common](lenovo/montevina_series.md)
|
||||
- [X301](lenovo/x301.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
X200 / T400 / T500 / X301 common <lenovo/montevina_series.md>
|
||||
X301 <lenovo/x301.md>
|
||||
```
|
||||
|
||||
### Arrandale series
|
||||
|
||||
- [T410](lenovo/t410.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
T410 <lenovo/t410.md>
|
||||
```
|
||||
|
||||
### Sandy Bridge series
|
||||
|
||||
- [T420](lenovo/t420.md)
|
||||
- [T420 / T520 / X220 / T420s / W520 common](lenovo/Sandy_Bridge_series.md)
|
||||
- [X1](lenovo/x1.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
T420 <lenovo/t420.md>
|
||||
T420 / T520 / X220 / T420s / W520 common <lenovo/Sandy_Bridge_series.md>
|
||||
X1 <lenovo/x1.md>
|
||||
```
|
||||
|
||||
### Ivy Bridge series
|
||||
|
||||
- [T430](lenovo/t430.md)
|
||||
- [T530 / W530](lenovo/w530.md)
|
||||
- [T430 / T530 / X230 / W530 common](lenovo/Ivy_Bridge_series.md)
|
||||
- [T431s](lenovo/t431s.md)
|
||||
- [X230s](lenovo/x230s.md)
|
||||
- [Internal flashing](lenovo/ivb_internal_flashing.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
T430 <lenovo/t430.md>
|
||||
T530 / W530 <lenovo/w530.md>
|
||||
T430 / T530 / X230 / W530 common <lenovo/Ivy_Bridge_series.md>
|
||||
T431s <lenovo/t431s.md>
|
||||
X230s <lenovo/x230s.md>
|
||||
Internal flashing <lenovo/ivb_internal_flashing.md>
|
||||
```
|
||||
|
||||
### Haswell series
|
||||
|
||||
- [T440p](lenovo/t440p.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
T440p <lenovo/t440p.md>
|
||||
```
|
||||
|
||||
## Libretrend
|
||||
|
||||
- [LT1000](libretrend/lt1000.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
LT1000 <libretrend/lt1000.md>
|
||||
```
|
||||
|
||||
## MSI
|
||||
|
||||
- [MS-7707](msi/ms7707/ms7707.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
MS-7707 <msi/ms7707/ms7707.md>
|
||||
```
|
||||
|
||||
## OCP
|
||||
|
||||
- [Delta Lake](ocp/deltalake.md)
|
||||
- [Tioga Pass](ocp/tiogapass.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Delta Lake <ocp/deltalake.md>
|
||||
Tioga Pass <ocp/tiogapass.md>
|
||||
```
|
||||
|
||||
## Open Cellular
|
||||
|
||||
- [Elgon](opencellular/elgon.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Elgon <opencellular/elgon.md>
|
||||
```
|
||||
|
||||
## PC Engines
|
||||
|
||||
- [APU1](pcengines/apu1.md)
|
||||
- [APU2](pcengines/apu2.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
APU1 <pcengines/apu1.md>
|
||||
APU2 <pcengines/apu2.md>
|
||||
```
|
||||
|
||||
## Portwell
|
||||
|
||||
- [PQ7-M107](portwell/pq7-m107.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
PQ7-M107 <portwell/pq7-m107.md>
|
||||
```
|
||||
|
||||
## Prodrive
|
||||
|
||||
- [Hermes](prodrive/hermes.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Hermes <prodrive/hermes.md>
|
||||
```
|
||||
|
||||
## Purism
|
||||
|
||||
- [Librem 14](purism/librem_14.md)
|
||||
- [Librem Mini](purism/librem_mini.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Librem 14 <purism/librem_14.md>
|
||||
Librem Mini <purism/librem_mini.md>
|
||||
```
|
||||
|
||||
## Protectli
|
||||
|
||||
- [FW2B / FW4B](protectli/fw2b_fw4b.md)
|
||||
- [FW6A / FW6B / FW6C](protectli/fw6.md)
|
||||
- [VP2420](protectli/vp2420.md)
|
||||
- [VP4630 / VP4650 / VP4670](protectli/vp46xx.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
FW2B / FW4B <protectli/fw2b_fw4b.md>
|
||||
FW6A / FW6B / FW6C <protectli/fw6.md>
|
||||
VP2420 <protectli/vp2420.md>
|
||||
VP4630 / VP4650 / VP4670 <protectli/vp46xx.md>
|
||||
```
|
||||
|
||||
## Roda
|
||||
|
||||
- [RK9 Flash Header](roda/rk9/flash_header.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
RK9 Flash Header <roda/rk9/flash_header.md>
|
||||
```
|
||||
|
||||
## SiFive
|
||||
|
||||
- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
SiFive HiFive Unleashed <sifive/hifive-unleashed.md>
|
||||
```
|
||||
|
||||
## Star Labs Systems
|
||||
|
||||
- [LabTop Mk III](starlabs/labtop_kbl.md)
|
||||
- [LabTop Mk IV](starlabs/labtop_cml.md)
|
||||
- [StarLite Mk III](starlabs/lite_glk.md)
|
||||
- [StarLite Mk IV](starlabs/lite_glkr.md)
|
||||
- [StarBook Mk V](starlabs/starbook_tgl.md)
|
||||
- [StarBook Mk VI](starlabs/starbook_adl.md)
|
||||
- [Flashing devices](starlabs/common/flashing.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
LabTop Mk III <starlabs/labtop_kbl.md>
|
||||
LabTop Mk IV <starlabs/labtop_cml.md>
|
||||
StarLite Mk III <starlabs/lite_glk.md>
|
||||
StarLite Mk IV <starlabs/lite_glkr.md>
|
||||
StarLite Mk V <starlabs/lite_adl.md>
|
||||
StarBook Mk V <starlabs/starbook_tgl.md>
|
||||
StarBook Mk VI <starlabs/starbook_adl.md>
|
||||
Flashing devices <starlabs/common/flashing.md>
|
||||
```
|
||||
|
||||
## Supermicro
|
||||
|
||||
- [X9SAE](supermicro/x9sae.md)
|
||||
- [X10SLM+-F](supermicro/x10slm-f.md)
|
||||
- [X11 LGA1151 series](supermicro/x11-lga1151-series/x11-lga1151-series.md)
|
||||
- [Flashing using the BMC](supermicro/flashing_on_vendorbmc.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
X9SAE <supermicro/x9sae.md>
|
||||
X10SLM+-F <supermicro/x10slm-f.md>
|
||||
X11 LGA1151 series <supermicro/x11-lga1151-series/x11-lga1151-series.md>
|
||||
Flashing using the BMC <supermicro/flashing_on_vendorbmc.md>
|
||||
```
|
||||
|
||||
## System76
|
||||
|
||||
- [Adder Workstation 1](system76/addw1.md)
|
||||
- [Adder Workstation 2](system76/addw2.md)
|
||||
- [Adder Workstation 3](system76/addw3.md)
|
||||
- [Bonobo Workstation 14](system76/bonw14.md)
|
||||
- [Bonobo Workstation 15](system76/bonw15.md)
|
||||
- [Darter Pro 6](system76/darp6.md)
|
||||
- [Darter Pro 7](system76/darp7.md)
|
||||
- [Darter Pro 8](system76/darp8.md)
|
||||
- [Darter Pro 9](system76/darp9.md)
|
||||
- [Galago Pro 4](system76/galp4.md)
|
||||
- [Galago Pro 5](system76/galp5.md)
|
||||
- [Galago Pro 6](system76/galp6.md)
|
||||
- [Galago Pro 7](system76/galp7.md)
|
||||
- [Gazelle 15](system76/gaze15.md)
|
||||
- [Gazelle 16](system76/gaze16.md)
|
||||
- [Gazelle 17](system76/gaze17.md)
|
||||
- [Gazelle 18](system76/gaze18.md)
|
||||
- [Lemur Pro 9](system76/lemp9.md)
|
||||
- [Lemur Pro 10](system76/lemp10.md)
|
||||
- [Lemur Pro 11](system76/lemp11.md)
|
||||
- [Lemur Pro 12](system76/lemp12.md)
|
||||
- [Oryx Pro 5](system76/oryp5.md)
|
||||
- [Oryx Pro 6](system76/oryp6.md)
|
||||
- [Oryx Pro 7](system76/oryp7.md)
|
||||
- [Oryx Pro 8](system76/oryp8.md)
|
||||
- [Oryx Pro 9](system76/oryp9.md)
|
||||
- [Oryx Pro 10](system76/oryp10.md)
|
||||
- [Oryx Pro 11](system76/oryp11.md)
|
||||
- [Serval Workstation 13](system76/serw13.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Adder Workstation 1 <system76/addw1.md>
|
||||
Adder Workstation 2 <system76/addw2.md>
|
||||
Adder Workstation 3 <system76/addw3.md>
|
||||
Bonobo Workstation 14 <system76/bonw14.md>
|
||||
Bonobo Workstation 15 <system76/bonw15.md>
|
||||
Darter Pro 6 <system76/darp6.md>
|
||||
Darter Pro 7 <system76/darp7.md>
|
||||
Darter Pro 8 <system76/darp8.md>
|
||||
Darter Pro 9 <system76/darp9.md>
|
||||
Galago Pro 4 <system76/galp4.md>
|
||||
Galago Pro 5 <system76/galp5.md>
|
||||
Galago Pro 6 <system76/galp6.md>
|
||||
Galago Pro 7 <system76/galp7.md>
|
||||
Gazelle 15 <system76/gaze15.md>
|
||||
Gazelle 16 <system76/gaze16.md>
|
||||
Gazelle 17 <system76/gaze17.md>
|
||||
Gazelle 18 <system76/gaze18.md>
|
||||
Lemur Pro 9 <system76/lemp9.md>
|
||||
Lemur Pro 10 <system76/lemp10.md>
|
||||
Lemur Pro 11 <system76/lemp11.md>
|
||||
Lemur Pro 12 <system76/lemp12.md>
|
||||
Oryx Pro 5 <system76/oryp5.md>
|
||||
Oryx Pro 6 <system76/oryp6.md>
|
||||
Oryx Pro 7 <system76/oryp7.md>
|
||||
Oryx Pro 8 <system76/oryp8.md>
|
||||
Oryx Pro 9 <system76/oryp9.md>
|
||||
Oryx Pro 10 <system76/oryp10.md>
|
||||
Oryx Pro 11 <system76/oryp11.md>
|
||||
Serval Workstation 13 <system76/serw13.md>
|
||||
```
|
||||
|
||||
## Texas Instruments
|
||||
|
||||
- [Beaglebone Black](ti/beaglebone-black.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Beaglebone Black <ti/beaglebone-black.md>
|
||||
```
|
||||
|
||||
## UP
|
||||
|
||||
- [Squared](up/squared/index.md)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
Squared <up/squared/index.md>
|
||||
```
|
||||
|
@@ -4,7 +4,7 @@ This page describes how to run coreboot on the [Intel DG43GT] desktop.
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+------------+
|
||||
| Type | Value |
|
||||
+=====================+============+
|
||||
@@ -79,7 +79,7 @@ The layout of the header is:
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+---------------------------------------------------+
|
||||
| Northbridge | Intel G43 (called x4x in coreboot code) |
|
||||
+------------------+---------------------------------------------------+
|
||||
|
@@ -4,7 +4,7 @@ The Intel DQ67SW is a microATX-sized desktop board for Intel Sandy Bridge CPUs.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
|
||||
+------------------+--------------------------------------------------+
|
||||
@@ -67,7 +67,7 @@ The Intel DQ67SW is a microATX-sized desktop board for Intel Sandy Bridge CPUs.
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+------------+
|
||||
| Type | Value |
|
||||
+=====================+============+
|
||||
@@ -104,7 +104,7 @@ the PCI configuration space of the LPC Interface Bridge, is set.
|
||||
It is possible to program the chip is to attach an external programmer
|
||||
with an SOIC-8 clip.
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
Another way is to boot the vendor firmware in UEFI mode and exploit the
|
||||
unpatched S3 Boot Script vulnerability. See this page for a similar procedure:
|
||||
:doc:`../lenovo/ivb_internal_flashing`.
|
||||
@@ -126,7 +126,7 @@ The boot script contains an entry that writes 0x02 to memory at address
|
||||
Interface Bridge [0][1]. The value 0x02 sets the BLE bit, and the modification
|
||||
prevents this by making it write a 0 instead.
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
After suspending and resuming the board, the BIOS region can be flashed with
|
||||
a coreboot image, e.g. using flashrom. Note that the ME region is not readable,
|
||||
so the `--noverify-all` flag is necessary. Please refer to the
|
||||
|
@@ -23,7 +23,7 @@
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+------------+
|
||||
| Type | Value |
|
||||
+=====================+============+
|
||||
@@ -65,7 +65,7 @@ $ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+---------------------------------------------------+
|
||||
| CPU | Kaby lake H (i7-7820EQ) |
|
||||
+------------------+---------------------------------------------------+
|
||||
|
@@ -6,7 +6,7 @@ processors.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+----------------------------------+
|
||||
| COMe Type | mini pin-out type 10 |
|
||||
+------------------+----------------------------------+
|
||||
|
@@ -3,7 +3,7 @@
|
||||
This information is valid for all supported models, except T430s, [T431s](t431s.md) and [X230s](x230s.md).
|
||||
|
||||
## Flashing coreboot
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+--------------------------------+
|
||||
| Type | Value |
|
||||
+=====================+================================+
|
||||
@@ -37,7 +37,7 @@ This information is valid for all supported models, except T430s, [T431s](t431s.
|
||||
exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB.
|
||||
* ROM chip size should be set to 12MiB.
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
Please also have a look at :doc:`../../tutorial/flashing_firmware/index`.
|
||||
```
|
||||
|
||||
@@ -82,7 +82,7 @@ It is possible to reduce the Intel ME firmware size to free additional
|
||||
space for the `bios` region. This is usually referred to as *cleaning the ME* or
|
||||
*stripping the ME*.
|
||||
After reducing the Intel ME firmware size you must modify the original IFD,
|
||||
[split the resulting coreboot ROM](#splitting-the-coreboot-rom) and then write
|
||||
[split the resulting coreboot ROM](#splitting-the-corebootrom) and then write
|
||||
each ROM using an [external programmer].
|
||||
Have a look at [me_cleaner] for more information.
|
||||
|
||||
|
@@ -1,7 +1,7 @@
|
||||
# Lenovo Sandy Bridge series
|
||||
|
||||
## Flashing coreboot
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+--------------------+
|
||||
| Type | Value |
|
||||
+=====================+====================+
|
||||
|
@@ -1,6 +1,6 @@
|
||||
# Lenovo mainboard codenames
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
.. csv-table::
|
||||
:header: "Marketing name", "Development codename"
|
||||
:file: codenames.csv
|
||||
|
@@ -19,7 +19,11 @@ that was discovered and fixed later.
|
||||
|
||||
- USB drive (in case you need to downgrade BIOS)
|
||||
- Linux install that (can be) loaded in UEFI mode
|
||||
- [CHIPSEC](https://github.com/chipsec/chipsec)
|
||||
```{toctree}
|
||||
:maxdepth: 1
|
||||
|
||||
CHIPSEC <https://github.com/chipsec/chipsec>
|
||||
```
|
||||
|
||||
## BIOS versions
|
||||
|
||||
@@ -27,7 +31,7 @@ Below is a table of BIOS versions that are vulnerable enough for our
|
||||
goals, per model. The version number means that you need to downgrade to
|
||||
that or earlier version.
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------+--------------+
|
||||
| Model | BIOS version |
|
||||
+============+==============+
|
||||
|
@@ -20,7 +20,7 @@ touch any other regions:
|
||||
|
||||
## Installing without ME firmware
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
.. Note::
|
||||
**ThinkPad R500** has slightly different flash layout (it doesn't have
|
||||
``gbe`` region), so the process would be a little different for that model.
|
||||
@@ -46,12 +46,12 @@ Now you need to patch the flash descriptor. You can either [modify the one from
|
||||
your backup with **ifdtool**](#modifying-flash-descriptor-using-ifdtool), or
|
||||
[use one from the coreboot repository](#using-checked-in-flash-descriptor-via-bincfg).
|
||||
|
||||
#### Modifying flash descriptor using ifdtool
|
||||
### Modifying flash descriptor using ifdtool
|
||||
|
||||
Pick the layout according to your chip size from the table below and save it to
|
||||
the `new_layout.txt` file:
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------------+---------------------------+---------------------------+
|
||||
| 4 MiB chip | 8 MiB chip | 16 MiB chip |
|
||||
+===========================+===========================+===========================+
|
||||
@@ -88,7 +88,7 @@ $ mv flashregion_0_flashdescriptor.bin.new.new flashregion_0_flashdescriptor.bin
|
||||
|
||||
Continue to the [Configuring coreboot](#configuring-coreboot) section.
|
||||
|
||||
#### Using checked-in flash descriptor via bincfg
|
||||
### Using checked-in flash descriptor via bincfg
|
||||
|
||||
There is a copy of an X200's flash descriptor checked into the coreboot
|
||||
repository. It is supposed to work for the T400/T500 as well. The descriptor
|
||||
@@ -102,7 +102,7 @@ $ make
|
||||
If your flash is not 8 MiB, you need to change values of `flcomp_density1` and
|
||||
`flreg1_limit` in the `ifd-x200.set` file according to following table:
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+-----------------+-------+-------+--------+
|
||||
| | 4 MiB | 8 MiB | 16 MiB |
|
||||
+=================+=======+=======+========+
|
||||
@@ -119,7 +119,7 @@ $ make gen-ifd-x200
|
||||
|
||||
It will be saved to the `flashregion_0_fd.bin` file.
|
||||
|
||||
#### Configuring coreboot
|
||||
### Configuring coreboot
|
||||
|
||||
Now configure coreboot. You need to select correct chip size and specify paths
|
||||
to flash descriptor and gbe dump.
|
||||
@@ -144,7 +144,7 @@ Then build coreboot and flash whole `build/coreboot.rom` to the chip.
|
||||
|
||||
The flash layouts of the OEM firmware are as follows:
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------------------+---------------------------------+
|
||||
| 4 MiB chip | 8 MiB chip |
|
||||
+=================================+=================================+
|
||||
|
@@ -5,7 +5,7 @@
|
||||
* TPM not working with VBOOT and C_ENV bootblock (works without C_ENV BB)
|
||||
|
||||
## Flashing instructions
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+---------------------+--------------------------------+
|
||||
| Type | Value |
|
||||
+=====================+================================+
|
||||
|
@@ -9,7 +9,7 @@ updates using an A/B partitioning scheme once enabled.
|
||||
## Enabling vboot
|
||||
You can enable [vboot] in Kconfig's *Security* section. Besides a verified
|
||||
boot you can also enable a measured boot by setting
|
||||
`CONFIG_VBOOT_MEASURED_BOOT`. Both options need a working TPM, which is
|
||||
`CONFIG_TPM_MEASURED_BOOT`. Both options need a working TPM, which is
|
||||
present on all recent Lenovo devices.
|
||||
|
||||
## Updating and recovery
|
||||
|
@@ -10,7 +10,7 @@ Librebox).
|
||||
To build a minimal working coreboot image some blobs are required (assuming
|
||||
only the BIOS region is being modified).
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+-----------------+---------------------------------+---------------------+
|
||||
| Binary file | Apply | Required / Optional |
|
||||
+=================+=================================+=====================+
|
||||
@@ -98,7 +98,7 @@ The platform contains an LR-i7S65T1 baseboard (LR-i7S65T2 with two NICs not
|
||||
sold yet). More details on [baseboard site]. Unfortunately the board manual is
|
||||
not publicly available.
|
||||
|
||||
```eval_rst
|
||||
```{eval-rst}
|
||||
+------------------+--------------------------------------------------+
|
||||
| CPU | Intel Core i7-6500U |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user