35599f9a66
Recommonmark has been deprecated since 2021 [1] and the last release was
over 3 years ago [2]. As per their announcement, Markedly Structured
Text (MyST) Parser [3] is the recommended replacement.
For the most part, the existing documentation is compatible with MyST,
as both parsers are built around the CommonMark flavor of Markdown. The
main difference that affects coreboot is how the Sphinx toctree is
generated. Recommonmark has a feature called auto_toc_tree, which
converts single level lists of references into a toctree:
* [Part 1: Starting from scratch](part1.md)
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)
MyST Parser does not provide a replacement for this feature, meaning the
toctree must be defined manually. This is done using MyST's syntax for
Sphinx directives:
```{toctree}
:maxdepth: 1
Part 1: Starting from scratch <part1.md>
Part 2: Submitting a patch to coreboot.org <part2.md>
Part 3: Writing unit tests <part3.md>
Managing local additions <managing_local_additions.md>
Flashing firmware <flashing_firmware/index.md>
```
Internally, auto_toc_tree essentially converts lists of references into
the Sphinx toctree structure that the MyST syntax above more directly
represents.
The toctrees were converted to the MyST syntax using the following
command and Python script:
`find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py`
```
import re
import sys
in_list = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()
with open(sys.argv[1], "w") as f:
for line in lines:
match = re.match(r"^[-*+] \[(.*)\]\((.*)\)$", line)
if match is not None:
if not in_list:
in_list = True
f.write("```{toctree}\n")
f.write(":maxdepth: 1\n\n")
f.write(match.group(1) + " <" + match.group(2) + ">\n")
else:
if in_list:
f.write("```\n")
f.write(line)
in_list = False
if in_list:
f.write("```\n")
```
While this does add a little more work for creating the toctree, this
does give more control over exactly what goes into the toctree. For
instance, lists of links to external resources currently end up in the
toctree, but we may want to limit it to pages within coreboot.
This change does break rendering and navigation of the documentation in
applications that can render Markdown, such as Okular, Gitiles, or the
GitHub mirror. Assuming the docs are mainly intended to be viewed after
being rendered to doc.coreboot.org, this is probably not an issue in
practice.
Another difference is that MyST natively supports Markdown tables,
whereas with Recommonmark, tables had to be written in embedded rST [4].
However, MyST also supports embedded rST, so the existing tables can be
easily converted as the syntax is nearly identical.
These were converted using
`find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"`
Makefile.sphinx and conf.py were regenerated from scratch by running
`sphinx-quickstart` using the updated version of Sphinx, which removes a
lot of old commented out boilerplate. Any relevant changes coreboot had
made on top of the previous autogenerated versions of these files were
ported over to the newly generated file.
From some initial testing the generated webpages appear and function
identically to the existing documentation built with Recommonmark.
TEST: `make -C util/docker docker-build-docs` builds the documentation
successfully and the generated output renders properly when viewed in
a web browser.
[1] https://github.com/readthedocs/recommonmark/issues/221
[2] https://pypi.org/project/recommonmark/
[3] https://myst-parser.readthedocs.io/en/latest/
[4] https://doc.coreboot.org/getting_started/writing_documentation.html
Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
3.7 KiB
ASUS P3B-F
This page describes how to run coreboot on the ASUS P3B-F mainboard.
Flashing coreboot
+---------------------+---------------------------+
| Type | Value |
+=====================+===========================+
| Model | SST 39SF020A (or similar) |
+---------------------+---------------------------+
| Protocol | Parallel |
+---------------------+---------------------------+
| Size | 256 KiB |
+---------------------+---------------------------+
| Package | DIP-32 |
+---------------------+---------------------------+
| Socketed | yes |
+---------------------+---------------------------+
| Write protection | See below |
+---------------------+---------------------------+
| Internal flashing | yes |
+---------------------+---------------------------+
flashrom supports this mainboard since commit c7e9a6e15153684672bbadd1fc6baed8247ba0f6. If you are using older versions of flashrom, below has to be done (with ACPI disabled!) before flashrom can detect the flash chip:
# rmmod w83781d
# modprobe i2c-dev
# i2cset 0 0x48 0x80 0x80
Upon power up, flash chip is inaccessible until flashrom has been run once. Since flashrom does not support reversing board enabling steps, once it detects the flash chip, there will be no write protection until the next power cycle.
CPU microcode considerations
By default, this board includes microcode updates for 5 families of Intel CPUs because of the wide variety of CPUs the board supports, directly or with an adapter. These take up a third of the total flash space leaving only 20kB free in the final cbfs image. It may be necessary to build a custom microcode update file by manually concatenating files in 3rdparty/intel-microcode/intel-ucode for only CPU models that the board will actually be run with.
Working
- Slot 1 and Socket 370 CPUs and their L1/L2 caches
- PS/2 keyboard with SeaBIOS (See [Known issues])
- IDE hard drives
- USB
- PCI add-on cards
- AGP graphics cards
- Serial ports 1 and 2
- Reboot
Known issues
-
PS/2 keyboard may not be usable until Linux has completely booted. With SeaBIOS as payload, setting keyboard initialization timeout to 2500ms may help.
-
The coreboot+SeaBIOS combination boots so quickly some IDE hard drives are not yet ready by the time SeaBIOS attempts to boot from them.
-
i440BX does not support 256Mbit RAM modules. If installed, coreboot will attempt to initialize them at half their capacity anyway whereas vendor firmware will not boot at all.
-
ECC memory can be used, but ECC support is still pending.
Untested
- Floppy
- Parallel port
- EDO memory
- ECC memory
- Infrared
- PC speaker
Not working
- ACPI (Support is currently under gerrit review)
Technology
+------------------+--------------------------------------------------+
| Northbridge | Intel I440BX |
+------------------+--------------------------------------------------+
| Southbridge | i82371eb |
+------------------+--------------------------------------------------+
| CPU | P6 family for Slot 1 and Socket 370 |
| | (all models from model_63x to model_6bx) |
+------------------+--------------------------------------------------+
| Super I/O | winbond/w83977tf |
+------------------+--------------------------------------------------+