soc/intel/xeon_sp/spr: Move XHCI code into southbridge folder

Move the XHCI code into soc/intel/xeon_sp/ebg where it belongs.

TEST=intel/archercity CRB

Change-Id: I2206ec5426a0f922cfce0e2d968e6806d349a6b2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This commit is contained in:
Patrick Rudolph
2024-03-21 08:05:03 +01:00
committed by Felix Held
parent 2b24fc7c56
commit cb92d28d7a
5 changed files with 6 additions and 6 deletions

View File

@@ -2,6 +2,6 @@
bootblock-y += soc_gpio.c soc_pch.c
romstage-y += soc_gpio.c soc_pmutil.c soc_pch.c
ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c
ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c soc_xhci.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/ebg/include

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@@ -2,10 +2,13 @@
#include <console/console.h>
#include <device/pci.h>
#include <soc/pci_devs.h>
#include <soc/pch_pci_devs.h>
#include <soc/xhci.h>
#include <types.h>
// XHCI register
#define SYS_BUS_CFG2 0x44
static uint8_t *get_xhci_bar(void)
{
const struct resource *res;

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@@ -12,7 +12,7 @@ romstage-y += romstage.c soc_util.c ddr.c
romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c xhci.c reset.c
ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c reset.c
ramstage-y += crashlog.c ioat.c
ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c

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@@ -122,9 +122,6 @@
#define IIO_DFX_TSWCTL0 0x30c
#define IIO_DFX_LCK_CTL 0x504
// XHCI register
#define SYS_BUS_CFG2 0x44
/* MSM registers */
#define MSM_BUS 0xF2
#define MSM_DEV 3