soc/intel/xeon_sp/spr: Move XHCI code into southbridge folder
Move the XHCI code into soc/intel/xeon_sp/ebg where it belongs. TEST=intel/archercity CRB Change-Id: I2206ec5426a0f922cfce0e2d968e6806d349a6b2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jincheng Li <jincheng.li@intel.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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committed by
Felix Held
parent
2b24fc7c56
commit
cb92d28d7a
@@ -2,6 +2,6 @@
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bootblock-y += soc_gpio.c soc_pch.c
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romstage-y += soc_gpio.c soc_pmutil.c soc_pch.c
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ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c
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ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c soc_xhci.c
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CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/ebg/include
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@@ -2,10 +2,13 @@
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#include <console/console.h>
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#include <device/pci.h>
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#include <soc/pci_devs.h>
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#include <soc/pch_pci_devs.h>
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#include <soc/xhci.h>
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#include <types.h>
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// XHCI register
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#define SYS_BUS_CFG2 0x44
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static uint8_t *get_xhci_bar(void)
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{
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const struct resource *res;
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@@ -12,7 +12,7 @@ romstage-y += romstage.c soc_util.c ddr.c
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romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
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romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
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ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c xhci.c reset.c
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ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c reset.c
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ramstage-y += crashlog.c ioat.c
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ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
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ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
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@@ -122,9 +122,6 @@
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#define IIO_DFX_TSWCTL0 0x30c
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#define IIO_DFX_LCK_CTL 0x504
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// XHCI register
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#define SYS_BUS_CFG2 0x44
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/* MSM registers */
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#define MSM_BUS 0xF2
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#define MSM_DEV 3
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