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soc/intel/xeon_sp: Remove PAM unlock operations

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unlock_pam_regions routes Programmable Attribute Map (PAM) access
to DRAM. In SPR, PAM routing to DRAM is covered by FSP. Move the
step to SoC specific codes.

TEST=intel/archercity CRB

Change-Id: I3fd1d806807449e6a4d9d4d2c8a47ce61ed53018
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This commit is contained in:
Shuo Liu
2024-03-21 00:43:10 +08:00
committed by Lean Sheng Tan
parent f4a12e1d39
commit 42fa6247f4
5 changed files with 51 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
src/soc/intel/xeon_sp/cpx/chip.c
View File

@@ -161,8 +161,32 @@ static void chip_final(void *data)
set_bios_init_completion();
}
/* Only call this code from socket0! */
static void unlock_pam_regions(void)
{
uint32_t pam0123_unlock_dram = 0x33333330;
uint32_t pam456_unlock_dram = 0x00333333;
/* Get UBOX(1) for socket0 */
uint32_t bus1 = socket0_get_ubox_busno(PCU_IIO_STACK);
/* Assume socket0 owns PCI segment 0 */
pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
SAD_ALL_PAM0123_CSR, pam0123_unlock_dram);
pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
SAD_ALL_PAM456_CSR, pam456_unlock_dram);
uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR);
uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
SAD_ALL_FUNC), SAD_ALL_PAM456_CSR);
printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n",
__FILE__, __func__, reg1, reg2);
}
static void chip_init(void *data)
{
unlock_pam_regions();
printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
fsp_silicon_init();

1
src/soc/intel/xeon_sp/include/soc/util.h
View File

@@ -9,7 +9,6 @@
#define MEM_ADDR_64MB_SHIFT_BITS 26
void lock_pam0123(void);
void unlock_pam_regions(void);
msr_t read_msr_ppin(void);
int get_platform_thread_count(void);

2
src/soc/intel/xeon_sp/romstage.c
View File

@@ -24,8 +24,6 @@ void mainboard_romstage_entry(void)
}
}
unlock_pam_regions();
save_dimm_info();
}

27
src/soc/intel/xeon_sp/skx/chip.c
View File

@@ -3,6 +3,9 @@
#include <cbfs.h>
#include <console/console.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <soc/pci_devs.h>
#include <gpio.h>
#include <intelblocks/acpi.h>
#include <soc/acpi.h>
@@ -35,8 +38,32 @@ static void soc_enable_dev(struct device *dev)
}
}
/* Only call this code from socket0! */
static void unlock_pam_regions(void)
{
uint32_t pam0123_unlock_dram = 0x33333330;
uint32_t pam456_unlock_dram = 0x00333333;
/* Get UBOX(1) for socket0 */
uint32_t bus1 = socket0_get_ubox_busno(PCU_IIO_STACK);
/* Assume socket0 owns PCI segment 0 */
pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
SAD_ALL_PAM0123_CSR, pam0123_unlock_dram);
pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
SAD_ALL_PAM456_CSR, pam456_unlock_dram);
uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR);
uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
SAD_ALL_FUNC), SAD_ALL_PAM456_CSR);
printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n",
__FILE__, __func__, reg1, reg2);
}
static void soc_init(void *data)
{
unlock_pam_regions();
printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
fsp_silicon_init();

22
src/soc/intel/xeon_sp/util.c
View File

@@ -17,28 +17,6 @@
#include <soc/util.h>
#include <timer.h>
/* Only call this code from socket0! */
void unlock_pam_regions(void)
{
uint32_t pam0123_unlock_dram = 0x33333330;
uint32_t pam456_unlock_dram = 0x00333333;
/* Get UBOX(1) for socket0 */
uint32_t bus1 = socket0_get_ubox_busno(PCU_IIO_STACK);
/* Assume socket0 owns PCI segment 0 */
pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
SAD_ALL_PAM0123_CSR, pam0123_unlock_dram);
pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
SAD_ALL_PAM456_CSR, pam456_unlock_dram);
uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR);
uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
SAD_ALL_FUNC), SAD_ALL_PAM456_CSR);
printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n",
__FILE__, __func__, reg1, reg2);
}
msr_t read_msr_ppin(void)
{
msr_t ppin = {0};