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skl mainboards/dt: Drop SataPortsEnable[x] setting if disabled

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The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.

Change-Id: Icdf58a85bbde0dcb4e555df68cd20eade241dde3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83176
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
This commit is contained in:
Felix Singer 2024-06-23 04:33:08 +02:00
parent d91e20f19b
commit 00e1376943
12 changed files with 0 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/mainboard/facebook/monolith/devicetree.cb
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@ -40,13 +40,6 @@ chip soc/intel/skylake
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{
[0] = 1,
[1] = 0,
[2] = 0,
[3] = 0,
[4] = 0,
[5] = 0,
[6] = 0,
[7] = 0,
}"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch

1
src/mainboard/google/eve/devicetree.cb
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@ -36,7 +36,6 @@ chip soc/intel/skylake
register "gen3_dec" = "0x00fc0901"
# FSP Configuration
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ScsEmmcHs400Enabled" = "1"

1
src/mainboard/google/glados/devicetree.cb
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@ -35,7 +35,6 @@ chip soc/intel/skylake
register "dptf_enable" = "1"
# FSP Configuration
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ScsEmmcHs400Enabled" = "1"

1
src/mainboard/google/poppy/variants/atlas/devicetree.cb
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@ -43,7 +43,6 @@ chip soc/intel/skylake
register "CmdTriStateDis" = "1"
# FSP Configuration
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ScsEmmcHs400Enabled" = "1"

1
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
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@ -31,7 +31,6 @@ chip soc/intel/skylake
register "s0ix_enable" = true
# FSP Configuration
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ScsEmmcHs400Enabled" = "1"

1
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
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@ -40,7 +40,6 @@ chip soc/intel/skylake
register "s0ix_enable" = true
# FSP Configuration
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ScsEmmcHs400Enabled" = "1"

1
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
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@ -36,7 +36,6 @@ chip soc/intel/skylake
register "CmdTriStateDis" = "1"
# FSP Configuration
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ScsEmmcHs400Enabled" = "1"

1
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View File

@ -43,7 +43,6 @@ chip soc/intel/skylake
register "CmdTriStateDis" = "1"
# FSP Configuration
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ScsEmmcHs400Enabled" = "1"

1
src/mainboard/google/poppy/variants/soraka/devicetree.cb
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@ -40,7 +40,6 @@ chip soc/intel/skylake
register "s0ix_enable" = true
# FSP Configuration
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ScsEmmcHs400Enabled" = "1"

1
src/mainboard/protectli/vault_kbl/devicetree.cb
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@ -109,7 +109,6 @@ chip soc/intel/skylake
# Enable SATA ports 1,2
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "SataPortsEnable[2]" = "0"
register "SataPortsDevSlp[0]" = "0"
register "SataPortsDevSlp[1]" = "0"

1
src/mainboard/purism/librem_skl/devicetree.cb
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@ -42,7 +42,6 @@ chip soc/intel/skylake
# FSP Configuration
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "0"
register "SataPortsEnable[2]" = "1"
register "SataPortsDevSlp[0]" = "0"
register "SataPortsDevSlp[2]" = "0"

5
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
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@ -22,11 +22,6 @@ chip soc/intel/skylake
register "dptf_enable" = "0"
# FSP Configuration
register "SataPortsEnable" = "{
[0] = 0,
[1] = 0,
[2] = 0,
}"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "SkipExtGfxScan" = "1"