35599f9a66
Recommonmark has been deprecated since 2021 [1] and the last release was
over 3 years ago [2]. As per their announcement, Markedly Structured
Text (MyST) Parser [3] is the recommended replacement.
For the most part, the existing documentation is compatible with MyST,
as both parsers are built around the CommonMark flavor of Markdown. The
main difference that affects coreboot is how the Sphinx toctree is
generated. Recommonmark has a feature called auto_toc_tree, which
converts single level lists of references into a toctree:
* [Part 1: Starting from scratch](part1.md)
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)
MyST Parser does not provide a replacement for this feature, meaning the
toctree must be defined manually. This is done using MyST's syntax for
Sphinx directives:
```{toctree}
:maxdepth: 1
Part 1: Starting from scratch <part1.md>
Part 2: Submitting a patch to coreboot.org <part2.md>
Part 3: Writing unit tests <part3.md>
Managing local additions <managing_local_additions.md>
Flashing firmware <flashing_firmware/index.md>
```
Internally, auto_toc_tree essentially converts lists of references into
the Sphinx toctree structure that the MyST syntax above more directly
represents.
The toctrees were converted to the MyST syntax using the following
command and Python script:
`find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py`
```
import re
import sys
in_list = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()
with open(sys.argv[1], "w") as f:
for line in lines:
match = re.match(r"^[-*+] \[(.*)\]\((.*)\)$", line)
if match is not None:
if not in_list:
in_list = True
f.write("```{toctree}\n")
f.write(":maxdepth: 1\n\n")
f.write(match.group(1) + " <" + match.group(2) + ">\n")
else:
if in_list:
f.write("```\n")
f.write(line)
in_list = False
if in_list:
f.write("```\n")
```
While this does add a little more work for creating the toctree, this
does give more control over exactly what goes into the toctree. For
instance, lists of links to external resources currently end up in the
toctree, but we may want to limit it to pages within coreboot.
This change does break rendering and navigation of the documentation in
applications that can render Markdown, such as Okular, Gitiles, or the
GitHub mirror. Assuming the docs are mainly intended to be viewed after
being rendered to doc.coreboot.org, this is probably not an issue in
practice.
Another difference is that MyST natively supports Markdown tables,
whereas with Recommonmark, tables had to be written in embedded rST [4].
However, MyST also supports embedded rST, so the existing tables can be
easily converted as the syntax is nearly identical.
These were converted using
`find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"`
Makefile.sphinx and conf.py were regenerated from scratch by running
`sphinx-quickstart` using the updated version of Sphinx, which removes a
lot of old commented out boilerplate. Any relevant changes coreboot had
made on top of the previous autogenerated versions of these files were
ported over to the newly generated file.
From some initial testing the generated webpages appear and function
identically to the existing documentation built with Recommonmark.
TEST: `make -C util/docker docker-build-docs` builds the documentation
successfully and the generated output renders properly when viewed in
a web browser.
[1] https://github.com/readthedocs/recommonmark/issues/221
[2] https://pypi.org/project/recommonmark/
[3] https://myst-parser.readthedocs.io/en/latest/
[4] https://doc.coreboot.org/getting_started/writing_documentation.html
Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
5.0 KiB
HP EliteBook Folio 9480m
This page is about the notebook HP EliteBook Folio 9480m.
Release status
HP EliteBook Folio 9480m was released in 2014 and is now end of life. It can be bought from a secondhand market like Taobao or eBay.
Required proprietary blobs
The following blobs are required to operate the hardware:
- EC firmware
- Intel ME firmware
- mrc.bin
HP EliteBook Folio 9480m uses SMSC MEC1322 as its embedded controller. The EC firmware is stored in the flash chip, but we don't need to touch it or use it in the coreboot build process.
Intel ME firmware is in the flash chip. It is not needed when building coreboot.
The Haswell memory reference code binary is needed when building coreboot. Please see mrc.bin.
Programming
Before flashing, remove the battery and the hard drive cover according to the Maintenance and Service Guide of this laptop.
HP EliteBook Folio 9480m has two flash chips, a 16MiB system flash, and a 2MiB private flash. To install coreboot, we need to program both flash chips. Read HP Sure Start for detailed information.
To access the system flash, we need to connect the AC adapter to the machine, then clip on the flash chip with an SOIC-8 clip. An STM32-based flash programmer made with an STM32 development board is tested to work.
To access the private flash chip, we can use a ch341a based flash programmer and flash the chip with the AC adapter disconnected.
Before flashing coreboot, we need to do the following:
- Erase the private flash to disable the IFD protection
- Modify the IFD to shrink the BIOS region, so that we'll not use or override the protected bootblock and PEI region, as well as the EC firmware
To erase the private flash chip, attach it with the flash programmer via the SOIC-8 clip, then run:
flashrom -p <programmer> --erase
To modify the IFD, we need a new flash layout. The flash layout of the OEM firmware is:
00000000:00000fff fd
00001000:00002fff gbe
00003000:005fffff me
00600000:00ffffff bios
The default coreboot configuration sets the flash chip size to 12MiB, so set the end of the BIOS region to 0xbfffff in the new layout. The modified IFD is as follows (Platform Data region pd is the region protected by HP Sure Start):
00000000:00000fff fd
00001000:00002fff gbe
00003000:005fffff me
00600000:00bfffff bios
00eb5000:00ffffff pd
Write the above layout in a file, and use ifdtool to modify the IFD of a flash image.
Suppose the above layout file is layout.txt and the origin content of the system flash
is in factory-sys.rom, run:
ifdtool -n layout.txt factory-sys.rom
Then a flash image with a new IFD will be in factory-sys.rom.new.
Flash the IFD of the system flash:
flashrom -p <programmer> --ifd -i fd -w factory-sys.rom.new
Then flash the coreboot image:
# first extend the 12M coreboot.rom to 16M
fallocate -l 16M build/coreboot.rom
flashrom -p <programmer> --ifd -i bios -w build/coreboot.rom
After coreboot is installed, the coreboot firmware can be updated with internal flashing:
flashrom -p internal --ifd -i bios --noverify-all -w build/coreboot.rom
Debugging
The board can be debugged with EHCI debug. The EHCI debug port is the USB port on the left.
Test status
Known issues
- GRUB payload freezes just like previous EliteBook laptops
- Sometimes the PCIe WLAN module can not be found in the OS after booting to the system
- Sometimes all the USB devices can not be found in the OS after S3 resume
Untested
- Fingerprint reader
- Smart Card reader
Working
- i5-4310U CPU with 4G+4G memory
- SATA and M.2 SATA disk
- Ethernet
- WLAN
- WWAN
- SD card reader
- USB
- Keyboard and touchpad
- DisplayPort
- VGA
- Dock
- Audio output from speaker and headphone jack
- Webcam
- TPM
- EC ACPI
- S3 resume
- Arch Linux with Linux 5.8.9
- Memory initialization with mrc.bin version 1.6.1 Build 2
- Graphics initialization with libgfxinit
- Payload: SeaBIOS, edk2
- EC firmware
- KBC Revision 92.15 from OEM firmware version 01.33
- KBC Revision 92.17 from OEM firmware version 01.50
- Internal flashing under coreboot
Technology
+------------------+-----------------------------+
| CPU | Intel Haswell-ULT |
+------------------+-----------------------------+
| PCH | Intel Lynx Point Low Power |
+------------------+-----------------------------+
| EC | SMSC MEC1322 |
+------------------+-----------------------------+
| Coprocessor | Intel Management Engine |
+------------------+-----------------------------+