soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSP

In a server platform many silicon specific register lock operations
are by default in FSP space. CHIPSET_LOCKDOWN_FSP provides an option
to make sure the codes could be used out-of-box to build products.

Change-Id: I8efcc1f27446be8e35f51e2568c4af6f8165486b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82081
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>

src/soc/intel/xeon_sp/lockdown.c

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <intelblocks/cfg.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelpch/lockdown.h>
 #include <soc/lockdown.h>
@@ -20,6 +21,9 @@ static void lpc_lockdown_config(void)
 
 void soc_lockdown_config(int chipset_lockdown)
 {
+	if (chipset_lockdown == CHIPSET_LOCKDOWN_FSP)
+		return;
+
 	lpc_lockdown_config();
 	pmc_lockdown_config();
 	sata_lockdown_config(chipset_lockdown);