78439118c8
In a server platform many silicon specific register lock operations are by default in FSP space. CHIPSET_LOCKDOWN_FSP provides an option to make sure the codes could be used out-of-box to build products. Change-Id: I8efcc1f27446be8e35f51e2568c4af6f8165486b Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82081 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
32 lines
676 B
C
32 lines
676 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <intelblocks/cfg.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelpch/lockdown.h>
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#include <soc/lockdown.h>
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#include <soc/pm.h>
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static void lpc_lockdown_config(void)
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{
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/* Set BIOS Interface Lock, BIOS Lock */
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lpc_set_bios_interface_lock_down();
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/* Only allow writes in SMM */
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if (CONFIG(BOOTMEDIA_SMM_BWP)) {
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lpc_set_eiss();
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lpc_enable_wp();
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}
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lpc_set_lock_enable();
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}
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void soc_lockdown_config(int chipset_lockdown)
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{
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if (chipset_lockdown == CHIPSET_LOCKDOWN_FSP)
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return;
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lpc_lockdown_config();
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pmc_lockdown_config();
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sata_lockdown_config(chipset_lockdown);
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spi_lockdown_config(chipset_lockdown);
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}
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