tree: Remove blank lines before '}' and after '{'
Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes Haouas
parent
1dc8f0272b
commit
31402178c5
@ -40,5 +40,4 @@ void buffer_to_fifo32_prefix(const void *buffer, u32 prefix, int prefsz, size_t
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val = 0;
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j = 0;
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}
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}
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@ -1491,7 +1491,6 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn,
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prev = &bus->children;
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for (dev = bus->children; dev; dev = dev->sibling) {
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/*
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* If static device is not PCI then enable it here and don't
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* treat it as a leftover device.
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@ -1851,7 +1850,6 @@ void pci_assign_irqs(struct device *dev, const unsigned char pIntAtoD[4])
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slot = dev->path.pci.devfn >> 3;
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for (; dev ; dev = dev->sibling) {
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if (dev->path.pci.devfn >> 3 != slot)
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break;
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@ -140,7 +140,6 @@ static void update_bridge_resource(const struct device *bridge, struct resource
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print_bridge_res(bridge, bridge_res, print_depth, "");
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while ((child = largest_resource(bus, &child_res, type_mask, type_match))) {
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/* Size 0 resources can be skipped. */
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if (!child_res->size)
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continue;
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@ -260,7 +259,6 @@ static void compute_domain_resources(const struct device *domain)
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return;
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for (child = domain->downstream->children; child; child = child->sibling) {
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/* Skip if this is not a bridge or has no children under it. */
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if (!dev_has_children(child))
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continue;
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@ -400,7 +398,6 @@ static void allocate_toplevel_resources(const struct device *const domain,
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setup_resource_ranges(domain, type, &ranges);
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while ((dev = largest_resource(domain->downstream, &res, type_mask, type))) {
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if (!res->size)
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continue;
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@ -557,7 +554,6 @@ void allocate_resources(const struct device *root)
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return;
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for (child = root->downstream->children; child; child = child->sibling) {
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if (child->path.type != DEVICE_PATH_DOMAIN)
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continue;
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@ -26,7 +26,6 @@ static void print_guid(int log_level, const EFI_GUID *g)
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printk(log_level, "GUID: %08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x",
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g->Data1, g->Data2, g->Data3, g->Data4[0], g->Data4[1], g->Data4[2],
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g->Data4[3], g->Data4[4], g->Data4[5], g->Data4[6], g->Data4[7]);
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}
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static bool compare_guid(const EFI_GUID *a, const EFI_GUID *b)
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@ -164,7 +163,6 @@ static enum cb_err validate_fv_header(const struct region_device *rdev,
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printk(BIOS_SPEW, PREFIX "UEFI FV with size %lld found\n", fw_vol_hdr->FvLength);
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return CB_SUCCESS;
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}
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static enum cb_err
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@ -4,7 +4,6 @@
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#define __DRIVERS_I2C_PTN3460_CHIP_H__
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struct drivers_i2c_ptn3460_config {
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};
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#endif /* __DRIVERS_I2C_PTN3460_CHIP_H__ */
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@ -446,7 +446,6 @@ static tpm_result_t cr50_i2c_probe(uint32_t *did_vid)
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printk(BIOS_INFO, "Probing TPM I2C: ");
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for (retries = 100; retries > 0; retries--) {
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rc = cr50_i2c_read(TPM_DID_VID(0), (uint8_t *)did_vid, 4);
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/* Exit once DID and VID verified */
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@ -117,7 +117,6 @@ static int iic_tpm_read(uint8_t addr, uint8_t *buffer, size_t len)
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buffer, len);
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if (rc == 0)
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break; /* success, break to skip sleep */
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}
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break;
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@ -245,7 +245,6 @@ void print_hob_type_structure(u16 hob_type, void *hob_list_ptr)
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printk(BIOS_DEBUG, "%p: hob_list_ptr\n", hob_list_ptr);
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for (current_hob = hob_list_ptr; !END_OF_HOB_LIST(current_hob);
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current_hob = GET_NEXT_HOB(current_hob)) {
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EFI_HOB_GENERIC_HEADER *current_header_ptr =
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(EFI_HOB_GENERIC_HEADER *)current_hob;
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@ -97,7 +97,6 @@ int smmstore_lookup_region(struct region_device *rstore)
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static struct region_device rdev;
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if (!done) {
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done = 1;
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if (fmap_locate_area_as_rdev_rw(SMMSTORE_REGION, &rdev)) {
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@ -48,7 +48,6 @@ void ec_mirror_flag(void)
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if (CONFIG(EC_STARLABS_MIRROR_SUPPORT) &&
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(CONFIG(DRIVERS_INTEL_USB4_RETIMER) || get_uint_option("mirror_flag", 0)) &&
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(ec_version != CONFIG_EC_STARLABS_MIRROR_VERSION)) {
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printk(BIOS_ERR, "ITE: EC version 0x%x doesn't match coreboot version 0x%x.\n",
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ec_version, CONFIG_EC_STARLABS_MIRROR_VERSION);
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@ -387,7 +387,6 @@ static void lb_strings(struct lb_header *header)
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rec->size = ALIGN_UP(sizeof(*rec) + len + 1, LB_ENTRY_ALIGN);
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memcpy(rec->string, strings[i].string, len+1);
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}
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}
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static void lb_record_version_timestamp(struct lb_header *header)
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@ -1389,7 +1389,6 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
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out->mode_is_supported[j] = 1;
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}
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}
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}
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printk(BIOS_SPEW, "Standard timings supported:\n");
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@ -316,7 +316,6 @@ static struct state_tracker {
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static void bs_walk_state_machine(void)
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{
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while (1) {
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struct boot_state *state;
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boot_state_t next_id;
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@ -183,7 +183,6 @@ static void merge_add_memranges(struct memranges *ranges,
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/* The new entry starts after this one. */
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if (begin > cur->end)
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continue;
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}
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/* Add new entry and merge with neighbors. */
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@ -389,7 +388,6 @@ memranges_find_entry(struct memranges *ranges, resource_t limit, resource_t size
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return NULL;
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memranges_each_entry(r, ranges) {
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if (r->tag != tag)
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continue;
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@ -242,7 +242,6 @@ int region_file_init(struct region_file *f, const struct region_device *p)
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int region_file_data(const struct region_file *f, struct region_device *rdev)
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{
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size_t offset;
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size_t size;
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@ -57,5 +57,4 @@ int checkstack(void *top_of_stack, int core)
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}
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return 0;
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}
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@ -7,7 +7,6 @@
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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/* GPIO A0-A6, A9-A10 default function is NF1 for eSPI interface when
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eSPI is enabled */
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@ -3,7 +3,6 @@
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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/*
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* VerbTable: CFL Display Audio Codec
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* Revision ID = 0xFF
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@ -3,7 +3,6 @@
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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/*
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* VerbTable: CFL Display Audio Codec
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* Revision ID = 0xFF
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@ -6,7 +6,6 @@
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#include <soc/romstage.h>
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static const struct mb_cfg ehlcrb_lpddr4x_memcfg_cfg = {
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.dq_map[DDR_CH0] = {
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{0xf, 0xf0},
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{0xf, 0xf0},
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@ -7,7 +7,6 @@
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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/* WWAN_WAKE_N */
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PAD_CFG_GPI_SCI(GPP_A10, NONE, DEEP, LEVEL, INVERT),
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@ -8,7 +8,6 @@
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#include <soc/romstage.h>
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static const struct mb_cfg jslrvp_ddr4_memcfg_cfg = {
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.dq_map[DDR_CH0] = {
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{0xf, 0xf0},
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{0xf, 0xf0},
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@ -51,7 +50,6 @@ static const struct mb_cfg jslrvp_ddr4_memcfg_cfg = {
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};
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static const struct mb_cfg jslrvp_lpddr4_memcfg_cfg = {
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.dq_map[DDR_CH0] = {
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{0xf, 0xf0},
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{0xf, 0xf0},
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@ -48,7 +48,6 @@ static void ioexpander_init(void *unused)
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/* Port 0 Configuration */
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i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_1_ADDR, IO_EXPANDER_P0CONF,
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0x00);
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}
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BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, ioexpander_init, NULL);
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@ -6,7 +6,6 @@
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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0x8086280B,
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0x00000000,
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0x00000005,
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@ -6,7 +6,6 @@
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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0x8086280B,
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0x00000000,
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0x00000005,
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@ -6,7 +6,6 @@
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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0x8086280B,
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0x00000000,
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0x00000005,
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@ -55,7 +55,6 @@ void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
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} else {
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memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
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}
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}
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uintptr_t mainboard_get_spd_data(void)
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@ -96,6 +96,5 @@ static void fw_config_handle(void *unused)
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printk(BIOS_INFO, "Configure GPIOs for SoundWire audio (onboard codec).\n");
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gpio_configure_pads(sndw_alc711_enable_pads, ARRAY_SIZE(i2s_enable_pads));
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}
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
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@ -5,7 +5,6 @@
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* UART0 RX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* UART0 TX */
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@ -241,6 +241,5 @@ static struct soc_gpio_config gpio_config = {
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struct soc_gpio_config *mainboard_get_gpios(void)
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{
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return &gpio_config;
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}
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@ -48,5 +48,4 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
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bool half_populated = false;
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memcfg_init(mupd, mem_config, &spd_info, half_populated);
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}
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@ -232,6 +232,5 @@ static struct soc_gpio_config gpio_config = {
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struct soc_gpio_config *mainboard_get_gpios(void)
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{
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return &gpio_config;
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}
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@ -7,7 +7,6 @@
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/* Pad configuration was generated automatically using intelp2m utility */
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Community 0 ------- */
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/* ------- GPIO Group GPP_A ------- */
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@ -15,7 +15,6 @@
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/* PAD configuration was generated automatically using intelp2m utility */
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Community 0 ------- */
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/* ------- GPIO Group GPP_B ------- */
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@ -5,7 +5,6 @@
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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/* Community 0 - GpioGroup GPP_B */
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PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */
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PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */
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@ -6,7 +6,6 @@
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#include <soc/romstage.h>
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static const struct mb_cfg fa_ehl_lpddr4x_memcfg_cfg = {
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.dq_map[DDR_CH0] = {
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{0xf, 0xf0},
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{0xf, 0xf0},
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@ -7,7 +7,6 @@
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EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
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more logical grouping. */
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static const struct pad_config gpio_table[] = {
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/* Southwest Community */
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/* PCIE_WAKE[0:3]_N */
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@ -7,7 +7,6 @@
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EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
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more logical grouping. */
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static const struct pad_config gpio_table[] = {
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/* Southwest Community */
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/* EXT_WAKE0_1V8# */
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@ -7,7 +7,6 @@
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EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
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more logical grouping. */
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static const struct pad_config gpio_table[] = {
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/* Southwest Community */
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/* PCIE_WAKE[0:3]_N */
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@ -7,7 +7,6 @@
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EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
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more logical grouping. */
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static const struct pad_config gpio_table[] = {
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/* Southwest Community */
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/* PCIE_WAKE[0:3]_N */
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@ -7,7 +7,6 @@
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EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
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more logical grouping. */
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static const struct pad_config gpio_table[] = {
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/* Southwest Community */
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/* PCIE_WAKE[0:3]_N */
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@ -6,7 +6,6 @@
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#include <soc/romstage.h>
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static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
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.dq_map[DDR_CH0] = {
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{0xf, 0xf0},
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{0xf, 0xf0},
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@ -5,7 +5,6 @@
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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/* Community 0 - GpioGroup GPP_B */
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PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */
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PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */
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@ -6,7 +6,6 @@
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#include <soc/romstage.h>
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static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
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.dq_map[DDR_CH0] = {
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{0xf, 0xf0},
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{0xf, 0xf0},
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@ -5,7 +5,6 @@
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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/* Community 0 - GpioGroup GPP_B */
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PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */
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PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */
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@ -6,7 +6,6 @@
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#include <soc/romstage.h>
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static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
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.dq_map[DDR_CH0] = {
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{0xf, 0xf0},
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{0xf, 0xf0},
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@ -6,7 +6,6 @@
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#include <soc/romstage.h>
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static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
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.dq_map[DDR_CH0] = {
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{0xf, 0xf0},
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{0xf, 0xf0},
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@ -5,7 +5,6 @@
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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/* Community 0 - GpioGroup GPP_B */
|
||||
PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */
|
||||
PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */
|
||||
|
||||
@ -6,7 +6,6 @@
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
|
||||
|
||||
.dq_map[DDR_CH0] = {
|
||||
{0xf, 0xf0},
|
||||
{0xf, 0xf0},
|
||||
|
||||
@ -241,7 +241,6 @@ static void add_ivhd_device_entries(struct device *parent, struct device *dev,
|
||||
}
|
||||
|
||||
if (dev->path.type == DEVICE_PATH_PCI) {
|
||||
|
||||
if ((dev->upstream->secondary == 0x0) &&
|
||||
(dev->path.pci.devfn == 0x0))
|
||||
*root_level = depth;
|
||||
|
||||
@ -340,7 +340,6 @@ static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
|
||||
if (value > 2)
|
||||
die("Bad SPD value\n");
|
||||
if (value == 2) {
|
||||
|
||||
pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently
|
||||
value = smbus_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
|
||||
if (value < 0)
|
||||
@ -413,14 +412,12 @@ static struct dimm_size spd_get_dimm_size(unsigned int dimm_socket_address)
|
||||
struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address);
|
||||
|
||||
if (sz.side1 > 0) {
|
||||
|
||||
value = smbus_read_byte(dimm_socket_address, SPD_NUM_ROWS);
|
||||
die_on_spd_error(value);
|
||||
|
||||
sz.side1 += value & 0xf;
|
||||
|
||||
if (sz.side2 > 0) {
|
||||
|
||||
// Double-sided DIMM
|
||||
if (value & 0xF0)
|
||||
sz.side2 += value >> 4; // Asymmetric
|
||||
@ -496,7 +493,6 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
|
||||
// since we only support dual-channel.
|
||||
|
||||
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
|
||||
|
||||
uint16_t channel0_dimm = ctrl->channel0[i];
|
||||
uint16_t channel1_dimm = ctrl->channel1[i];
|
||||
uint8_t bDualChannel = 1;
|
||||
@ -565,7 +561,6 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
|
||||
// NOTE: unpopulated DIMMs cause read to fail
|
||||
spd_value = smbus_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
|
||||
if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
|
||||
|
||||
printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
|
||||
continue;
|
||||
}
|
||||
@ -580,7 +575,6 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
|
||||
if (!are_spd_values_equal
|
||||
(dual_channel_parameters[j], channel0_dimm,
|
||||
channel1_dimm)) {
|
||||
|
||||
bDualChannel = 0;
|
||||
break;
|
||||
}
|
||||
@ -653,7 +647,6 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
|
||||
* Seems like rows 4-7 overlap with 0-3.
|
||||
*/
|
||||
for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
|
||||
|
||||
uint8_t dimm_end_64M_multiple = pci_read_config8(MCHDEV, DRB_ROW_0 + i);
|
||||
|
||||
if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
|
||||
@ -800,7 +793,6 @@ static void configure_e7501_ram_addresses(const struct mem_controller
|
||||
pci_write_config32(MCHDEV, DRB_ROW_4, 0);
|
||||
|
||||
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
|
||||
|
||||
uint16_t dimm_socket_address = ctrl->channel0[i];
|
||||
struct dimm_size sz;
|
||||
|
||||
@ -1020,7 +1012,6 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl,
|
||||
uint32_t dimm_compatible_cas_latencies;
|
||||
|
||||
for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
|
||||
|
||||
uint16_t dimm_socket_address;
|
||||
|
||||
if (!(dimm_mask & (1 << i)))
|
||||
@ -1098,7 +1089,6 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl,
|
||||
dram_timing |= DRT_CAS_2_0;
|
||||
dram_read_timing |= 0x0222;
|
||||
} else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
|
||||
|
||||
uint32_t dram_row_attributes =
|
||||
pci_read_config32(MCHDEV, DRA);
|
||||
|
||||
@ -1111,7 +1101,6 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl,
|
||||
&& (dram_row_attributes & 0xff00)
|
||||
&& (dram_row_attributes & 0xff0000)
|
||||
&& (dram_row_attributes & 0xff000000)) {
|
||||
|
||||
// All slots populated
|
||||
dram_read_timing |= 0x0882;
|
||||
} else {
|
||||
@ -1179,7 +1168,6 @@ static void configure_e7501_dram_controller_mode(const struct mem_controller *ct
|
||||
*/
|
||||
|
||||
for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
|
||||
|
||||
uint32_t dimm_refresh_mode;
|
||||
int value;
|
||||
uint16_t dimm_socket_address;
|
||||
@ -1250,7 +1238,6 @@ static void configure_e7501_row_attributes(const struct mem_controller
|
||||
uint32_t row_attributes = 0;
|
||||
|
||||
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
|
||||
|
||||
uint16_t dimm_socket_address = ctrl->channel0[i];
|
||||
struct dimm_size page_size;
|
||||
struct dimm_size sdram_width;
|
||||
@ -1300,7 +1287,6 @@ static void enable_e7501_clocks(uint8_t dimm_mask)
|
||||
pci_write_config8(MCHDEV, 0x8e, 0xb0);
|
||||
|
||||
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
|
||||
|
||||
uint8_t socket_mask = 1 << i;
|
||||
|
||||
if (dimm_mask & socket_mask)
|
||||
@ -1702,7 +1688,6 @@ void sdram_initialize(void)
|
||||
|
||||
/* If this is a warm boot, some initialisation can be skipped */
|
||||
if (!e7505_mch_is_ready()) {
|
||||
|
||||
/* The real MCH initialisation. */
|
||||
timestamp_add_now(TS_INITRAM_START);
|
||||
|
||||
|
||||
@ -127,5 +127,4 @@ void fill_postcar_frame(struct postcar_frame *pcf)
|
||||
MTRR_TYPE_WRBACK);
|
||||
postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
|
||||
northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
|
||||
|
||||
}
|
||||
|
||||
@ -36,7 +36,6 @@ static unsigned long acpi_fill_dmar(unsigned long current)
|
||||
|
||||
/* VTVC0BAR has to be set, enabled, and in 32-bit space */
|
||||
if (vtvc0bar && vtvc0en && !mchbar_read32(VTVC0BAR + 4)) {
|
||||
|
||||
const unsigned long tmp = current;
|
||||
current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
|
||||
current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR,
|
||||
|
||||
@ -124,7 +124,6 @@ u32 gtt_read(u32 reg)
|
||||
u32 val;
|
||||
val = read32(res2mmio(gtt_res, reg, 0));
|
||||
return val;
|
||||
|
||||
}
|
||||
|
||||
void gtt_write(u32 reg, u32 data)
|
||||
|
||||
@ -59,5 +59,4 @@ void fill_postcar_frame(struct postcar_frame *pcf)
|
||||
top_of_ram = (uintptr_t)cbmem_top();
|
||||
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
|
||||
MTRR_TYPE_WRBACK);
|
||||
|
||||
}
|
||||
|
||||
@ -755,7 +755,6 @@ static void set_dram_row_attributes(void)
|
||||
/* This is 440BX! We do EDO too! */
|
||||
if (value == SPD_MEMORY_TYPE_EDO
|
||||
|| value == SPD_MEMORY_TYPE_SDRAM) {
|
||||
|
||||
if (value == SPD_MEMORY_TYPE_EDO) {
|
||||
edo = 1;
|
||||
} else if (value == SPD_MEMORY_TYPE_SDRAM) {
|
||||
|
||||
@ -290,7 +290,6 @@ static void i945_setup_egress_port(void)
|
||||
printk(BIOS_DEBUG, "timeout!\n");
|
||||
else
|
||||
printk(BIOS_DEBUG, "ok\n");
|
||||
|
||||
}
|
||||
|
||||
static void ich7_setup_dmi_rcrb(void)
|
||||
|
||||
@ -537,7 +537,6 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf,
|
||||
vga_sr_write(1, vga_sr_read(1) & ~0x20);
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
/* compare the header of the vga edid header */
|
||||
|
||||
@ -49,7 +49,6 @@ static int get_dimm_spd_address(struct sys_info *sysinfo, int device)
|
||||
return sysinfo->spd_addresses[device];
|
||||
else
|
||||
return 0x50 + device;
|
||||
|
||||
}
|
||||
|
||||
static __attribute__((noinline)) void do_ram_command(u32 command)
|
||||
@ -226,7 +225,6 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
|
||||
/* Write back clears bit 2 */
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
|
||||
do_reset = true;
|
||||
|
||||
}
|
||||
|
||||
if (reg8 & (1 << 7)) {
|
||||
@ -289,7 +287,6 @@ struct timings {
|
||||
*/
|
||||
static void gather_common_timing(struct sys_info *sysinfo, struct timings *saved_timings)
|
||||
{
|
||||
|
||||
int i, j;
|
||||
u8 raw_spd[SPD_SIZE_MAX_DDR2];
|
||||
u8 dimm_mask = 0;
|
||||
@ -2313,7 +2310,6 @@ static void sdram_power_management(struct sys_info *sysinfo)
|
||||
|
||||
static void sdram_thermal_management(void)
|
||||
{
|
||||
|
||||
mchbar_write8(TCO1, 0);
|
||||
mchbar_write8(TCO0, 0);
|
||||
|
||||
|
||||
@ -83,7 +83,6 @@ static void set_receive_enable(int channel_offset, u8 medium, u8 coarse)
|
||||
reg32 |= medium;
|
||||
}
|
||||
mchbar_write32(RCVENMT, reg32);
|
||||
|
||||
}
|
||||
|
||||
static int normalize(int channel_offset, u8 *mediumcoarse, u8 *fine)
|
||||
@ -190,7 +189,6 @@ static int find_strobes_low(int channel_offset, u8 *mediumcoarse, u8 *fine,
|
||||
continue;
|
||||
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "Could not find low strobe\n");
|
||||
@ -200,7 +198,6 @@ static int find_strobes_low(int channel_offset, u8 *mediumcoarse, u8 *fine,
|
||||
static int find_strobes_edge(int channel_offset, u8 *mediumcoarse, u8 *fine,
|
||||
struct sys_info *sysinfo)
|
||||
{
|
||||
|
||||
int counter;
|
||||
u32 rcvenmt;
|
||||
|
||||
|
||||
@ -168,7 +168,6 @@ static void ironlake_init(void *const chip_info)
|
||||
const struct device *const d0f0 = pcidev_on_root(0, 0);
|
||||
if (d0f0)
|
||||
pci_update_config32(d0f0, DEVEN, deven_mask, 0);
|
||||
|
||||
}
|
||||
|
||||
static struct device_operations mc_ops = {
|
||||
|
||||
@ -1552,7 +1552,6 @@ static void read_4090(struct raminfo *info)
|
||||
rank), 9)
|
||||
+ (i == 1) * 11; // !!!!
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static u32 get_etalon2(int flip, u32 addr)
|
||||
@ -2759,7 +2758,6 @@ static void do_ram_training(struct raminfo *info)
|
||||
timings);
|
||||
totalrank++;
|
||||
}
|
||||
|
||||
}
|
||||
} else {
|
||||
for (reg_178 = reg178_center - 12;
|
||||
|
||||
@ -76,7 +76,6 @@ static uintptr_t northbridge_get_tseg_base(void)
|
||||
uintptr_t cbmem_top_chipset(void)
|
||||
{
|
||||
return ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB);
|
||||
|
||||
}
|
||||
|
||||
void smm_region(uintptr_t *start, size_t *size)
|
||||
|
||||
@ -377,7 +377,6 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
|
||||
|
||||
/* Before reusing training data, assert that the CPU has not been replaced */
|
||||
if (ctrl_cached && cpuid != ctrl_cached->cpu) {
|
||||
|
||||
/* It is not really worrying on a cold boot, but fatal when resuming from S3 */
|
||||
printk(s3resume ? BIOS_ALERT : BIOS_NOTICE,
|
||||
"CPUID %x differs from stored CPUID %x, CPU was replaced!\n",
|
||||
|
||||
@ -64,7 +64,6 @@ void dram_find_common_params(ramctr_timing *ctrl)
|
||||
valid_dimms = 0;
|
||||
|
||||
FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) {
|
||||
|
||||
const struct dimm_attr_ddr3_st *dimm = &dimms->dimm[channel][slot];
|
||||
if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3)
|
||||
continue;
|
||||
@ -1138,7 +1137,6 @@ static void fine_tune_rcven_pi(ramctr_timing *ctrl, int channel, int slotrank, i
|
||||
int lane, i;
|
||||
|
||||
for (rcven_delta = -25; rcven_delta <= 25; rcven_delta++) {
|
||||
|
||||
FOR_ALL_LANES {
|
||||
ctrl->timings[channel][slotrank].lanes[lane].rcven
|
||||
= upperA[lane] + rcven_delta + QCLK_PI;
|
||||
@ -1358,7 +1356,6 @@ int receive_enable_calibration(ramctr_timing *ctrl)
|
||||
FOR_ALL_LANES {
|
||||
ctrl->timings[channel][slotrank].lanes[lane].rcven -= QCLK_PI;
|
||||
upperA[lane] -= QCLK_PI;
|
||||
|
||||
}
|
||||
} else if (some_high) {
|
||||
ctrl->timings[channel][slotrank].roundtrip_latency++;
|
||||
@ -1657,7 +1654,6 @@ static void train_write_flyby(ramctr_timing *ctrl)
|
||||
fill_pattern1(ctrl, channel);
|
||||
}
|
||||
FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS {
|
||||
|
||||
/* Reset read and write WDB pointers */
|
||||
mchbar_write32(IOSAV_DATA_CTL_ch(channel), 0x10001);
|
||||
|
||||
@ -2501,7 +2497,6 @@ int aggressive_write_training(ramctr_timing *ctrl)
|
||||
upper[channel][slotrank][lane] =
|
||||
MIN(rn.end - ctrl->tx_dq_offset[i],
|
||||
upper[channel][slotrank][lane]);
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -2621,7 +2616,6 @@ void channel_scrub(ramctr_timing *ctrl)
|
||||
rowsize = 1 << ctrl->info.dimm[channel][slotrank >> 1].row_bits;
|
||||
for (bank = 0; bank < 8; bank++) {
|
||||
for (row = 0; row < rowsize; row += 16) {
|
||||
|
||||
u8 gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD);
|
||||
const struct iosav_ssq sequence[] = {
|
||||
/*
|
||||
|
||||
@ -295,7 +295,6 @@ static void devicetree_fill_pei_data(struct pei_data *pei_data)
|
||||
case 800:
|
||||
pei_data->max_ddr3_freq = 1600;
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@ -274,7 +274,6 @@ static unsigned int get_mem_min_tck(void)
|
||||
|
||||
/* If non-zero, it was set in the devicetree */
|
||||
if (cfg->max_mem_clock_mhz) {
|
||||
|
||||
if (cfg->max_mem_clock_mhz >= 1066)
|
||||
return TCK_1066MHZ;
|
||||
|
||||
|
||||
@ -147,7 +147,6 @@ static enum cb_err ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
|
||||
dram_print_spd_ddr2(&decoded_dimm);
|
||||
|
||||
if (!(decoded_dimm.width & (0x08 | 0x10))) {
|
||||
|
||||
printk(BIOS_ERR, "DIMM%d Unsupported width: x%d. Disabling dimm\n",
|
||||
dimm_idx, s->dimms[dimm_idx].width);
|
||||
return CB_ERR;
|
||||
@ -523,7 +522,6 @@ static void find_dimm_config(struct sysinfo *s)
|
||||
}
|
||||
printk(BIOS_DEBUG, " Config[CH%d] : %d\n", chan, s->dimm_config[chan]);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static void checkreset_ddr2(int boot_path)
|
||||
|
||||
@ -247,7 +247,6 @@ enum dc_winc_filter_p {
|
||||
|
||||
/* Window A/B/C register 0x500 ~ 0x628 */
|
||||
struct dc_winc_reg {
|
||||
|
||||
/* Address 0x500 */
|
||||
u32 color_palette; /* _WINC_COLOR_PALETTE_0 */
|
||||
|
||||
|
||||
@ -440,7 +440,6 @@ static void tegra_dc_dp_dump_link_cfg(struct tegra_dc_dp_data *dp,
|
||||
static int _tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp,
|
||||
struct tegra_dc_dp_link_config *cfg)
|
||||
{
|
||||
|
||||
switch (cfg->link_bw){
|
||||
case SOR_LINK_SPEED_G1_62:
|
||||
if (cfg->max_link_bw > SOR_LINK_SPEED_G1_62)
|
||||
|
||||
@ -51,7 +51,6 @@ enum {
|
||||
* Defines the SDRAM parameter structure
|
||||
*/
|
||||
struct sdram_params {
|
||||
|
||||
/* Specifies the type of memory device */
|
||||
uint32_t MemoryType;
|
||||
|
||||
|
||||
@ -722,7 +722,6 @@ void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor)
|
||||
tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1);
|
||||
|
||||
tegra_dc_sor_set_dp_mode(sor, link_cfg);
|
||||
|
||||
}
|
||||
|
||||
void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor)
|
||||
|
||||
@ -38,7 +38,6 @@ int sdram_size_mb(void)
|
||||
static void carveout_from_regs(uintptr_t *base_mib, size_t *size_mib,
|
||||
uint32_t bom, uint32_t bom_hi, uint32_t size)
|
||||
{
|
||||
|
||||
/* All size regs of carveouts are in MiB. */
|
||||
if (size == 0)
|
||||
return;
|
||||
|
||||
@ -452,7 +452,6 @@ static void tegra_dc_dp_dump_link_cfg(struct tegra_dc_dp_data *dp,
|
||||
static int _tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp,
|
||||
struct tegra_dc_dp_link_config *link_cfg)
|
||||
{
|
||||
|
||||
switch (link_cfg->link_bw) {
|
||||
case SOR_LINK_SPEED_G1_62:
|
||||
if (link_cfg->max_link_bw > SOR_LINK_SPEED_G1_62)
|
||||
@ -1457,7 +1456,6 @@ static int tegra_dc_dp_sink_out_of_sync(struct tegra_dc_dp_data *dp,
|
||||
static void tegra_dc_dp_check_sink(struct tegra_dc_dp_data *dp,
|
||||
struct soc_nvidia_tegra210_config *config)
|
||||
{
|
||||
|
||||
u8 max_retry = 3;
|
||||
int delay_frame;
|
||||
|
||||
|
||||
@ -30,7 +30,6 @@ enum {
|
||||
* currently the I2C is 0-based and SPI is 1-based in its indexing.
|
||||
*/
|
||||
enum {
|
||||
|
||||
I2C1_BUS = 0,
|
||||
I2C2_BUS = 1,
|
||||
I2C3_BUS = 2,
|
||||
|
||||
@ -54,7 +54,6 @@ enum {
|
||||
* Defines the SDRAM parameter structure
|
||||
*/
|
||||
struct sdram_params {
|
||||
|
||||
/* Specifies the type of memory device */
|
||||
uint32_t MemoryType;
|
||||
|
||||
|
||||
@ -13,7 +13,6 @@
|
||||
|
||||
int mipi_dphy_set_timing(struct tegra_dsi *dsi)
|
||||
{
|
||||
|
||||
u32 freq = (dsi->clk_rate * 2) / 1000000;
|
||||
|
||||
u32 thsdexit = (DSI_PHY_TIMING_DIV(120, (freq)));
|
||||
|
||||
@ -798,7 +798,6 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param,
|
||||
uint32_t val = 0;
|
||||
|
||||
if (param->MemoryType == NvBootMemoryType_LpDdr4) {
|
||||
|
||||
val = (param->EmcPinGpioEn << EMC_PIN_GPIOEN_SHIFT) |
|
||||
(param->EmcPinGpio << EMC_PIN_GPIO_SHIFT);
|
||||
write32(®s->pin, val);
|
||||
@ -835,7 +834,6 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param,
|
||||
die("Failed to program EMC pin.");
|
||||
|
||||
if (param->MemoryType != NvBootMemoryType_LpDdr4) {
|
||||
|
||||
/* Send NOP (trigger just needs to be non-zero) */
|
||||
writebits(((1 << EMC_NOP_CMD_SHIFT) |
|
||||
(param->EmcDevSelect << EMC_NOP_DEV_SELECTN_SHIFT)),
|
||||
|
||||
@ -716,7 +716,6 @@ void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor)
|
||||
tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1);
|
||||
|
||||
tegra_dc_sor_set_dp_mode(sor, link_cfg);
|
||||
|
||||
}
|
||||
|
||||
void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor)
|
||||
|
||||
@ -411,7 +411,6 @@ void clock_gate(void)
|
||||
clrbits32(&exynos_clock->gate_ip_cdrex, CLK_DPHY0_MASK |
|
||||
CLK_DPHY1_MASK |
|
||||
CLK_TZASC_DRBXR_MASK);
|
||||
|
||||
}
|
||||
|
||||
void clock_init_dp_clock(void)
|
||||
|
||||
@ -115,7 +115,6 @@ int s5p_dp_init_analog_func(struct s5p_dp_device *dp)
|
||||
|
||||
/* Power up PLL */
|
||||
if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
|
||||
|
||||
clrbits32(&base->dp_pll_ctl, DP_PLL_PD);
|
||||
|
||||
stopwatch_init_msecs_expire(&sw, PLL_LOCK_TIMEOUT);
|
||||
|
||||
@ -186,7 +186,6 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
|
||||
}
|
||||
|
||||
if (mem->gate_leveling_enable) {
|
||||
|
||||
write32(&exynos_phy0_control->phy_con0, PHY_CON0_RESET_VAL);
|
||||
write32(&exynos_phy1_control->phy_con0, PHY_CON0_RESET_VAL);
|
||||
|
||||
|
||||
@ -142,7 +142,6 @@ static unsigned int exynos_dp_read_edid(void)
|
||||
exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
|
||||
DPCD_TEST_EDID_CHECKSUM_WRITE);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return 0;
|
||||
@ -338,7 +337,6 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
|
||||
if (ret != EXYNOS_DP_SUCCESS) {
|
||||
printk(BIOS_ERR, "DP write_to_dpcd failed\n");
|
||||
return -1;
|
||||
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
||||
@ -110,7 +110,6 @@ static inline void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_ad
|
||||
_REG32(225<<2, ahbregaddr) = 0xFFFFFFFF;
|
||||
_REG32(208<<2, ahbregaddr) |= (1 << AXI0_ADDRESS_RANGE_ENABLE);
|
||||
_REG32(208<<2, ahbregaddr) |= (1 << PORT_ADDR_PROTECTION_EN_OFFSET);
|
||||
|
||||
}
|
||||
|
||||
static inline void ux00ddr_disableaxireadinterleave(size_t ahbregaddr) {
|
||||
|
||||
@ -114,5 +114,4 @@ void intel_acpi_pcie_hotplug_generator(bool *hotplug_map, int port_number)
|
||||
}
|
||||
acpigen_pop_len();
|
||||
acpigen_pop_len();
|
||||
|
||||
}
|
||||
|
||||
@ -320,7 +320,6 @@ static int block_cmd_loop(uintptr_t base, u8 *buf, size_t max_bytes, int flags)
|
||||
host_and_or(base, SMBHSTCTL, 0xff,
|
||||
SMBHSTCNT_LAST_BYTE);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Engine internally completes the transaction
|
||||
|
||||
@ -913,7 +913,6 @@ static const struct spi_flash_ops spi_flash_ops = {
|
||||
static int spi_flash_programmer_probe(const struct spi_slave *spi,
|
||||
struct spi_flash *flash)
|
||||
{
|
||||
|
||||
if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
|
||||
return spi_flash_generic_probe(spi, flash);
|
||||
|
||||
|
||||
@ -16,7 +16,6 @@
|
||||
*/
|
||||
void acpi_fill_fadt(acpi_fadt_t *fadt)
|
||||
{
|
||||
|
||||
fadt->pm1a_evt_blk = DEFAULT_PMBASE;
|
||||
fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL;
|
||||
|
||||
|
||||
@ -54,7 +54,6 @@ void sata_enable(struct device *dev)
|
||||
config->sata_mode = SATA_MODE_IDE_PLAIN;
|
||||
printk(BIOS_DEBUG, "AHCI not supported, falling back to plain mode.\n");
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if (config->sata_mode == SATA_MODE_AHCI) {
|
||||
|
||||
@ -52,7 +52,6 @@ static void pci_init(struct device *dev)
|
||||
|
||||
/* Enable expresscard hotplug events. */
|
||||
if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
|
||||
|
||||
pci_or_config32(dev, 0xd8, 1 << 30);
|
||||
pci_write_config16(dev, 0x42, 0x142);
|
||||
}
|
||||
|
||||
@ -52,7 +52,6 @@ static void pci_init(struct device *dev)
|
||||
|
||||
/* Enable expresscard hotplug events. */
|
||||
if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
|
||||
|
||||
pci_or_config32(dev, 0xd8, 1 << 30);
|
||||
pci_write_config16(dev, 0x42, 0x142);
|
||||
}
|
||||
|
||||
@ -20,7 +20,6 @@ static void p64h2_pcix_init(struct device *dev)
|
||||
pci_write_config32(dev, ACNF, dword);
|
||||
byte = 0x08;
|
||||
pci_write_config8(dev, MTT, byte);
|
||||
|
||||
}
|
||||
static struct device_operations pcix_ops = {
|
||||
.read_resources = pci_bus_read_resources,
|
||||
|
||||
@ -231,7 +231,6 @@ static void pcie_enable_clock_gating(void)
|
||||
rp = root_port_number(dev);
|
||||
|
||||
if (!is_rp_enabled(rp)) {
|
||||
|
||||
/* Configure shared resource clock gating. */
|
||||
if (rp == 1 || rp == 5 || (rp == 6 && is_lp))
|
||||
pci_or_config8(dev, 0xe1, 0x3c);
|
||||
|
||||
@ -142,7 +142,6 @@ static void rl5c476_init(struct device *dev)
|
||||
|
||||
static void rl5c476_read_resources(struct device *dev)
|
||||
{
|
||||
|
||||
struct resource *resource;
|
||||
|
||||
/* For CF socket we need an extra memory window for
|
||||
@ -173,7 +172,6 @@ static void rl5c476_set_resources(struct device *dev)
|
||||
}
|
||||
|
||||
pci_dev_set_resources(dev);
|
||||
|
||||
}
|
||||
|
||||
static void rl5c476_set_subsystem(struct device *dev, unsigned int vendor,
|
||||
|
||||
@ -10,7 +10,6 @@
|
||||
|
||||
static void ti_pci1x2y_init(struct device *dev)
|
||||
{
|
||||
|
||||
printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
|
||||
struct southbridge_ti_pci1x2x_config *conf = dev->chip_info;
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user