31402178c5
Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
42 lines
1.0 KiB
C
42 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include "82870.h"
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static void p64h2_pcix_init(struct device *dev)
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{
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u32 dword;
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u8 byte;
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/* The purpose of changes to HCCR, ACNF, and MTT is to speed
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* up the PCI bus for cards having high speed transfers.
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*/
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dword = 0xc2040002;
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pci_write_config32(dev, HCCR, dword);
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dword = 0x0000c3bf;
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pci_write_config32(dev, ACNF, dword);
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byte = 0x08;
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pci_write_config8(dev, MTT, byte);
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}
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static struct device_operations pcix_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.init = p64h2_pcix_init,
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.scan_bus = pci_scan_bridge,
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.reset_bus = pci_bus_reset,
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};
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static const struct pci_driver pcix_driver __pci_driver = {
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.ops = &pcix_ops,
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.vendor = PCI_VID_INTEL,
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.device = PCI_DID_INTEL_82870_1F0,
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};
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struct chip_operations southbridge_intel_i82870_ops = {
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.name = "Intel 82870",
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};
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