soc/intel/mtl: Hook up GMA ACPI brightness controls

Add function needed to generate ACPI backlight control SSDT, along with
Kconfig values for accessing the registers.

Change-Id: Ied08e5e9fe4913bd60474ed7dcf88b945172558d
Signed-off-by: Jeremy Soller <jeremy@sysetm76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>

src/mainboard/google/brya/variants/nova/overridetree.cb

@@ -6,6 +6,8 @@ chip soc/intel/alderlake
 	register "sagv" = "SaGv_Enabled"
 
 	register "usb2_ports[1]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A3
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A2
 	register "usb2_ports[4]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 4
 	register "usb2_ports[5]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 5
 	register "usb2_ports[6]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 6

src/soc/intel/common/block/crashlog/crashlog.c

@@ -112,7 +112,7 @@ int cpu_cl_poll_mailbox_ready(u32 cl_mailbox_addr)
 	u16 stall_cnt = 0;
 
 	do {
-		cl_mailbox_interface.data = read32((u32 *)cl_mailbox_addr);
+		cl_mailbox_interface.data = read32((u32 *)(uintptr_t)cl_mailbox_addr);
 		udelay(CPU_CRASHLOG_WAIT_STALL);
 		stall_cnt++;
 	} while ((cl_mailbox_interface.fields.busy == 1)
@@ -140,7 +140,7 @@ int cpu_cl_mailbox_cmd(u8 cmd, u8 param)
 	cl_mailbox_intf.fields.param = param;
 	cl_mailbox_intf.fields.busy = 1;
 
-	write32((u32 *)(cl_base_addr + cl_get_cpu_mb_int_addr()),
+	write32((u32 *)(uintptr_t)(cl_base_addr + cl_get_cpu_mb_int_addr()),
 		cl_mailbox_intf.data);
 
 	cpu_cl_poll_mailbox_ready(cl_base_addr + cl_get_cpu_mb_int_addr());
@@ -167,7 +167,7 @@ int pmc_cl_gen_descriptor_table(u32 desc_table_addr,
 				pmc_crashlog_desc_table_t *descriptor_table)
 {
 	int total_data_size = 0;
-	descriptor_table->numb_regions = read32((u32 *)desc_table_addr);
+	descriptor_table->numb_regions = read32((u32 *)(uintptr_t)desc_table_addr);
 	printk(BIOS_DEBUG, "CL PMC desc table: numb of regions is 0x%x at addr 0x%x\n",
 	       descriptor_table->numb_regions, desc_table_addr);
 	for (int i = 0; i < descriptor_table->numb_regions; i++) {
@@ -178,7 +178,7 @@ int pmc_cl_gen_descriptor_table(u32 desc_table_addr,
 			break;
 		}
 		desc_table_addr += 4;
-		descriptor_table->regions[i].data = read32((u32 *)(desc_table_addr));
+		descriptor_table->regions[i].data = read32((u32 *)(uintptr_t)(desc_table_addr));
 		total_data_size += descriptor_table->regions[i].bits.size * sizeof(u32);
 		printk(BIOS_DEBUG, "CL PMC desc table: region 0x%x has size 0x%x at offset 0x%x\n",
 			i, descriptor_table->regions[i].bits.size,
@@ -295,7 +295,7 @@ bool cl_copy_data_from_sram(u32 src_bar,
 
 	u32 src_addr = src_bar + offset;
 
-	u32 data =  read32((u32 *)src_addr);
+	u32 data =  read32((u32 *)(uintptr_t)src_addr);
 
 	/* First 32bits of the record must not be 0xdeadbeef */
 	if (data == INVALID_CRASHLOG_RECORD) {
@@ -320,7 +320,7 @@ bool cl_copy_data_from_sram(u32 src_bar,
 	u32 copied = 0;
 	while (copied < size) {
 		/* DW by DW copy: byte access to PMC SRAM not allowed */
-		*dest_addr = read32((u32 *)src_addr);
+		*dest_addr = read32((u32 *)(uintptr_t)src_addr);
 		dest_addr++;
 		src_addr += 4;
 		copied++;

src/soc/intel/meteorlake/Kconfig

@@ -402,6 +402,18 @@ config BUILDING_WITH_DEBUG_FSP
 	help
 	  Set this option if debug build of FSP is used.
 
+config INTEL_GMA_BCLV_OFFSET
+	default 0xc8258
+
+config INTEL_GMA_BCLV_WIDTH
+	default 32
+
+config INTEL_GMA_BCLM_OFFSET
+	default 0xc8254
+
+config INTEL_GMA_BCLM_WIDTH
+	default 32
+
 config DROP_CPU_FEATURE_PROGRAM_IN_FSP
 	bool
 	default y if MP_SERVICES_PPI_V2_NOOP || CHROMEOS

src/soc/intel/meteorlake/Makefile.mk

@@ -37,6 +37,7 @@ ramstage-y += elog.c
 ramstage-y += espi.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
+ramstage-y += graphics.c
 ramstage-y += lockdown.c
 ramstage-y += p2sb.c
 ramstage-y += pcie_rp.c

src/soc/intel/meteorlake/chip.h

@@ -4,6 +4,7 @@
 #define _SOC_CHIP_H_
 
 #include <drivers/i2c/designware/dw_i2c.h>
+#include <drivers/intel/gma/gma.h>
 #include <device/pci_ids.h>
 #include <gpio.h>
 #include <intelblocks/cfg.h>
@@ -527,6 +528,9 @@ struct soc_intel_meteorlake_config {
 	 * as per `enum slew_rate` data type.
 	 */
 	uint8_t slow_slew_rate_config[NUM_VR_DOMAINS];
+
+	/* i915 struct for GMA backlight control */
+	struct i915_gpu_controller_info gfx;
 };
 
 typedef struct soc_intel_meteorlake_config config_t;

src/soc/intel/meteorlake/crashlog.c

@@ -34,7 +34,7 @@ static u32 disc_tab_addr;
 
 static u64 get_disc_tab_header(void)
 {
-	return read64((void *)disc_tab_addr);
+	return read64((void *)(uintptr_t)disc_tab_addr);
 }
 
 /* Get the SRAM BAR. */
@@ -338,7 +338,7 @@ static bool cpu_cl_gen_discovery_table(void)
 
 	disc_tab_addr = bar_addr + get_disc_table_offset();
 
-	u32 dw0 = read32((u32 *)disc_tab_addr);
+	u32 dw0 = read32((u32 *)(uintptr_t)disc_tab_addr);
 	if (!is_crashlog_data_valid(dw0))
 		return false;
 
@@ -351,7 +351,7 @@ static bool cpu_cl_gen_discovery_table(void)
 	for (int i = 0; i < cpu_cl_disc_tab.header.fields.count; i++) {
 		cur_offset = 8 + 24 * i;
 
-		dw0 = read32((u32 *)disc_tab_addr + cur_offset);
+		dw0 = read32((u32 *)(uintptr_t)disc_tab_addr + cur_offset);
 		if (!is_crashlog_data_valid(dw0))
 			continue;
 
@@ -361,7 +361,7 @@ static bool cpu_cl_gen_discovery_table(void)
 			break;
 		}
 
-		cpu_cl_disc_tab.buffers[i].data = read64((void *)(disc_tab_addr + cur_offset));
+		cpu_cl_disc_tab.buffers[i].data = read64((void *)(uintptr_t)(disc_tab_addr + cur_offset));
 		printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size: "
 			"0x%x offset: 0x%x\n", i,  cpu_cl_disc_tab.buffers[i].fields.size,
 			cpu_cl_disc_tab.buffers[i].fields.offset);
@@ -450,7 +450,7 @@ void cpu_cl_rearm(void)
 	cl_punit_control_interface_t punit_ctrl_intfc;
 	memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
 	punit_ctrl_intfc.fields.set_re_arm = 1;
-	write32((u32 *)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
+	write32((u32 *)(uintptr_t)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
 
 	if (!wait_and_check(CRASHLOG_RE_ARM_STATUS_MASK))
 		printk(BIOS_ERR, "CPU crashlog re_arm not asserted\n");
@@ -480,7 +480,7 @@ void cpu_cl_cleanup(void)
 	cl_punit_control_interface_t punit_ctrl_intfc;
 	memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
 	punit_ctrl_intfc.fields.set_storage_off = 1;
-	write32((u32 *)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
+	write32((u32 *)(uintptr_t)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
 
 	if (!wait_and_check(CRASHLOG_PUNIT_STORAGE_OFF_MASK))
 		printk(BIOS_ERR, "CPU crashlog storage_off not asserted\n");

src/soc/intel/meteorlake/graphics.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <intelblocks/graphics.h>
+#include <soc/ramstage.h>
+
+const struct i915_gpu_controller_info *
+intel_igd_get_controller_info(const struct device *const dev)
+{
+	const struct soc_intel_meteorlake_config *const chip = dev->chip_info;
+	return &chip->gfx;
+}