soc/intel/mtl: Hook up GMA ACPI brightness controls

Add function needed to generate ACPI backlight control SSDT, along with
Kconfig values for accessing the registers.

Change-Id: Ied08e5e9fe4913bd60474ed7dcf88b945172558d
Signed-off-by: Jeremy Soller <jeremy@sysetm76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>

src/include/spd_bin.h

@@ -36,18 +36,6 @@
 #define DDR4_SPD_PART_OFF	329
 #define DDR4_SPD_PART_LEN	20
 #define DDR4_SPD_SN_OFF		325
-#define MAX_SPD_PAGE_SIZE_SPD5	128
-#define MAX_SPD_SIZE		(SPD_PAGE_LEN * 4)
-#define SPD_HUB_MEMREG(addr)	((u8)(0x80 | (addr)))
-#define SPD5_MR11		0x0B
-#define SPD5_MR0		0x00
-#define SPD5_MEMREG_REG(addr)	((u8)((~0x80) & (addr)))
-#define SPD5_MR0_SPD5_HUB_DEV	0x51
-
-struct spd_offset_table {
-	u16 start;		/* Offset 0 */
-	u16 end;		/* Offset 2 */
-};
 
 struct spd_block {
 	u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */

src/lib/spd_cache.c

@@ -209,9 +209,7 @@ enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk)
 
 	dram_type = *(spd_cache + SC_SPD_OFFSET(i) + SPD_DRAM_TYPE);
 
-	if (dram_type == SPD_DRAM_DDR5)
-		blk->len = CONFIG_DIMM_SPD_SIZE;
-	else if (dram_type == SPD_DRAM_DDR4)
+	if (dram_type == SPD_DRAM_DDR4)
 		blk->len = SPD_PAGE_LEN_DDR4;
 	else
 		blk->len = SPD_PAGE_LEN;

src/soc/intel/common/block/smbus/smbuslib.c

@@ -13,11 +13,8 @@ static void update_spd_len(struct spd_block *blk)
 		if (blk->spd_array[i] != NULL)
 			j |= blk->spd_array[i][SPD_DRAM_TYPE];
 
-	/* If spd used is DDR5, then its length is 1024 byte. */
-	if (j == SPD_DRAM_DDR5)
-		blk->len = CONFIG_DIMM_SPD_SIZE;
 	/* If spd used is DDR4, then its length is 512 byte. */
-	else if (j == SPD_DRAM_DDR4)
+	if (j == SPD_DRAM_DDR4)
 		blk->len = SPD_PAGE_LEN_DDR4;
 	else
 		blk->len = SPD_PAGE_LEN;
@@ -40,61 +37,6 @@ static void smbus_read_spd(u8 *spd, u8 addr)
 	}
 }
 
-static void switch_page(u8 spd_addr, u8 new_page)
-{
-	u32 offset;
-	/*
-	 *  By default,an SPD5 hub accepts 1 byte addressing pointing
-	 *  to the first 128 bytes of memory. MR11[2:0] selects the page
-	 *  pointer to address the entire 1024 bytes of non-volatile memory.
-	 */
-	offset = SPD5_MEMREG_REG(SPD5_MR11);
-	smbus_write_byte(spd_addr, offset, new_page);
-}
-
-/*
- * Read the SPD data over the SMBus, at the specified SPD address,
- * starting at the specified starting offset and read the given amount of data.
- */
-static void smbus_read_spd5(u8 *spd, u8 spd_addr, u16 size)
-{
-	u8 page = ~0;
-	u32 max_page_size = MAX_SPD_PAGE_SIZE_SPD5;
-
-	if (size > MAX_SPD_SIZE) {
-		printk(BIOS_ERR, "Maximum SPD size reached\n");
-		return;
-	}
-	for (int i = 0; i < size; i++) {
-		u8 next_page = (u8) (i / max_page_size);
-		if (next_page != page) {
-			switch_page(spd_addr, next_page);
-			page = next_page;
-		}
-		unsigned int byte_addr = SPD_HUB_MEMREG(i % max_page_size);
-		spd[i] = smbus_read_byte(spd_addr, byte_addr);
-	}
-}
-
-/* Read SPD5 MR0 and check if SPD Byte 0 matches the SPD5 HUB MR0 identifier.*/
-static int is_spd5_hub(u8 spd_addr)
-{
-	u8 spd_hub_byte;
-
-	spd_hub_byte = smbus_read_byte(spd_addr, SPD5_MEMREG_REG(SPD5_MR0));
-	return spd_hub_byte == SPD5_MR0_SPD5_HUB_DEV;
-}
-
-/*
- * Reset the SPD page back to page 0 on an SPD5 Hub device at the
- * input SPD SMbus address.
- */
-static void reset_page_spd5(u8 spd_addr)
-{
-	/* Set SPD5 MR11[2:0] = 0 (Page 0) */
-	smbus_write_byte(spd_addr, SPD5_MEMREG_REG(SPD5_MR11), 0);
-}
-
 /* return -1 if SMBus errors otherwise return 0 */
 static int get_spd(u8 *spd, u8 addr)
 {
@@ -110,21 +52,13 @@ static int get_spd(u8 *spd, u8 addr)
 		return -1;
 	}
 
-	if (is_spd5_hub(addr)) {
-		smbus_read_spd5(spd, addr, CONFIG_DIMM_SPD_SIZE);
-
-		/* Reset the page for the next loop iteration */
-		reset_page_spd5(addr);
-	} else {
-
 	if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) {
 		printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n");
 		smbus_read_spd(spd, addr);
 	}
 
 	/* Check if module is DDR4, DDR4 spd is 512 byte. */
-		if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 &&
-					CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) {
+	if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) {
 		/* Switch to page 1 */
 		smbus_write_byte(SPD_PAGE_1, 0, 0);
 
@@ -135,7 +69,6 @@ static int get_spd(u8 *spd, u8 addr)
 		/* Restore to page 0 */
 		smbus_write_byte(SPD_PAGE_0, 0, 0);
 	}
-	}
 	return 0;
 }
 

src/soc/intel/meteorlake/Kconfig

@@ -402,6 +402,18 @@ config BUILDING_WITH_DEBUG_FSP
 	help
 	  Set this option if debug build of FSP is used.
 
+config INTEL_GMA_BCLV_OFFSET
+	default 0xc8258
+
+config INTEL_GMA_BCLV_WIDTH
+	default 32
+
+config INTEL_GMA_BCLM_OFFSET
+	default 0xc8254
+
+config INTEL_GMA_BCLM_WIDTH
+	default 32
+
 config DROP_CPU_FEATURE_PROGRAM_IN_FSP
 	bool
 	default y if MP_SERVICES_PPI_V2_NOOP || CHROMEOS

src/soc/intel/meteorlake/Makefile.mk

@@ -37,6 +37,7 @@ ramstage-y += elog.c
 ramstage-y += espi.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
+ramstage-y += graphics.c
 ramstage-y += lockdown.c
 ramstage-y += p2sb.c
 ramstage-y += pcie_rp.c

src/soc/intel/meteorlake/chip.h

@@ -4,6 +4,7 @@
 #define _SOC_CHIP_H_
 
 #include <drivers/i2c/designware/dw_i2c.h>
+#include <drivers/intel/gma/gma.h>
 #include <device/pci_ids.h>
 #include <gpio.h>
 #include <intelblocks/cfg.h>
@@ -527,6 +528,9 @@ struct soc_intel_meteorlake_config {
 	 * as per `enum slew_rate` data type.
 	 */
 	uint8_t slow_slew_rate_config[NUM_VR_DOMAINS];
+
+	/* i915 struct for GMA backlight control */
+	struct i915_gpu_controller_info gfx;
 };
 
 typedef struct soc_intel_meteorlake_config config_t;

src/soc/intel/meteorlake/graphics.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <intelblocks/graphics.h>
+#include <soc/ramstage.h>
+
+const struct i915_gpu_controller_info *
+intel_igd_get_controller_info(const struct device *const dev)
+{
+	const struct soc_intel_meteorlake_config *const chip = dev->chip_info;
+	return &chip->gfx;
+}