Documentation: Finalize 24.05 release notes

These are the final release notes for the 24.05 release before the tree
is marked with a tag, completing the release. We will update the notes
with final numbers and anything else after the release is tagged.

The 24.05 release will be announced a week later, barring any issues
that require an updated release tag.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I00be0127351f8641116b4bc523c266628b084e69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82407
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>

Documentation/releases/coreboot-24.05-relnotes.md

@@ -1,37 +1,76 @@
-Upcoming release - coreboot 24.05
+coreboot 24.05 release
 ========================================================================
 
-The 24.05 release is scheduled for Mid May, 2024
+The coreboot project is pleased to announce the release of coreboot version
+24.05. This update represents three months of hard work and commitment from our
+community. With over 20 new members and contributions from more than a hundred
+fifty other people in coding, reviewing patches, and other areas, this release
+showcases the strength of our collaborative efforts.
 
+With this release, coreboot has expanded its support, adding 25 new platforms or
+variants and 2 new processors, further demonstrating our dedication to offering
+flexible and adaptable firmware solutions. From laptops and servers to embedded
+devices, coreboot 24.05 is designed to enhance a variety of hardware platforms
+with its strong features.
 
-Update this document with changes that should be in the release notes.
+We are grateful to all the contributors who have made this release possible.
+Your expertise and collaborative efforts continue to propel the coreboot project
+forward. We value the participation of everyone in the community, from long-time
+developers to those new to the project, and encourage you to explore the new
+opportunities that coreboot 24.05 offers.
 
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-* Note that all changes before the release are done are marked upcoming.
-  A final version of the notes are done after the release.
+Our next release will be 24.08, scheduled for mid-August.
 
 
 
 Significant or interesting changes
 ----------------------------------
 
-* Add changes that need a full description here
+### Mark 64-bit support as stable
 
-* This section should have full descriptions and can or should have
-  a link to the referenced commits.
+A significant amount of work has gone into fully supporting 64-bit coreboot
+builds. There are still additional pieces that are happening, but with SMM
+holding page tables itself, we can consider SMM support stable and safe enough
+for general use.
+
+
+### security/tpm: support compiling in multiple TPM drivers
+
+Previously, boards could only be built with code supporting TPM 1.x or TPM 2.x
+specifications. This has been updated with code allowing both to be built in
+simultaneously, allowing the system to query the TPM. For systems with
+soldered-down TPMs or firmware TPM solutions, it’s still possible to specify a
+single TPM version so that the code for the other version isn’t included.
+
+
+### arch/arm64: Add EL1/EL2/EL3 support for arm64
+
+Previously, arch/arm64 required coreboot to run on EL3 due to EL3 register
+access. This might be an issue when, for example, one boots into TF-A first and
+drops into EL2 for coreboot afterwards.
+
+This patch aims at making arch/arm64 more versatile by removing the current EL3
+constraint and allowing arm64 coreboot to run on EL1, EL2 and EL3.
+
+The strategy is to add a Kconfig option (ARM64_CURRENT_EL) which allows us to
+specify coreboot's EL upon entry. Based on that, we access the appropriate ELx
+registers. So, for example, when running coreboot on EL1, we would not access
+vbar_el3 or vbar_el2 but instead vbar_el1. This way, we don't generate faults
+when accessing higher-EL registers.
 
 
 
 Additional coreboot changes
 ---------------------------
 
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Changes that only need a line or two of description go here.
+* util/smmstoretool: support processing ROMs
+* cpu/x86: Link page tables in stage if possible
+* lib/lzmadecode: Allow for 8 byte reads on 64bit to speed up decompression
+* mb/lenovo/*: Set VR12 PSI to fix crash
+* Numerous fixes for clang support
+* Ongoing code cleanup
+* Docs: Replace Recommonmark with MyST Parser. For changes, see the commit
+  message in https://review.coreboot.org/73158
 
 
 
@@ -40,11 +79,29 @@ Changes to external resources
 
 ### Toolchain updates
 
+* util/kconfig: Uprev to Linux 6.8's kconfig
+* crossgcc: Upgrade CMake from 3.27.7 to version 3.28.3
+* util/crossgcc: Update LLVM from 16.0.6 to 17.0.6
+* crossgcc: Upgrade binutils from 2.41 to 2.42
+* util/crossgcc/buildgcc: Use Intel mirror for ACPICA
+
 
 ### Git submodule pointers
 
+- amd_blobs: Update from commit id 64cdd7c8ef to ae5fc7d277 (1 commits)
+- arm-trusted-firmware: Update from commit id 17bef2248d to 48f1bc9f52 (517
+  commits)
+- cmocka: Update from commit id 8931845c35 to 8be3737209 (32 commits)
+- fsp: Update from commit id 507ef01cce to cc6399e8c7 (14 commits)
+- intel-microcode: Update from commit id ece0d294a2 to 41af345005 (1 commit)
+- vboot: Update from commit id 3d37d2aafe to 09fcd2184f (27 commits)
 
-### External payloads
+
+#### External payloads
+
+* payloads/U-Boot: Upgrade from U-Boot v2023.07 to v2024.4
+* payloads/edk2: Add Kconfig options for LAPIC timer & UFS support
+* payloads/Kconfig: Add flat binary as payload option
 
 
 
@@ -52,42 +109,154 @@ Platform Updates
 ----------------
 
 ### Added mainboards:
-* To be filled in immediately before the release by the release team
+
+* AMD BirmanPlus for Glinda SoC
+* AMD BirmanPlus for Phoenix SoC
+* ASROCK Z97 Extreme6
+* Dell OptiPlex 7020/9020 MT
+* Dell OptiPlex 7020/9020 SFF
+* Framework Azalea (Framework 13 AMD 7040)
+* Google Brox EC ISH
+* Google Bujia
+* Google Glassway
+* Google Greenbayupoc
+* Google Kyogre
+* Google Lotso
+* Google Nova
+* Google Pujjoga
+* Google Riven
+* Google Skitty
+* Google Squirtle
+* Google Sundance
+* Google Tivviks
+* Google Trulo
+* Google Veluza
+* Google Wugtrio
+* Google Yavista
+* HP Pro 3500 Series
+* Lenovo ThinkCentre M700 / M900 Tiny
+* Lenovo ThinkCentre M710s
+* Raptor Computing Systems Talos II
+* SiFive HiFive Unmatched
 
 
 ### Removed Mainboards
-* To be filled in immediately before the release by the release team
+
+* Intel Alderlake-M RVP
+* Intel Alderlake-M RVP with Chrome EC
 
 
 ### Updated SoCs
-* To be filled in immediately before the release by the release team
+
+* Added src/soc/ibm/power9
+* Added src/soc/sifive/fu740
 
 
 
-Plans to move platform support to a branch
-------------------------------------------
-* To be filled in immediately before the release by the release team
-
-
-
-Statistics from the 4.22 to the 24.02 release
+Statistics from the 24.02 to the 24.05 release
 --------------------------------------------
-* To be filled in immediately before the release by the release team
 
+* Total Commits: 722
+* Average Commits per day: 8.55
+* Total lines added: 302523
+* Average lines added per commit: 419.01
+* Number of patches adding more than 100 lines: 57
+* Average lines added per small commit: 37.80
+* Total lines removed: 16089
+* Average lines removed per commit: 22.28
+* Total difference between added and removed: 286434
+* Total authors: 131
+* New authors: 23
 
 
 Significant Known and Open Issues
 ---------------------------------
 
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-* To be filled in immediately before the release by the release team
+## coreboot-wide or architecture-wide issues
 
+```{eval-rst}
++-----+-----------------------------------------------------------------+
+| #   | Subject                                                         |
++=====+=================================================================+
+| 522 | 'region_overlap()' issues due to an integer overflow.           |
++-----+-----------------------------------------------------------------+
+| 519 | make gconfig - could not find glade file                        |
++-----+-----------------------------------------------------------------+
+| 518 | make xconfig - g++: fatal error: no input files                 |
++-----+-----------------------------------------------------------------+
+```
+
+
+## Payload-specific issues
+
+```{eval-rst}
++-----+-----------------------------------------------------------------+
+| #   | Subject                                                         |
++=====+=================================================================+
+| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled       |
++-----+-----------------------------------------------------------------+
+| 496 | Missing malloc check in libpayload                              |
++-----+-----------------------------------------------------------------+
+| 484 | No USB keyboard support with secondary payloads                 |
++-----+-----------------------------------------------------------------+
+| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
++-----+-----------------------------------------------------------------+
+```
+
+
+## Platform-specific issues
+
+```{eval-rst}
++-----+-----------------------------------------------------------------+
+| #   | Subject                                                         |
++=====+=================================================================+
+| 524 | X2APIC Options cause Linux to crash on emulation/qemu-i440fx    |
++-----+-----------------------------------------------------------------+
+| 517 | lenovo x230 boot stuck with connected external monitor          |
++-----+-----------------------------------------------------------------+
+| 509 | SD Card hotplug not working on Apollo Lake                      |
++-----+-----------------------------------------------------------------+
+| 507 | Windows GPU driver fails on Google guybrush & skyrim boards     |
++-----+-----------------------------------------------------------------+
+| 506 | APL/GML don't boot OS when CPU microcode included "from tree"   |
++-----+-----------------------------------------------------------------+
+| 505 | Harcuvar CRB - 15 of 16 cores present in the operating system   |
++-----+-----------------------------------------------------------------+
+| 499 | T440p - EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled    |
++-----+-----------------------------------------------------------------+
+| 495 | Stoney Chromebooks not booting PSPSecureOS                      |
++-----+-----------------------------------------------------------------+
+| 478 | X200 booting Linux takes a long time with TSC                   |
++-----+-----------------------------------------------------------------+
+| 474 | X200s crashes after graphic init with 8GB RAM                   |
++-----+-----------------------------------------------------------------+
+| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb  |
++-----+-----------------------------------------------------------------+
+| 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit   |
++-----+-----------------------------------------------------------------+
+| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
++-----+-----------------------------------------------------------------+
+| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
++-----+-----------------------------------------------------------------+
+| 446 | Optiplex 9010 No Post                                           |
++-----+-----------------------------------------------------------------+
+| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
++-----+-----------------------------------------------------------------+
+| 427 | x200: Two battery charging issues                               |
++-----+-----------------------------------------------------------------+
+| 412 | x230 reboots on suspend                                         |
++-----+-----------------------------------------------------------------+
+| 393 | T500 restarts rather than waking up from suspend                |
++-----+-----------------------------------------------------------------+
+| 350 | I225 PCIe device not detected on Harcuvar                       |
++-----+-----------------------------------------------------------------+
+```
 
 
 coreboot Links and Contact Information
 --------------------------------------
 
-* Main Web site: https://www.coreboot.org
+* Main Website: https://www.coreboot.org
 * Downloads: https://coreboot.org/downloads.html
 * Source control: https://review.coreboot.org
 * Documentation: https://doc.coreboot.org

Documentation/security/vboot/list_vboot.md

@@ -4,6 +4,8 @@
 - Birman for Phoenix SoC using FSP
 - Birman for Phoenix SoC using openSIL
 - Birman for Glinda SoC
+- BirmanPlus for Phoenix SoC
+- BirmanPlus for Glinda SoC
 - Chausie
 - Majolica
 - Mayan for Phoenix SoC
@@ -35,6 +37,9 @@
 - Tricky (Dell Chromebox 3010)
 - Zako (HP Chromebox G1)
 - Brox
+- Brox EC ISH
+- Lotso
+- Greenbayupoc
 - Agah
 - Anahera
 - Anahera4ES
@@ -53,6 +58,7 @@
 - Gimble
 - Gimble4ES
 - Gladios
+- Glassway
 - Gothrax
 - Hades
 - Kano
@@ -74,11 +80,14 @@
 - Quandiso
 - Redrix
 - Redrix4ES
+- Riven
 - Skolas
 - Skolas4ES
 - Taeko
 - Taeko4ES
 - Taniks
+- Tivviks
+- Trulo
 - Uldren
 - Vell
 - Volmar
@@ -87,19 +96,29 @@
 - Yavilla
 - Zydron
 - Xol
+- Nova
+- Bujia
+- Yavista
+- Sundance
+- Pujjoga
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
 - Dojo
 - Tomato
 - Kingler
+- Kyogre
+- Ponyta
+- Squirtle
 - Steelix
 - Voltorb
-- Ponyta
-- Krabby
-- Tentacruel
-- Magikarp
 - Chinchou
+- Krabby
+- Magikarp
+- Skitty
+- Tentacruel
+- Veluza
 - Starmie
+- Wugtrio
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))
@@ -305,8 +324,6 @@
 - Alderlake-P RVP
 - Alderlake-P RVP with Chrome EC
 - Alderlake-P RVP with Microchip EC
-- Alderlake-M RVP
-- Alderlake-M RVP with Chrome EC
 - Alderlake-N RVP
 - Alderlake-N RVP with Chrome EC
 - Raptorlake silicon with Alderlake-P RVP
@@ -365,6 +382,7 @@
 - ThinkPad X230
 - ThinkPad X230t
 - ThinkPad X230s
+- ThinkPad X230 eDP Mod (2K/FHD)
 - ThinkPad X60 / X60s / X60t
 
 ## MSI

configs/config.protectli_cml_vp46xx

@@ -1,5 +1,5 @@
 CONFIG_VENDOR_PROTECTLI=y
-CONFIG_BOARD_PROTECTLI_VP4670=y
+CONFIG_BOARD_PROTECTLI_VP46XX=y
 CONFIG_TPM_MEASURED_BOOT=y
 CONFIG_SMMSTORE_SIZE=0x40000
 CONFIG_TPM2=y

configs/config.protectli_vp4630_vp4650

@@ -1,13 +0,0 @@
-CONFIG_VENDOR_PROTECTLI=y
-CONFIG_BOARD_PROTECTLI_VP4630_VP4650=y
-CONFIG_TPM_MEASURED_BOOT=y
-CONFIG_SMMSTORE_SIZE=0x40000
-CONFIG_TPM2=y
-CONFIG_POST_IO_PORT=0x80
-CONFIG_PAYLOAD_EDK2=y
-CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
-CONFIG_EDK2_BOOT_TIMEOUT=6
-CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
-# CONFIG_EDK2_FULL_SCREEN_SETUP is not set
-CONFIG_EDK2_SD_MMC_TIMEOUT=10
-CONFIG_EDK2_SERIAL_SUPPORT=y

payloads/external/LinuxBoot/Makefile

@@ -33,7 +33,7 @@ endif
 
 ifeq ($(CONFIG_LINUXBOOT_KERNEL_BZIMAGE),y)
 
-build/bzImage: $(kernel_dir)/arch/x86/boot/bzImage | build
+build/bzImage: $(kernel_dir)/arch/x86/boot/bzImage build/initramfs | build
 	cp $< $@
 
 else ifeq ($(CONFIG_LINUXBOOT_KERNEL_UIMAGE),y)

src/arch/x86/Makefile.mk

@@ -253,7 +253,6 @@ ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c
 ramstage-y += boot.c
 ramstage-y += post.c
 ramstage-y += c_start.S
-ramstage-y += c_exit.S
 ramstage-y += cpu.c
 ramstage-y += cpu_common.c
 ramstage-$(CONFIG_DEBUG_HW_BREAKPOINTS) += breakpoint.c

src/arch/x86/boot.c

@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/boot/boot.h>
 #include <arch/cpu.h>
 #include <commonlib/helpers.h>
 #include <console/console.h>
+#include <mode_switch.h>
 #include <program_loading.h>
 #include <symbols.h>
 #include <assert.h>
@@ -26,7 +26,7 @@ void arch_prog_run(struct prog *prog)
 	const uint32_t entry = pointer_to_uint32_safe(prog_entry(prog));
 
 	/* On x86 coreboot payloads expect to be called in protected mode */
-	protected_mode_jump(entry, arg);
+	protected_mode_call_1arg((void *)(uintptr_t)entry, arg);
 #else
 #if ENV_X86_64
 	void (*doit)(void *arg);

src/arch/x86/c_exit.S

@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/ram_segs.h>
-#include <cpu/x86/cr.h>
-
-#if ENV_X86_64
-
-	/*
-	 * Functions to handle mode switches from long mode to protected
-	 * mode.
-	 */
-.text
-.code64
-	.section ".text.protected_mode_jump", "ax", @progbits
-	.globl protected_mode_jump
-protected_mode_jump:
-
-	push %rbp
-	mov %rsp, %rbp
-
-	/* Arguments to stack */
-	push	%rdi
-	push	%rsi
-
-	#include <cpu/x86/64bit/exit32.inc>
-
-	movl	-8(%ebp), %eax	/* Function to call */
-	movl	-16(%ebp), %ebx	/* Argument 0 */
-
-	/* Align the stack */
-	andl	$0xFFFFFFF0, %esp
-	subl	$12, %esp
-	pushl	%ebx	/* Argument 0 */
-
-	jmp	*%eax
-#endif

src/arch/x86/include/arch/boot/boot.h

@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef X86_BOOT_H
-#define X86_BOOT_H
-
-#include <types.h>
-/*
- * Jump to function in protected mode.
- * @arg func_ptr           Function to jump to in protected mode
- * @arg                    Argument to pass to called function
- *
- * @noreturn
- */
-void protected_mode_jump(uint32_t func_ptr, uint32_t argument);
-
-#endif /* X86_BOOT_H */

src/cpu/x86/pae/pgtbl.c

@@ -213,69 +213,6 @@ int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl,
 	return 0;
 }
 
-#if ENV_RAMSTAGE
-void *map_2M_page(unsigned long page)
-{
-	struct pde {
-		uint32_t addr_lo;
-		uint32_t addr_hi;
-	} __packed;
-	struct pg_table {
-		struct pde pd[2048];
-		struct pde pdp[512];
-	} __packed;
-
-	static struct pg_table pgtbl[CONFIG_MAX_CPUS]
-		__attribute__((aligned(4096)));
-	static unsigned long mapped_window[CONFIG_MAX_CPUS];
-	int index;
-	unsigned long window;
-	void *result;
-	int i;
-	index = cpu_index();
-	if (index < 0)
-		return MAPPING_ERROR;
-	window = page >> 10;
-	if (window != mapped_window[index]) {
-		paging_disable_pae();
-		if (window > 1) {
-			struct pde *pd, *pdp;
-			/* Point the page directory pointers at the page
-			 * directories
-			 */
-			memset(&pgtbl[index].pdp, 0, sizeof(pgtbl[index].pdp));
-			pd = pgtbl[index].pd;
-			pdp = pgtbl[index].pdp;
-			pdp[0].addr_lo = ((uintptr_t)&pd[512*0])|1;
-			pdp[1].addr_lo = ((uintptr_t)&pd[512*1])|1;
-			pdp[2].addr_lo = ((uintptr_t)&pd[512*2])|1;
-			pdp[3].addr_lo = ((uintptr_t)&pd[512*3])|1;
-			/* The first half of the page table is identity mapped
-			 */
-			for (i = 0; i < 1024; i++) {
-				pd[i].addr_lo = ((i & 0x3ff) << 21) | 0xE3;
-				pd[i].addr_hi = 0;
-			}
-			/* The second half of the page table holds the mapped
-			 * page
-			 */
-			for (i = 1024; i < 2048; i++) {
-				pd[i].addr_lo = ((window & 1) << 31)
-					| ((i & 0x3ff) << 21) | 0xE3;
-				pd[i].addr_hi = (window >> 1);
-			}
-			paging_enable_pae_cr3((uintptr_t)pdp);
-		}
-		mapped_window[index] = window;
-	}
-	if (window == 0)
-		result = (void *)(page << 21);
-	else
-		result = (void *)(0x80000000 | ((page & 0x3ff) << 21));
-	return result;
-}
-#endif
-
 void paging_set_nxe(int enable)
 {
 	msr_t msr = rdmsr(IA32_EFER);

src/drivers/intel/fsp2_0/include/fsp/soc_binding.h

@@ -7,6 +7,8 @@
 
 #pragma pack(push)
 
+#include <efi/efi_datatype.h>
+
 /**
  * These includes are required to include headers that are missing in
  * the FSP headers. Import order matter for the correct PiHob definition
@@ -24,7 +26,6 @@
  * This file is a implementation specific header. i.e. different
  * FSP implementations for different chipsets.
  */
-#include <Base.h>
 #include <FspmUpd.h>
 #include <FspsUpd.h>
 #if CONFIG(MRC_CACHE_USING_MRC_VERSION)

src/drivers/intel/ish/ish.c

@@ -79,6 +79,7 @@ static const struct device_operations pci_ish_device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_PTL_ISHB,
 	PCI_DID_INTEL_LNL_ISHB,
 	PCI_DID_INTEL_MTL_ISHB,
 	PCI_DID_INTEL_CNL_ISHB,

src/drivers/mipi/panel-IVO_T109NW41.c

@@ -21,14 +21,13 @@ struct panel_serializable_data IVO_T109NW41 = {
 	.init = {
 		PANEL_DELAY(60),
 		PANEL_DCS(0xB9, 0x83, 0x10, 0x21, 0x55, 0x00),
-		PANEL_DCS(0xB1, 0x2C, 0xED, 0xED, 0x27, 0xE7, 0x42, 0xF5, 0x39,
+		PANEL_DCS(0xB1, 0x2C, 0xED, 0xED, 0x0F, 0xCF, 0x42, 0xF5, 0x39,
 			0x36, 0x36, 0x36, 0x36, 0x32, 0x8B, 0x11, 0x65, 0x00, 0x88,
 			0xFA, 0xFF, 0xFF, 0x8F, 0xFF, 0x08, 0xD6, 0x33),
 		PANEL_DCS(0xB2, 0x00, 0x47, 0xB0, 0x80, 0x00, 0x12, 0x71, 0x3C,
 			0xA3, 0x22, 0x20, 0x00, 0x00, 0x88, 0x01),
 		PANEL_DCS(0xB4, 0x35, 0x35, 0x43, 0x43, 0x35, 0x35, 0x30, 0x7A,
 			0x30, 0x7A, 0x01, 0x9D),
-		PANEL_DCS(0xB6, 0x34, 0x34, 0x03),
 		PANEL_DCS(0xE9, 0xCD),
 		PANEL_DCS(0xBA, 0x84),
 		PANEL_DCS(0xE9, 0x3F),
@@ -40,6 +39,9 @@ struct panel_serializable_data IVO_T109NW41 = {
 		PANEL_DCS(0xE9, 0xCC),
 		PANEL_DCS(0xC7, 0x80),
 		PANEL_DCS(0xE9, 0x3F),
+		PANEL_DCS(0xE9, 0xD3),
+		PANEL_DCS(0xC7, 0x22),
+		PANEL_DCS(0xE9, 0x3F),
 		PANEL_DCS(0xE9, 0xC6),
 		PANEL_DCS(0xC8, 0x97),
 		PANEL_DCS(0xE9, 0x3F),
@@ -56,19 +58,25 @@ struct panel_serializable_data IVO_T109NW41 = {
 			0x00, 0x02, 0x00, 0x02, 0x00, 0x00),
 		PANEL_DCS(0xD5, 0x25, 0x24, 0x25, 0x24, 0x18, 0x18, 0x18, 0x18,
 			0x07, 0x06, 0x07, 0x06, 0x05, 0x04, 0x05, 0x04, 0x03, 0x02,
-			0x03, 0x02, 0x01, 0x00, 0x01, 0x00, 0xA8, 0xA8, 0xA8, 0xA8,
-			0x29, 0x29, 0x29, 0x29, 0x21, 0x20, 0x21, 0x20, 0x18, 0x18,
+			0x03, 0x02, 0x01, 0x00, 0x01, 0x00, 0x1E, 0x1E, 0x1E, 0x1E,
+			0x1F, 0x1F, 0x1F, 0x1F, 0x21, 0x20, 0x21, 0x20, 0x18, 0x18,
 			0x18, 0x18, 0x18, 0x18, 0x18, 0x18),
 		PANEL_DCS(0xD8, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0xAA, 0xAA,
 			0xAA, 0xAA, 0xAA, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+		PANEL_DCS(0xE0, 0x04, 0X04, 0X06, 0X0A, 0X0A, 0X05, 0X12, 0X14,
+			0X17, 0X13, 0X2C, 0X33, 0X39, 0X4B, 0X4C, 0X56, 0X61, 0X78,
+			0X7A, 0X41, 0X50, 0X68, 0X73, 0X04, 0X04, 0X06, 0X0A, 0X0A,
+			0X05, 0X12, 0X14, 0X17, 0X13, 0X2C, 0X33, 0X39, 0X4B, 0X4C,
+			0X56, 0X61, 0X78, 0X7A, 0X41, 0X50, 0X68, 0X73),
 		PANEL_DCS(0xE7, 0x07, 0x10, 0x10, 0x1A, 0x26, 0x9E, 0x00, 0x4F,
 			0xA0, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x0A, 0x02,
 			0x02, 0x00, 0x33, 0x02, 0x04, 0x18, 0x01),
 		PANEL_DCS(0xBD, 0x01),
 		PANEL_DCS(0xB1, 0x01, 0x7F, 0x11, 0xFD),
 		PANEL_DCS(0xCB, 0x86),
+		PANEL_DCS(0xD3, 0x00, 0X00, 0X04, 0X00, 0X00),
 		PANEL_DCS(0xD8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 			0x00, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0,
 			0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0x00, 0x00, 0x00, 0x00,
@@ -94,6 +102,7 @@ struct panel_serializable_data IVO_T109NW41 = {
 		PANEL_DCS(0xE9, 0x3F),
 		PANEL_DCS(0xE1, 0x00),
 		PANEL_DCS(0xBD, 0x00),
+		PANEL_DCS(0xD2, 0xFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF),
 		PANEL_DCS(0xE9, 0xC4),
 		PANEL_DCS(0xBA, 0x96),
 		PANEL_DCS(0xE9, 0x3F),

src/include/cpu/intel/cpu_ids.h

@@ -81,5 +81,7 @@
 #define CPUID_RAPTORLAKE_J0		0xb06a2
 #define CPUID_RAPTORLAKE_Q0		0xb06a3
 #define CPUID_LUNARLAKE_A0_1		0xb06d0
+#define CPUID_LUNARLAKE_A0_2		0xb06d1
+#define CPUID_PANTHERLAKE_A0		0xc06c0
 
 #endif /* CPU_INTEL_CPU_IDS_H */

src/include/cpu/x86/pae.h

@@ -40,9 +40,6 @@ int paging_enable_for_car(const char *pdpt_name, const char *pt_name);
  * PAT defines above. 0 is returned on success, < 0 on failure. */
 int paging_identity_map_addr(uintptr_t base, size_t size, int pat);
 
-#define MAPPING_ERROR ((void *)0xffffffffUL)
-void *map_2M_page(unsigned long page);
-
 /* To be used with memset_pae */
 #define MEMSET_PAE_VMEM_ALIGN (2 * MiB)
 #define MEMSET_PAE_VMEM_SIZE (2 * MiB)

src/include/device/pci_ids.h

@@ -2185,6 +2185,7 @@
 #define PCI_DID_INTEL_ADL_N_ISHB	0x54fc
 #define PCI_DID_INTEL_ADL_P_ISHB	0x51fc
 #define PCI_DID_INTEL_LNL_ISHB		0xa845
+#define PCI_DID_INTEL_PTL_ISHB		0xe445
 
 /* Intel 82371FB (PIIX) */
 #define PCI_DID_INTEL_82371FB_ISA		0x122e
@@ -3166,6 +3167,14 @@
 #define PCI_DID_INTEL_LNL_ESPI_5			0xa805
 #define PCI_DID_INTEL_LNL_ESPI_6			0xa806
 #define PCI_DID_INTEL_LNL_ESPI_7			0xa807
+#define PCI_DID_INTEL_PTL_ESPI_0			0xe400
+#define PCI_DID_INTEL_PTL_ESPI_1			0xe401
+#define PCI_DID_INTEL_PTL_ESPI_2			0xe402
+#define PCI_DID_INTEL_PTL_ESPI_3			0xe403
+#define PCI_DID_INTEL_PTL_ESPI_4			0xe404
+#define PCI_DID_INTEL_PTL_ESPI_5			0xe405
+#define PCI_DID_INTEL_PTL_ESPI_6			0xe406
+#define PCI_DID_INTEL_PTL_ESPI_7			0xe407
 
 /* Intel PCIE device ids  */
 #define PCI_DID_INTEL_LPT_H_PCIE_RP1			0x8c10
@@ -3528,6 +3537,14 @@
 #define PCI_DID_INTEL_LNL_PCIE_RP6			0xa83d
 #define PCI_DID_INTEL_LNL_PCIE_RP7			0xa83e
 #define PCI_DID_INTEL_LNL_PCIE_RP8			0xa83f
+#define PCI_DID_INTEL_PTL_PCIE_RP1			0xe438
+#define PCI_DID_INTEL_PTL_PCIE_RP2			0xe439
+#define PCI_DID_INTEL_PTL_PCIE_RP3			0xe43a
+#define PCI_DID_INTEL_PTL_PCIE_RP4			0xe43b
+#define PCI_DID_INTEL_PTL_PCIE_RP5			0xe43c
+#define PCI_DID_INTEL_PTL_PCIE_RP6			0xe43d
+#define PCI_DID_INTEL_PTL_PCIE_RP7			0xe43e
+#define PCI_DID_INTEL_PTL_PCIE_RP8			0xe43f
 
 #define PCI_DID_INTEL_RPP_S_PCIE_RP1			0x7a38
 #define PCI_DID_INTEL_RPP_S_PCIE_RP2			0x7a39
@@ -3672,6 +3689,7 @@
 #define PCI_DID_INTEL_RPP_P_PMC			0x51a1
 #define PCI_DID_INTEL_RPP_S_PMC			0x7a21
 #define PCI_DID_INTEL_LNL_PMC			0xa821
+#define PCI_DID_INTEL_PTL_PMC			0xe421
 
 /* Intel I2C device Ids */
 #define PCI_DID_INTEL_LPT_LP_I2C0		0x9c61
@@ -3803,6 +3821,13 @@
 #define PCI_DID_INTEL_LNL_I2C4			0xa850
 #define PCI_DID_INTEL_LNL_I2C5			0xa851
 
+#define PCI_DID_INTEL_PTL_I2C0			0xe478
+#define PCI_DID_INTEL_PTL_I2C1			0xe479
+#define PCI_DID_INTEL_PTL_I2C2			0xe47a
+#define PCI_DID_INTEL_PTL_I2C3			0xe47b
+#define PCI_DID_INTEL_PTL_I2C4			0xe450
+#define PCI_DID_INTEL_PTL_I2C5			0xe451
+
 /* Intel UART device Ids */
 #define PCI_DID_INTEL_LPT_LP_UART0		0x9c63
 #define PCI_DID_INTEL_LPT_LP_UART1		0x9c64
@@ -3886,6 +3911,10 @@
 #define PCI_DID_INTEL_LNL_UART1			0xa826
 #define PCI_DID_INTEL_LNL_UART2			0xa852
 
+#define PCI_DID_INTEL_PTL_UART0			0xe425
+#define PCI_DID_INTEL_PTL_UART1			0xe426
+#define PCI_DID_INTEL_PTL_UART2			0xe452
+
 /* Intel SPI device Ids */
 #define PCI_DID_INTEL_LPT_LP_GSPI0		0x9c65
 #define PCI_DID_INTEL_LPT_LP_GSPI1		0x9c66
@@ -3985,6 +4014,11 @@
 #define PCI_DID_INTEL_LNL_GSPI1			0xa830
 #define PCI_DID_INTEL_LNL_GSPI2			0xa846
 
+#define PCI_DID_INTEL_PTL_HWSEQ_SPI		0xe423
+#define PCI_DID_INTEL_PTL_SPI0			0xe427
+#define PCI_DID_INTEL_PTL_SPI1			0xe430
+#define PCI_DID_INTEL_PTL_SPI2			0xe446
+
 /* Intel IGD device Ids */
 #define PCI_DID_INTEL_SKL_GT1F_DT2			0x1902
 #define PCI_DID_INTEL_SKL_GT1_SULTM			0x1906
@@ -4150,6 +4184,7 @@
 #define PCI_DID_INTEL_LNL_M_GT2				0x64a0
 #define PCI_DID_INTEL_TWL_GT1_1				0x46D3
 #define PCI_DID_INTEL_TWL_GT1_2				0x46D4
+#define PCI_DID_INTEL_PTL_GT2				0x64a0
 
 /* Intel Northbridge Ids */
 #define PCI_DID_INTEL_APL_NB			0x5af0
@@ -4292,6 +4327,8 @@
 #define PCI_DID_INTEL_RPL_P_ID_7		0xa70a
 #define PCI_DID_INTEL_RPL_P_ID_8		0xa716
 #define PCI_DID_INTEL_LNL_M_ID			0x6400
+#define PCI_DID_INTEL_LNL_M_ID_1		0x6410
+#define PCI_DID_INTEL_PTL_ID			0xb001
 
 /* Intel SMBUS device Ids */
 #define PCI_DID_INTEL_LPT_H_SMBUS			0x8c22
@@ -4321,6 +4358,7 @@
 #define PCI_DID_INTEL_RPP_P_SMBUS			0x51a3
 #define PCI_DID_INTEL_RPP_S_SMBUS			0x7a23
 #define PCI_DID_INTEL_LNL_SMBUS				0xa822
+#define PCI_DID_INTEL_PTL_SMBUS				0xe422
 
 /* Intel EHCI device IDs */
 #define PCI_DID_INTEL_LPT_H_EHCI_1		0x8c26
@@ -4363,6 +4401,8 @@
 #define PCI_DID_INTEL_RPP_S_XHCI		0x7a60
 #define PCI_DID_INTEL_LNL_XHCI			0xa87d
 #define PCI_DID_INTEL_LNL_TCSS_XHCI		0xa831
+#define PCI_DID_INTEL_PTL_XHCI                  0xe47d
+#define PCI_DID_INTEL_PTL_TCSS_XHCI             0xe431
 
 /* Intel P2SB device Ids */
 #define PCI_DID_INTEL_APL_P2SB			0x5a92
@@ -4391,6 +4431,8 @@
 #define PCI_DID_INTEL_RPP_S_P2SB		0x7a20
 #define PCI_DID_INTEL_LNL_P2SB			0xa820
 #define PCI_DID_INTEL_LNL_P2SB2			0xa84c
+#define PCI_DID_INTEL_PTL_P2SB			0xe420
+#define PCI_DID_INTEL_PTL_P2SB2			0xe44c
 
 /* Intel SRAM device Ids */
 #define PCI_DID_INTEL_APL_SRAM			0x5aec
@@ -4406,6 +4448,7 @@
 #define PCI_DID_INTEL_MTL_IOE_M_SRAM		0x7ebf
 #define PCI_DID_INTEL_MTL_IOE_P_SRAM		0x7ecf
 #define PCI_DID_INTEL_LNL_SRAM			0xa87f
+#define PCI_DID_INTEL_PTL_SRAM			0xe47f
 
 /* Intel AUDIO device Ids */
 #define PCI_DID_INTEL_LPT_H_AUDIO		0x8c20
@@ -4472,6 +4515,15 @@
 #define PCI_DID_INTEL_LNL_AUDIO_7		0xa82e
 #define PCI_DID_INTEL_LNL_AUDIO_8		0xa82f
 
+#define PCI_DID_INTEL_PTL_AUDIO_1		0xe428
+#define PCI_DID_INTEL_PTL_AUDIO_2		0xe429
+#define PCI_DID_INTEL_PTL_AUDIO_3		0xe42a
+#define PCI_DID_INTEL_PTL_AUDIO_4		0xe42b
+#define PCI_DID_INTEL_PTL_AUDIO_5		0xe42c
+#define PCI_DID_INTEL_PTL_AUDIO_6		0xe42d
+#define PCI_DID_INTEL_PTL_AUDIO_7		0xe42e
+#define PCI_DID_INTEL_PTL_AUDIO_8		0xe42f
+
 /* Intel HECI/ME device Ids */
 #define PCI_DID_INTEL_LPT_H_MEI			0x8c3a
 #define PCI_DID_INTEL_LPT_H_MEI_9		0x8cba
@@ -4517,6 +4569,10 @@
 #define PCI_DID_INTEL_RPP_S_CSE3		0x7a6d
 #define PCI_DID_INTEL_MTL_CSE0			0x7e70
 #define PCI_DID_INTEL_LNL_CSE0			0xa870
+#define PCI_DID_INTEL_PTL_CSE0			0xe470
+#define PCI_DID_INTEL_PTL_CSE1			0xe471
+#define PCI_DID_INTEL_PTL_CSE2			0xe474
+#define PCI_DID_INTEL_PTL_CSE3			0xe475
 
 /* Intel XDCI device Ids */
 #define PCI_DID_INTEL_APL_XDCI			0x5aaa
@@ -4540,6 +4596,7 @@
 #define PCI_DID_INTEL_MTL_XDCI			0x7e7e
 #define PCI_DID_INTEL_MTL_M_TCSS_XDCI		0x7eb1
 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI		0x7ec1
+#define PCI_DID_INTEL_PTL_TCSS_XDCI		0xe432
 
 /* Intel SD device Ids */
 #define PCI_DID_INTEL_LPT_LP_SD			0x9c35
@@ -4561,6 +4618,7 @@
 
 /* Intel UFS device Ids */
 #define PCI_DID_INTEL_LNL_UFS			0xa847
+#define PCI_DID_INTEL_PTL_UFS			0xe447
 
 /* Intel Thunderbolt device Ids */
 #define PCI_DID_INTEL_TGL_TBT_RP0		0x9a23
@@ -4598,8 +4656,11 @@
 #define PCI_DID_INTEL_LNL_TBT_RP0		0xa84e
 #define PCI_DID_INTEL_LNL_TBT_RP1		0xa84f
 #define PCI_DID_INTEL_LNL_TBT_RP2		0xa860
+#define PCI_DID_INTEL_LNL_TBT_RP3		0xa837
 #define PCI_DID_INTEL_LNL_TBT_DMA0		0xa833
 #define PCI_DID_INTEL_LNL_TBT_DMA1		0xa834
+#define PCI_DID_INTEL_PTL_TBT_DMA0		0xe433
+#define PCI_DID_INTEL_PTL_TBT_DMA1		0xe434
 
 /* Intel WIFI Ids */
 #define PCI_DID_1000_SERIES_WIFI		0x0084
@@ -4632,6 +4693,7 @@
 #define PCI_DID_TP_6SERIES_WIFI		0x2725
 #define PCI_DID_MP_7SERIES_WIFI		0x272b
 
+/* Intel IPU device IDs */
 #define PCI_DID_INTEL_TGL_IPU			0x9a19
 #define PCI_DID_INTEL_TGL_H_IPU			0x9a39
 #define PCI_DID_INTEL_JSL_IPU			0x4e19
@@ -4640,6 +4702,7 @@
 #define PCI_DID_INTEL_MTL_IPU			0x7d19
 #define PCI_DID_INTEL_RPL_IPU			0xa75d
 #define PCI_DID_INTEL_LNL_IPU			0x645d
+#define PCI_DID_INTEL_PTL_IPU			0xb05d
 
 /* Intel Dynamic Tuning Technology Device */
 #define PCI_DID_INTEL_CML_DTT			0x1903
@@ -4699,12 +4762,20 @@
 #define PCI_DID_INTEL_LNL_CNVI_WIFI_2		0xa842
 #define PCI_DID_INTEL_LNL_CNVI_WIFI_3		0xa843
 #define PCI_DID_INTEL_LNL_CNVI_BT		0xa876
+#define PCI_DID_INTEL_PTL_CNVI_WIFI_0		0xe440
+#define PCI_DID_INTEL_PTL_CNVI_WIFI_1		0xe441
+#define PCI_DID_INTEL_PTL_CNVI_WIFI_2		0xe442
+#define PCI_DID_INTEL_PTL_CNVI_WIFI_3		0xe443
+#define PCI_DID_INTEL_PTL_CNVI_BT		0xe476
 
 /* Platform Security Engine */
 #define PCI_DID_INTEL_LNL_PSE0			0xa862
 #define PCI_DID_INTEL_LNL_PSE1			0xa863
 #define PCI_DID_INTEL_LNL_PSE2			0xa864
 
+/* In-memory Analytics Accelerator device IDs */
+#define PCI_DID_INTEL_LNL_IAA			0x642d
+
 /* Intel Crashlog */
 #define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM		0x9a0d
 #define PCI_DID_INTEL_ADL_CPU_CRASHLOG_SRAM		0x467d
@@ -4718,6 +4789,7 @@
 
 /* Intel Trace Hub */
 #define PCI_DID_INTEL_MTL_TRACEHUB			0x7e24
+#define PCI_DID_INTEL_RPL_TRACEHUB			0xa76f
 
 /* Intel Ethernet Controller device Ids */
 #define PCI_DID_INTEL_EHL_GBE_HOST		0x4B32

src/include/efi/efi_datatype.h

@@ -3,6 +3,22 @@
 /* Create EFI equivalent datatype in coreboot based on UEFI specification */
 #ifndef __EFI_DATATYPE_H__
 #define __EFI_DATATYPE_H__
+
+/*
+ * EDK2 EFIAPI macro definition relies on compiler flags such as __GNUC__ which
+ * is not working well when included by coreboot. While it has no side-effect on
+ * i386 because the C calling convention used by coreboot and FSP are the same,
+ * it breaks on x86_64 because FSP/UEFI uses the Microsoft x64 calling
+ * convention while coreboot uses the System V AMD64 ABI.
+ *
+ * Fortunately, EDK2 header allows to override EFIAPI.
+ */
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
+#define EFIAPI __attribute__((regparm(0)))
+#else
+#define EFIAPI __attribute__((__ms_abi__))
+#endif
+
 #include <Base.h>
 #include <Uefi/UefiBaseType.h>
 

src/mainboard/amd/onyx_poc/devicetree.cb

@@ -55,7 +55,7 @@ chip soc/amd/genoa_poc
 	device domain 0 on
 		device ref iommu_0 on end
 		device ref rcec_0 on end
-		chip vendorcode/amd/opensil/genoa_poc/mpio # P2
+		chip vendorcode/amd/opensil/chip/mpio # P2
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "48"
 			register "end_lane" = "63"
@@ -63,7 +63,7 @@ chip soc/amd/genoa_poc
 			register "aspm" = "L1"
 			device ref gpp_bridge_0_0_a on end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio # G2
+		chip vendorcode/amd/opensil/chip/mpio # G2
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "112"
 			register "end_lane" = "127"
@@ -72,7 +72,7 @@ chip soc/amd/genoa_poc
 			register "hotplug" = "ServerExpress"
 			device ref gpp_bridge_0_0_b on end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "128"
 			register "end_lane" = "131"
@@ -93,7 +93,7 @@ chip soc/amd/genoa_poc
 	device domain 1 on
 		device ref iommu_1 on end
 		device ref rcec_1 on end
-		chip vendorcode/amd/opensil/genoa_poc/mpio # P3
+		chip vendorcode/amd/opensil/chip/mpio # P3
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "16"
 			register "end_lane" = "31"
@@ -101,7 +101,7 @@ chip soc/amd/genoa_poc
 			register "aspm" = "L1"
 			device ref gpp_bridge_1_0_a on end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio # G3
+		chip vendorcode/amd/opensil/chip/mpio # G3
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "80"
 			register "end_lane" = "95"
@@ -114,7 +114,7 @@ chip soc/amd/genoa_poc
 	device domain 2 on
 		device ref iommu_2 on end
 		device ref rcec_2 on end
-		chip vendorcode/amd/opensil/genoa_poc/mpio # P1
+		chip vendorcode/amd/opensil/chip/mpio # P1
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "32"
 			register "end_lane" = "47"
@@ -123,7 +123,7 @@ chip soc/amd/genoa_poc
 			register "hotplug" = "ServerExpress"
 			device ref gpp_bridge_2_0_a on end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio # G1
+		chip vendorcode/amd/opensil/chip/mpio # G1
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "64"
 			register "end_lane" = "79"
@@ -137,7 +137,7 @@ chip soc/amd/genoa_poc
 	device domain 3 on
 		device ref iommu_3 on end
 		device ref rcec_3 on end
-		chip vendorcode/amd/opensil/genoa_poc/mpio # P0
+		chip vendorcode/amd/opensil/chip/mpio # P0
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "0"
 			register "end_lane" = "15"
@@ -145,7 +145,7 @@ chip soc/amd/genoa_poc
 			register "aspm" = "L1"
 			device ref gpp_bridge_3_0_a on end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio # G0
+		chip vendorcode/amd/opensil/chip/mpio # G0
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "96"
 			register "end_lane" = "111"
@@ -153,7 +153,7 @@ chip soc/amd/genoa_poc
 			register "aspm" = "L1"
 			device ref gpp_bridge_3_0_b on end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "132"
 			register "end_lane" = "133"
@@ -161,7 +161,7 @@ chip soc/amd/genoa_poc
 			register "aspm" = "L1"
 			device ref gpp_bridge_3_0_c on end # WAFL
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "134"
 			register "end_lane" = "134"
@@ -170,7 +170,7 @@ chip soc/amd/genoa_poc
 			register "bmc" = "1"
 			device ref gpp_bridge_3_1_c on end # BMC
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			register "type" = "IFTYPE_PCIE"
 			register "start_lane" = "135"
 			register "end_lane" = "135"

src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default

@@ -9,3 +9,4 @@ sata_mode=AHCI
 usb3_mode=Enable
 usb3_drv=Enable
 usb3_streams=Enable
+audio_panel_type=HDA

src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout

@@ -51,6 +51,11 @@ entries
 #
 424          1       e       1        usb3_streams
 
+# audio_panel_type
+# HD Audio or AC'97
+#
+425          1       e       9        audio_panel_type
+
 # -----------------------------------------------------------------
 # Sandy/Ivy Bridge MRC Scrambler Seed values
 # note: MUST NOT be covered by checksum!
@@ -128,6 +133,10 @@ enumerations
 8     2     Auto
 8     3     SmartAuto
 
+# audio_panel_type
+9     0     HDA
+9     1     AC97
+
 # -----------------------------------------------------------------
 # <startBit[must be byte-aligned]> <endBit[must be byte aligned]>
 #     <bit where to start storing checksum[must be 16bits-aligned]>

src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c

@@ -1,6 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <device/azalia_device.h>
+#include <stdint.h>
+
+#include <option.h>
 
 const u32 cim_verb_data[] = {
 	0x10ec0887, /* Codec Vendor / Device ID: Realtek */
@@ -34,3 +37,32 @@ const u32 cim_verb_data[] = {
 const u32 pc_beep_verbs[0] = {};
 
 AZALIA_ARRAY_SIZES;
+
+void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
+{
+	unsigned int ac97 = get_uint_option("audio_panel_type", 0) & 0x1;
+
+	/*
+	 * The verbs above are for a HD Audio front panel.
+	 * With vendor firmware, if audio front panel type is set as AC97, line out 2
+	 * (0x1b) and mic 2 (0x19) pins of ALC887 are configured differently.
+	 *
+	 * The differences are all in the "Misc" fields of configuration defaults (in byte 2)
+	 * as shown below. ALC887 datasheet did not offer details on what those bits
+	 * (listed as reserved in HDA spec) are, so we'll have to take their word for it.
+	 *
+	 * Pin  | 0x19 | 0x1b
+	 * -----+------+-----
+	 * HDA  | 1100 | 1100
+	 * AC97 | 1001 | 0001
+	 */
+
+	const u32 verbs[] = {
+		AZALIA_VERB_12B(0, 0x19, 0x71d, 0x99),
+		AZALIA_VERB_12B(0, 0x1b, 0x71d, 0x41)
+	};
+
+	if ((viddid == 0x10ec0887) && ac97) {
+		azalia_program_verb_table(base, verbs, ARRAY_SIZE(verbs));
+	}
+}

src/mainboard/google/brox/Kconfig

@@ -44,7 +44,7 @@ config BOARD_GOOGLE_BASEBOARD_BROX
 	select DRIVERS_AUDIO_SOF
 	select DRIVERS_GFX_GENERIC
 	select HAVE_SLP_S0_GATE
-	select MEMORY_SOLDERDOWN
+	select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_GREENBAYUPOC
 	select SOC_INTEL_COMMON_BLOCK_IPU
 	select SOC_INTEL_CRASHLOG
 	select SOC_INTEL_RAPTORLAKE
@@ -70,6 +70,8 @@ config BOARD_GOOGLE_LOTSO
 
 config BOARD_GOOGLE_GREENBAYUPOC
 	select BOARD_GOOGLE_BASEBOARD_BROX
+	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select MEMORY_SODIMM
 
 if BOARD_GOOGLE_BROX_COMMON
 

src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb

@@ -21,6 +21,9 @@ chip soc/intel/alderlake
 	# seen on J0 and Q0 SKUs
 	register "disable_package_c_state_demotion" = "1"
 
+	# Disable C1 state auto-demotion for all brox baseboards
+	register "disable_c1_state_auto_demotion" = "1"
+
 	# DPTF enable
 	register "dptf_enable" = "1"
 

src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk

@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+romstage-y += memory.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-y += gpio.c
+ramstage-y += ramstage.c

src/mainboard/google/brox/variants/greenbayupoc/gpio.c

@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/*
+ * This header block is used to supply information to arbitrage, a
+ * google-internal tool. Updating it incorrectly will lead to issues,
+ * so please don't update it unless a change is specifically required.
+ * BaseID: E3110FFB1FCDA587
+ * Overrides: None
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* GPP_A18 : [NF1: DDSP_HPDB NF4: DISP_MISCB NF6: USB_C_GPP_A18] ==> NC */
+	PAD_NC(GPP_A18, NONE),
+	/* GPP_A19 : [NF1: DDSP_HPD1 NF4: DISP_MISC1 NF6: USB_C_GPP_A19] ==> NC */
+	PAD_NC(GPP_A19, NONE),
+	/* GPP_A20 : [NF1: DDSP_HPD2 NF4: DISP_MISC2 NF6: USB_C_GPP_A20] ==> NC */
+	PAD_NC(GPP_A20, NONE),
+
+	/* GPP_C0 : [NF1: SMBCLK NF6: USB_C_GPP_C0] ==> SMBCLK */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	/* GPP_C1 : [NF1: SMBDATA NF6: USB_C_GPP_C1] ==> SMBDATA */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+
+	/* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX
+	 * NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> NC */
+	PAD_NC(GPP_D9, NONE),
+	/* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX
+	 * NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> NC */
+	PAD_NC(GPP_D10, NONE),
+
+	/* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> NC */
+	PAD_NC(GPP_E4, NONE),
+
+	/* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> NC */
+	PAD_NC(GPP_E10, NONE),
+	/* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> NC */
+	PAD_NC(GPP_E12, NONE),
+	/* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> NC */
+	PAD_NC(GPP_E13, NONE),
+	/* GPP_E15 : SRCCLK_OE8_L ==> NC */
+	PAD_NC(GPP_E15, NONE),
+
+	/* GPP_H15 : [NF1: DDPB_CTRLCLK NF3: PCIE_LINK_DOWN NF6: USB_C_GPP_H15] ==> NC */
+	PAD_NC(GPP_H15, NONE),
+	/* GPP_H17 : [NF1: DDPB_CTRLDATA NF6: USB_C_GPP_H17] ==> NC */
+	PAD_NC(GPP_H17, NONE),
+
+	/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */
+	PAD_NC(GPP_S0, NONE),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* GPP_D11 : [] ==> EN_PP3300_SSD (NC) */
+	PAD_NC(GPP_D11, NONE),
+	/* GPP_E2  : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_E8 : GPP_E8 ==> PCH_WP_OD */
+	PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG),
+	/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_F9, 0, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> NC */
+	PAD_NC(GPP_F21, NONE),
+	/* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+	/* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2),
+	/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */
+	PAD_NC(GPP_S0, NONE),
+
+	/* CPU PCIe VGPIO for PEG60 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> NC */
+	PAD_NC(GPP_E10, NONE),
+	/* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> NC */
+	PAD_NC(GPP_E12, NONE),
+	/* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> NC */
+	PAD_NC(GPP_E13, NONE),
+	/* GPP_E15 : SRCCLK_OE8_L ==> NC */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */
+	PAD_CFG_GPO(GPP_F7, 1, PLTRST),
+	/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_F9, 1, DEEP),
+	/* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */
+	PAD_CFG_GPO(GPP_F17, 0, DEEP),
+	/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */
+	PAD_NC(GPP_S0, NONE),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
+}

src/mainboard/google/brox/variants/greenbayupoc/memory.c

@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg ddr4_mem_config = {
+	.type = MEM_TYPE_DDR4,
+
+	.rcomp = {
+		.resistor = 100,
+		.targets = {50, 20, 25, 25, 25},
+	},
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.ect = 1,
+
+	.UserBd = BOARD_TYPE_MOBILE,
+
+	.ddr_config = {
+		.dq_pins_interleaved = 0,
+	},
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &ddr4_mem_config;
+}
+
+bool variant_is_half_populated(void)
+{
+	return false;
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_DIMM_MODULE;
+	spd_info->smbus[0].addr_dimm[0] = 0x50;
+	spd_info->smbus[0].addr_dimm[1] = 0x51;
+	spd_info->smbus[1].addr_dimm[0] = 0x52;
+	spd_info->smbus[1].addr_dimm[1] = 0x53;
+}

src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk

@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-# This is an auto-generated file. Do not edit!!
-# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
-
-SPD_SOURCES = placeholder

src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt

@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-# This is an auto-generated file. Do not edit!!
-# Generated by:
-# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/brox/memory src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt
-
-DRAM Part Name                 ID to assign

src/mainboard/google/brox/variants/greenbayupoc/memory/mem_parts_used.txt

@@ -1,11 +0,0 @@
-# This is a CSV file containing a list of memory parts used by this variant.
-# One part per line with an optional fixed ID in column 2.
-# Only include a fixed ID if it is required for legacy reasons!
-# Generated IDs are dependent on the order of parts in this file,
-# so new parts must always be added at the end of the file!
-#
-# Generate an updated Makefile.mk and dram_id.generated.txt by running the
-# part_id_gen tool from util/spd_tools.
-# See util/spd_tools/README.md for more details and instructions.
-
-# Part Name

src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb

@@ -1,14 +1,202 @@
 fw_config
-	field STORAGE 0 1
+	field RETIMER 0 1
+		option RETIMER_UNKNOWN			0
+		option RETIMER_BYPASS			1
+	end
+	field STORAGE 2 3
 		option STORAGE_UNKNOWN			0
-		option STORAGE_UFS			1
-		option STORAGE_NVME			2
+		option STORAGE_NVME			1
+		option STORAGE_UFS			2
+	end
+	field WIFI 4
+		option WIFI_CNVI_WIFI			0
+		option WIFI_BT_PCIE			1
+	end
+	field UFC 5
+		option UFC_NONE				0
+		option UFC_USB				1
+	end
+	field AUDIO 6 7
+		option AUDIO_UNKNOWN			0
+		option AUDIO_REALTEK_ALC3247		1
 	end
 end
 
 chip soc/intel/alderlake
+	register "usb3_ports[0]" = "USB3_PORT_EMPTY"			# Disable UDB3 Port
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"		# Type-A port A0(DCI)
 
 	device domain 0 on
+		device ref igpu on
+			chip drivers/gfx/generic
+				register "device_count" = "6"
+				# DDIA for eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# DDIB for HDMI
+				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
+				register "device[1].name" = ""DD01""
+				# TCP0 (DP-1) for port C0
+				register "device[2].name" = ""DD02""
+				register "device[2].use_pld" = "true"
+				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+				# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
+				register "device[3].name" = ""DD03""
+				# TCP2 (DP-3) for port C2
+				register "device[4].name" = ""DD04""
+				register "device[4].use_pld" = "true"
+				register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+				# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
+				register "device[5].name" = ""DD05""
+				device generic 0 on end
+			end
+		end # Integrated Graphics Device
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port3 as usb2_port
+						use tcss_usb3_port3 as usb3_port
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C Port C2 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C0 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port C2 (MLB)""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "has_power_resource" = "1"
+						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port A0 (DCI)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb2_port9 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "has_power_resource" = "1"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A0 (DCI)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port A1 (DB)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
+						device ref usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref pcie4_0 on
+			# Enable CPU PCIE RP 1 using CLK 3
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_req = 3,
+				.clk_src = 3,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			probe STORAGE STORAGE_NVME
+			probe STORAGE STORAGE_UNKNOWN
+		end
+		device ref pcie_rp5 on
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW0_03"
+				register "add_acpi_dma_property" = "true"
+				device pci 00.0 on
+					probe WIFI WIFI_BT_PCIE
+				end
+			end
+			chip soc/intel/common/block/pcie/rtd3
+				# enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
+				register "srcclk_pin" = "1"
+				device generic 0 on end
+			end
+			probe WIFI WIFI_BT_PCIE
+		end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "add_acpi_dma_property" = "true"
+				register "enable_cnvi_ddr_rfim" = "true"
+				device generic 0 on end
+			end
+			probe WIFI WIFI_CNVI_WIFI
+		end
+		device ref smbus on end
 	end
 
 end

src/mainboard/google/brox/variants/greenbayupoc/ramstage.c

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <device/pci_ids.h>
+
+const struct cpu_power_limits limits[] = {
+	/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
+	/* All values are for performance config as per document #686872 */
+	{ PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 },
+	{ PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000,  64000,  64000, 126000 },
+	{ PCI_DID_INTEL_RPL_P_ID_3, 15,  6000, 15000,  55000,  55000, 114000 },
+};
+
+void variant_devtree_update(void)
+{
+	size_t total_entries = ARRAY_SIZE(limits);
+	variant_update_power_limits(limits, total_entries);
+}

src/mainboard/google/brox/variants/greenbayupoc/variant.c

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <fw_config.h>
+#include <sar.h>
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+	if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI))) {
+		printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n");
+		config->cnvi_bt_core = true;
+	}
+}
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
+}

src/mainboard/google/brya/Kconfig

@@ -446,6 +446,7 @@ config BOARD_GOOGLE_REDRIX4ES
 
 config BOARD_GOOGLE_RIVEN
 	select BOARD_GOOGLE_BASEBOARD_NISSA
+	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_TWINLAKE
 
 config BOARD_GOOGLE_SKOLAS

src/mainboard/google/brya/variants/glassway/Makefile.mk

@@ -4,4 +4,7 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-y += gpio.c
+
 ramstage-y += variant.c
+
+ramstage-y += ramstage.c

src/mainboard/google/brya/variants/glassway/ramstage.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	params->VccInAuxImonIccImax = 100; // 25 * 4 for ADL-N
+	printk(BIOS_INFO, "Override VccInAuxImonIccImax = %d\n", params->VccInAuxImonIccImax);
+}

src/mainboard/google/brya/variants/quandiso/overridetree.cb

@@ -264,6 +264,9 @@ chip soc/intel/alderlake
 				register "generic.detect" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
 				register "generic.reset_delay_ms" = "50"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_delay_ms" = "55"
+				register "generic.stop_off_delay_ms" = "5"
 				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
 				register "generic.enable_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"

src/mainboard/google/brya/variants/riven/memory/Makefile.mk

@@ -1,5 +1,10 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
-# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/riven/memory/ src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt
 
-SPD_SOURCES = placeholder
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 0(0b0000)  Parts = MT62F1G32D4DR-031 WT:B, H9JCNNNCP3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-5.hex      # ID = 2(0b0010)  Parts = K3LKLKL0EM-MGCN
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 3(0b0011)  Parts = K3LKBKB0BM-MGCP

src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt

@@ -1 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/riven/memory/ src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt
+
 DRAM Part Name                 ID to assign
+MT62F1G32D4DR-031 WT:B         0 (0000)
+MT62F512M32D2DR-031 WT:B       1 (0001)
+H9JCNNNBK3MLYR-N6E             1 (0001)
+K3LKLKL0EM-MGCN                2 (0010)
+K3LKBKB0BM-MGCP                3 (0011)
+H9JCNNNCP3MLYR-N6E             0 (0000)

src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt

@@ -9,3 +9,9 @@
 # See util/spd_tools/README.md for more details and instructions.
 
 # Part Name
+MT62F1G32D4DR-031 WT:B
+MT62F512M32D2DR-031 WT:B
+H9JCNNNBK3MLYR-N6E
+K3LKLKL0EM-MGCN
+K3LKBKB0BM-MGCP
+H9JCNNNCP3MLYR-N6E

src/mainboard/google/brya/variants/sundance/overridetree.cb

@@ -150,7 +150,7 @@ chip soc/intel/alderlake
 				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
 				register "generic.wake" = "GPE0_DW2_14"
 				register "generic.detect" = "1"
-				register "hid_desc_reg_offset" = "0x20"
+				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x38 on end
 			end
 		end

src/mainboard/google/dedede/variants/pirika/memory/Makefile.mk

@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# /tmp/go-build469829719/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
+# /tmp/go-build796126413/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
 
 SPD_SOURCES =
-SPD_SOURCES += spd/lp4x/set-1/spd-1.hex      # ID = 0(0b0000)  Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL
+SPD_SOURCES += spd/lp4x/set-1/spd-1.hex      # ID = 0(0b0000)  Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267
 SPD_SOURCES += spd/lp4x/set-1/spd-11.hex      # ID = 1(0b0001)  Parts = CXDB4CBAM-ML-A

src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt

@@ -1,10 +1,12 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# /tmp/go-build469829719/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
+# /tmp/go-build796126413/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 H9HCNNNBKMMLXR-NEE             0 (0000)
 K4U6E3S4AA-MGCR                0 (0000)
 K4U6E3S4AB-MGCL                0 (0000)
 CXDB4CBAM-ML-A                 1 (0001)
+MT53E512M32D1NP-046 WT:B       0 (0000)
+H54G46CYRBX267                 0 (0000)

src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt

@@ -2,3 +2,5 @@ H9HCNNNBKMMLXR-NEE
 K4U6E3S4AA-MGCR
 K4U6E3S4AB-MGCL
 CXDB4CBAM-ML-A
+MT53E512M32D1NP-046 WT:B
+H54G46CYRBX267

src/mainboard/google/eve/romstage.c

@@ -2,6 +2,7 @@
 
 #include <acpi/acpi.h>
 #include <boardid.h>
+#include <device/dram/ddr3.h>
 #include <string.h>
 #include <ec/google/chromeec/ec.h>
 #include <fsp/soc_binding.h>
@@ -37,7 +38,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 
 	mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data();
 	mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
-	mem_cfg->MemorySpdDataLen = SPD_LEN;
+	mem_cfg->MemorySpdDataLen = SPD_SIZE_MAX_DDR3;
 
 	/* Limit K4EBE304EB-EGCF memory to 1600MHz for stability */
 	if (board_id() < 6 && mainboard_get_spd_index() == 5) {

src/mainboard/google/eve/spd/spd.c

@@ -2,8 +2,10 @@
 
 #include <cbfs.h>
 #include <console/console.h>
+#include <device/dram/ddr3.h>
 #include <gpio.h>
 #include <soc/romstage.h>
+#include <spd.h>
 #include <string.h>
 
 #include "../gpio.h"
@@ -18,7 +20,7 @@ static void mainboard_print_spd_info(uint8_t spd[])
 	const int spd_ranks[8] = {  1,  2,  3,  4, -1, -1, -1, -1 };
 	const int spd_devw[8]  = {  4,  8, 16, 32, -1, -1, -1, -1 };
 	const int spd_busw[8]  = {  8, 16, 32, 64, -1, -1, -1, -1 };
-	char spd_name[SPD_PART_LEN+1] = { 0 };
+	char spd_name[SPD_DDR3_PART_LEN + 1] = { 0 };
 
 	int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
 	int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
@@ -30,21 +32,21 @@ static void mainboard_print_spd_info(uint8_t spd[])
 
 	/* Module type */
 	printk(BIOS_INFO, "SPD: module type is ");
-	switch (spd[SPD_DRAM_TYPE]) {
-	case SPD_DRAM_DDR3:
+	switch (spd[SPD_MEMORY_TYPE]) {
+	case SPD_MEMORY_TYPE_SDRAM_DDR3:
 		printk(BIOS_INFO, "DDR3\n");
 		break;
-	case SPD_DRAM_LPDDR3:
+	case SPD_MEMORY_TYPE_LPDDR3_INTEL:
 		printk(BIOS_INFO, "LPDDR3\n");
 		break;
 	default:
-		printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
+		printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_MEMORY_TYPE]);
 		break;
 	}
 
 	/* Module Part Number */
-	memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
-	spd_name[SPD_PART_LEN] = 0;
+	memcpy(spd_name, &spd[SPD_DDR3_PART_NUM], SPD_DDR3_PART_LEN);
+	spd_name[SPD_DDR3_PART_LEN] = 0;
 	printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
 
 	printk(BIOS_INFO,
@@ -86,16 +88,16 @@ uintptr_t mainboard_get_spd_data(void)
 		die("SPD data not found.");
 
 	/* make sure we have at least one SPD in the file. */
-	if (spd_file_len < SPD_LEN)
+	if (spd_file_len < SPD_SIZE_MAX_DDR3)
 		die("Missing SPD data.");
 
 	/* Make sure we did not overrun the buffer */
-	if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+	if (spd_file_len < ((spd_index + 1) * SPD_SIZE_MAX_DDR3)) {
 		printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n");
 		spd_index = 1;
 	}
 
-	spd_index *= SPD_LEN;
+	spd_index *= SPD_SIZE_MAX_DDR3;
 	mainboard_print_spd_info((uint8_t *)(spd_file + spd_index));
 
 	return (uintptr_t)(spd_file + spd_index);

src/mainboard/google/eve/spd/spd.h

@@ -3,18 +3,10 @@
 #ifndef MAINBOARD_SPD_H
 #define MAINBOARD_SPD_H
 
-#define SPD_LEN			256
-
-#define SPD_DRAM_TYPE		2
-#define  SPD_DRAM_DDR3		0x0b
-#define  SPD_DRAM_LPDDR3	0xf1
 #define SPD_DENSITY_BANKS	4
 #define SPD_ADDRESSING		5
 #define SPD_ORGANIZATION	7
 #define SPD_BUS_DEV_WIDTH	8
-#define SPD_PART_OFF		128
-#define  SPD_PART_LEN		18
-#define SPD_MANU_OFF		148
 
 int mainboard_get_spd_index(void);
 uintptr_t mainboard_get_spd_data(void);

src/mainboard/google/glados/romstage.c

@@ -2,6 +2,7 @@
 
 #include <acpi/acpi.h>
 #include <baseboard/variant.h>
+#include <device/dram/ddr3.h>
 #include <ec/google/chromeec/ec.h>
 #include <gpio.h>
 #include <soc/romstage.h>
@@ -30,7 +31,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const int spd_idx = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
 
-	mem_cfg->MemorySpdDataLen = SPD_LEN;
+	mem_cfg->MemorySpdDataLen = SPD_SIZE_MAX_DDR3;
 	mem_cfg->DqPinsInterleaved = FALSE;
 
 	spd_memory_init_params(mupd, spd_idx);

src/mainboard/google/glados/spd/spd.c

@@ -2,8 +2,10 @@
 
 #include <cbfs.h>
 #include <console/console.h>
+#include <device/dram/ddr3.h>
 #include <gpio.h>
 #include <soc/romstage.h>
+#include <spd.h>
 #include <string.h>
 #include <baseboard/variant.h>
 
@@ -19,7 +21,7 @@ static void mainboard_print_spd_info(uint8_t spd[])
 	const int spd_ranks[8] = {  1,  2,  3,  4, -1, -1, -1, -1 };
 	const int spd_devw[8]  = {  4,  8, 16, 32, -1, -1, -1, -1 };
 	const int spd_busw[8]  = {  8, 16, 32, 64, -1, -1, -1, -1 };
-	char spd_name[SPD_PART_LEN+1] = { 0 };
+	char spd_name[SPD_DDR3_PART_LEN + 1] = { 0 };
 
 	int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
 	int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
@@ -31,21 +33,21 @@ static void mainboard_print_spd_info(uint8_t spd[])
 
 	/* Module type */
 	printk(BIOS_INFO, "SPD: module type is ");
-	switch (spd[SPD_DRAM_TYPE]) {
-	case SPD_DRAM_DDR3:
+	switch (spd[SPD_MEMORY_TYPE]) {
+	case SPD_MEMORY_TYPE_SDRAM_DDR3:
 		printk(BIOS_INFO, "DDR3\n");
 		break;
-	case SPD_DRAM_LPDDR3:
+	case SPD_MEMORY_TYPE_LPDDR3_INTEL:
 		printk(BIOS_INFO, "LPDDR3\n");
 		break;
 	default:
-		printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
+		printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_MEMORY_TYPE]);
 		break;
 	}
 
 	/* Module Part Number */
-	memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
-	spd_name[SPD_PART_LEN] = 0;
+	memcpy(spd_name, &spd[SPD_DDR3_PART_NUM], SPD_DDR3_PART_LEN);
+	spd_name[SPD_DDR3_PART_LEN] = 0;
 	printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
 
 	printk(BIOS_INFO,
@@ -83,16 +85,16 @@ void spd_memory_init_params(FSPM_UPD *mupd, int spd_index)
 		die("SPD data not found.");
 
 	/* make sure we have at least one SPD in the file. */
-	if (spd_file_len < SPD_LEN)
+	if (spd_file_len < SPD_SIZE_MAX_DDR3)
 		die("Missing SPD data.");
 
 	/* Make sure we did not overrun the buffer */
-	if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+	if (spd_file_len < ((spd_index + 1) * SPD_SIZE_MAX_DDR3)) {
 		printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n");
 		spd_index = 1;
 	}
 
-	const size_t spd_offset = spd_index * SPD_LEN;
+	const size_t spd_offset = spd_index * SPD_SIZE_MAX_DDR3;
 	/* Make sure a valid SPD was found */
 	if (spd_file[spd_offset] == 0)
 		die("Invalid SPD data.");

src/mainboard/google/glados/spd/spd.h

@@ -3,17 +3,9 @@
 #ifndef MAINBOARD_SPD_H
 #define MAINBOARD_SPD_H
 
-#define SPD_LEN			256
-
-#define SPD_DRAM_TYPE		2
-#define  SPD_DRAM_DDR3		0x0b
-#define  SPD_DRAM_LPDDR3	0xf1
 #define SPD_DENSITY_BANKS	4
 #define SPD_ADDRESSING		5
 #define SPD_ORGANIZATION	7
 #define SPD_BUS_DEV_WIDTH	8
-#define SPD_PART_OFF		128
-#define  SPD_PART_LEN		18
-#define SPD_MANU_OFF		148
 
 #endif

src/mainboard/google/rambi/romstage.c

@@ -2,6 +2,7 @@
 
 #include <cbfs.h>
 #include <console/console.h>
+#include <device/dram/ddr3.h>
 #include <soc/gpio.h>
 #include <soc/mrc_wrapper.h>
 #include <soc/romstage.h>
@@ -38,7 +39,7 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
 	if (dual_channel_config & (1 << ram_id))
 		*dual = 1;
 
-	return &spd_file_content[SPD_SIZE * ram_id];
+	return &spd_file_content[SPD_SIZE_MAX_DDR3 * ram_id];
 }
 
 void mainboard_fill_mrc_params(struct mrc_params *mp)
@@ -52,7 +53,7 @@ void mainboard_fill_mrc_params(struct mrc_params *mp)
 	if (!spd_file)
 		die("SPD data not found.");
 
-	spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE,
+	spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE_MAX_DDR3,
 	                              &dual_channel);
 
 	mp->mainboard.dram_type = DRAM_DDR3L;

src/mainboard/google/rambi/variants/banjo/include/variant/variant.h

@@ -18,7 +18,6 @@
 static const uint32_t dual_channel_config =
 	(1 << 1) | (1 << 3) | (1 << 5);
 
-#define SPD_SIZE 256
 #define GPIO_SSUS_37_PAD 57
 #define GPIO_SSUS_38_PAD 50
 #define GPIO_SSUS_39_PAD 58

src/mainboard/google/rambi/variants/candy/include/variant/variant.h

@@ -24,7 +24,6 @@
 static const uint32_t dual_channel_config =
 	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 6) | (1 << 7) | (1 << 10);
 
-#define SPD_SIZE 256
 #define GPIO_SSUS_37_PAD 57
 #define GPIO_SSUS_38_PAD 50
 #define GPIO_SSUS_39_PAD 58

src/mainboard/google/rambi/variants/clapper/include/variant/variant.h

@@ -20,7 +20,6 @@
 static const uint32_t dual_channel_config =
 	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6);
 
-#define SPD_SIZE 256
 #define GPIO_SSUS_37_PAD 57
 #define GPIO_SSUS_38_PAD 50
 #define GPIO_SSUS_39_PAD 58

src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h

@@ -20,7 +20,6 @@
 static const uint32_t dual_channel_config =
 	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6);
 
-#define SPD_SIZE 256
 #define GPIO_SSUS_37_PAD 57
 #define GPIO_SSUS_38_PAD 50
 #define GPIO_SSUS_39_PAD 58

src/mainboard/google/rambi/variants/expresso/include/variant/variant.h

@@ -18,7 +18,6 @@
 static const uint32_t dual_channel_config =
 	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
 
-#define SPD_SIZE 256
 #define GPIO_SSUS_37_PAD 57
 #define GPIO_SSUS_38_PAD 50
 #define GPIO_SSUS_39_PAD 58

src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h

@@ -24,7 +24,6 @@ static const uint32_t dual_channel_config =
 	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) |
 	(1 << 4) |	      (1 << 6) | (1 << 7);
 
-#define SPD_SIZE 256
 #define GPIO_SSUS_37_PAD 57
 #define GPIO_SSUS_38_PAD 50
 #define GPIO_SSUS_39_PAD 58

src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h

@@ -20,7 +20,6 @@
 static const uint32_t dual_channel_config =
 	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 6) | (1 << 7);
 
-#define SPD_SIZE 256
 #define GPIO_SSUS_37_PAD 57
 #define GPIO_SSUS_38_PAD 50
 #define GPIO_SSUS_39_PAD 58

src/mainboard/google/rambi/variants/heli/include/variant/variant.h

@@ -18,7 +18,6 @@
 static const uint32_t dual_channel_config =
 	(1 << 6) | (1 << 7);
 
-#define SPD_SIZE 256
 #define GPIO_SSUS_37_PAD 57
 #define GPIO_SSUS_38_PAD 50
 #define GPIO_SSUS_39_PAD 58

src/mainboard/google/rambi/variants/kip/include/variant/variant.h

@@ -20,7 +20,6 @@
 static const uint32_t dual_channel_config =
 	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
 
-#define SPD_SIZE 256
 #define GPIO_SSUS_37_PAD 57
 #define GPIO_SSUS_38_PAD 50
 #define GPIO_SSUS_39_PAD 58

src/mainboard/google/rambi/variants/ninja/include/variant/variant.h

@@ -20,7 +20,6 @@
 static const uint32_t dual_channel_config =
 	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6);
 
-#define SPD_SIZE 256
 #define GPIO_SSUS_37_PAD 57
 #define GPIO_SSUS_38_PAD 50
 #define GPIO_SSUS_39_PAD 58

src/mainboard/google/rambi/variants/orco/include/variant/variant.h

@@ -20,7 +20,6 @@
 static const uint32_t dual_channel_config =
 	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6);
 
-#define SPD_SIZE 256
 #define GPIO_SSUS_37_PAD 57
 #define GPIO_SSUS_38_PAD 50
 #define GPIO_SSUS_39_PAD 58

src/mainboard/google/rambi/variants/quawks/include/variant/variant.h

@@ -20,7 +20,6 @@
 static const uint32_t dual_channel_config =
 	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
 
-#define SPD_SIZE 256
 #define GPIO_SSUS_37_PAD 57
 #define GPIO_SSUS_38_PAD 50
 #define GPIO_SSUS_39_PAD 58

src/mainboard/google/rambi/variants/rambi/include/variant/variant.h

@@ -17,7 +17,6 @@
 static const uint32_t dual_channel_config =
 	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
 
-#define SPD_SIZE 256
 #define GPIO_SSUS_37_PAD 57
 #define GPIO_SSUS_38_PAD 50
 #define GPIO_SSUS_39_PAD 58

src/mainboard/google/rambi/variants/squawks/include/variant/variant.h

@@ -20,7 +20,6 @@
 static const uint32_t dual_channel_config =
 	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
 
-#define SPD_SIZE 256
 #define GPIO_SSUS_37_PAD 57
 #define GPIO_SSUS_38_PAD 50
 #define GPIO_SSUS_39_PAD 58

src/mainboard/google/rambi/variants/sumo/include/variant/variant.h

@@ -20,7 +20,6 @@
 static const uint32_t dual_channel_config =
 	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6);
 
-#define SPD_SIZE 256
 #define GPIO_SSUS_37_PAD 57
 #define GPIO_SSUS_38_PAD 50
 #define GPIO_SSUS_39_PAD 58

src/mainboard/google/rambi/variants/swanky/include/variant/variant.h

@@ -16,7 +16,6 @@
 static const uint32_t dual_channel_config =
 	(1 << 2) | (1 << 3);
 
-#define SPD_SIZE 256
 #define GPIO_SSUS_37_PAD 57
 #define GPIO_SSUS_38_PAD 50
 #define GPIO_SSUS_39_PAD 58

src/mainboard/google/rambi/variants/winky/include/variant/variant.h

@@ -18,7 +18,6 @@
 static const uint32_t dual_channel_config =
 	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
 
-#define SPD_SIZE 256
 #define GPIO_SSUS_37_PAD 57
 #define GPIO_SSUS_38_PAD 50
 #define GPIO_SSUS_39_PAD 58

src/mainboard/google/rex/variants/deku/overridetree.cb

@@ -60,7 +60,7 @@ chip soc/intel/meteorlake
 	# The ICC Limit is represented in 1/4 A increments, i.e., a value of 400 = 100A
 	# For GT VR configuration
 	register "enable_fast_vmode[VR_DOMAIN_GT]" = "1"
-	register "cep_enable[VR_DOMAIN_IA]" = "1"
+	register "cep_enable[VR_DOMAIN_GT]" = "1"
 	register "fast_vmode_i_trip[VR_DOMAIN_GT]" = "216" # 54A
 	# For SA VR configuration
 	register "enable_fast_vmode[VR_DOMAIN_SA]" = "1"

src/mainboard/intel/harcuvar/spd/spd.c

@@ -2,6 +2,8 @@
 
 #include <cbfs.h>
 #include <console/console.h>
+#include <device/dram/ddr4.h>
+#include <spd.h>
 
 #include "spd.h"
 
@@ -19,17 +21,17 @@ uint8_t *mainboard_find_spd_data(void)
 	if (!spd_file)
 		die("SPD data not found.");
 
-	if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+	if (spd_file_len < ((spd_index + 1) * SPD_SIZE_MAX_DDR4)) {
 		printk(BIOS_ERR,
 		       "SPD index override to 0 due to incorrect SPD index.\n");
 		spd_index = 0;
 	}
 
-	if (spd_file_len < SPD_LEN)
+	if (spd_file_len < SPD_SIZE_MAX_DDR4)
 		die("Missing SPD data.");
 
 	/* Assume same memory in both channels */
-	spd_index *= SPD_LEN;
+	spd_index *= SPD_SIZE_MAX_DDR4;
 	spd_data = (uint8_t *)(spd_file + spd_index);
 
 	/* Make sure a valid SPD was found */

src/mainboard/intel/harcuvar/spd/spd.h

@@ -5,18 +5,6 @@
 
 #include <stdint.h>
 
-#define SPD_LEN 512
-
-#define SPD_DRAM_TYPE 2
-#define SPD_DRAM_DDR3 0x0b
-#define SPD_DRAM_LPDDR3 0xf1
-#define SPD_DENSITY_BANKS 4
-#define SPD_ADDRESSING 5
-#define SPD_ORGANIZATION 7
-#define SPD_BUS_DEV_WIDTH 8
-#define SPD_PART_OFF 128
-#define SPD_PART_LEN 18
-
 uint8_t *mainboard_find_spd_data(void);
 
 #endif

src/mainboard/intel/kunimitsu/romstage.c

@@ -4,6 +4,9 @@
 #include <gpio.h>
 #include "gpio.h"
 #include <soc/romstage.h>
+#include <device/dram/ddr3.h>
+#include <spd.h>
+
 #include "spd/spd.h"
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
@@ -20,5 +23,5 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data();
 	if (mainboard_has_dual_channel_mem())
 		mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
-	mem_cfg->MemorySpdDataLen = SPD_LEN;
+	mem_cfg->MemorySpdDataLen = SPD_SIZE_MAX_DDR3;
 }

src/mainboard/intel/kunimitsu/spd/spd.h

@@ -8,19 +8,6 @@
 
 #define MAINBOARD_SPD_H
 
-#define SPD_LEN			256
-
-#define SPD_DRAM_TYPE		2
-#define  SPD_DRAM_DDR3		0x0b
-#define  SPD_DRAM_LPDDR3	0xf1
-#define SPD_DENSITY_BANKS	4
-#define SPD_ADDRESSING		5
-#define SPD_ORGANIZATION	7
-#define SPD_BUS_DEV_WIDTH	8
-#define SPD_PART_OFF		128
-#define  SPD_PART_LEN		18
-#define SPD_MANU_OFF		148
-
 #define HYNIX_SINGLE_CHAN	0x1
 #define SAMSUNG_SINGLE_CHAN	0x4
 #define MIC_SINGLE_CHAN		0x5

src/mainboard/intel/kunimitsu/spd/spd_util.c

@@ -1,8 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 #include <cbfs.h>
 #include <console/console.h>
+#include <device/dram/ddr3.h>
+#include <spd.h>
 #include <stdint.h>
 #include <string.h>
+
 #include "boardid.h"
 #include "spd.h"
 
@@ -72,16 +75,16 @@ uintptr_t mainboard_get_spd_data(void)
 		die("SPD data not found.");
 
 	/* make sure we have at least one SPD in the file. */
-	if (spd_file_len < SPD_LEN)
+	if (spd_file_len < SPD_SIZE_MAX_DDR3)
 		die("Missing SPD data.");
 
 	/* Make sure we did not overrun the buffer */
-	if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+	if (spd_file_len < ((spd_index + 1) * SPD_SIZE_MAX_DDR3)) {
 		printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
 		spd_index = 0;
 	}
 
-	spd_span = spd_index * SPD_LEN;
+	spd_span = spd_index * SPD_SIZE_MAX_DDR3;
 	return (uintptr_t)(spd_file + spd_span);
 }
 

src/mainboard/protectli/vault_cml/Kconfig

@@ -1,11 +1,12 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-if BOARD_PROTECTLI_VP4630_VP4650 || BOARD_PROTECTLI_VP4670
+if BOARD_PROTECTLI_VP46XX
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
 	select GFX_GMA_IGNORE_PRESENCE_STRAPS
+	select SOC_INTEL_COMETLAKE_1_2
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
@@ -15,8 +16,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select MAINBOARD_HAS_LIBGFXINIT
 	select MEMORY_MAPPED_TPM
 	select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
-	select SOC_INTEL_COMETLAKE_1 if BOARD_PROTECTLI_VP4670
-	select SOC_INTEL_COMETLAKE_2 if BOARD_PROTECTLI_VP4630_VP4650
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPI_FLASH_MACRONIX
 	select SUPERIO_ITE_IT8784E
@@ -25,8 +24,7 @@ config MAINBOARD_DIR
 	default "protectli/vault_cml"
 
 config MAINBOARD_PART_NUMBER
-	default "VP4630/VP4650" if BOARD_PROTECTLI_VP4630_VP4650
-	default "VP4670" if BOARD_PROTECTLI_VP4670
+	default "VP46XX"
 
 config MAINBOARD_FAMILY
 	default "Vault Pro"

src/mainboard/protectli/vault_cml/Kconfig.name

@@ -1,7 +1,4 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-config BOARD_PROTECTLI_VP4630_VP4650
-	bool "VP4630/VP4650"
-
-config BOARD_PROTECTLI_VP4670
-	bool "VP4670"
+config BOARD_PROTECTLI_VP46XX
+	bool "VP4630/VP4650/VP4670"

src/northbridge/intel/haswell/broadwell_mrc/raminit.c

@@ -8,6 +8,7 @@
 #include <cbmem.h>
 #include <cbfs.h>
 #include <cf9_reset.h>
+#include <device/dram/ddr3.h>
 #include <memory_info.h>
 #include <mrc_cache.h>
 #include <device/device.h>
@@ -245,7 +246,6 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
 }
 
 #include <device/smbus_host.h>
-#define SPD_LEN 256
 
 /* Copy SPD data for on-board memory */
 static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi)
@@ -261,20 +261,21 @@ static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi)
 	if (!spd_file)
 		die("SPD data not found.");
 
-	if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) {
+	if (spd_file_len < ((spdi->spd_index + 1) * SPD_SIZE_MAX_DDR3)) {
 		printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
 		spdi->spd_index = 0;
 	}
 
-	if (spd_file_len < SPD_LEN)
+	if (spd_file_len < SPD_SIZE_MAX_DDR3)
 		die("Missing SPD data.");
 
 	/* MRC only uses index 0, but coreboot uses the other indices */
-	memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_LEN), SPD_LEN);
+	memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_SIZE_MAX_DDR3),
+		SPD_SIZE_MAX_DDR3);
 
 	for (size_t i = 1; i < ARRAY_SIZE(spdi->addresses); i++) {
 		if (spdi->addresses[i] == SPD_MEMORY_DOWN)
-			memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_LEN);
+			memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_SIZE_MAX_DDR3);
 	}
 }
 

src/northbridge/intel/haswell/haswell_mrc/pei_data.h

@@ -8,8 +8,6 @@
 typedef void (*tx_byte_func)(unsigned char byte);
 #define PEI_VERSION 15
 
-#define SPD_LEN 256
-
 #define PEI_USB_OC_PIN_SKIP 8
 
 enum pei_usb2_port_location {
@@ -82,7 +80,7 @@ struct pei_data
 	int usb_xhci_on_resume;
 	struct pei_usb2_port_setting usb2_ports[16];
 	struct pei_usb3_port_setting usb3_ports[16];
-	uint8_t spd_data[4][SPD_LEN];
+	uint8_t spd_data[4][SPD_SIZE_MAX_DDR3];
 	tx_byte_func tx_byte;
 } __packed;
 

src/northbridge/intel/haswell/haswell_mrc/raminit.c

@@ -291,20 +291,21 @@ static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi)
 	if (!spd_file)
 		die("SPD data not found.");
 
-	if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) {
+	if (spd_file_len < ((spdi->spd_index + 1) * SPD_SIZE_MAX_DDR3)) {
 		printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
 		spdi->spd_index = 0;
 	}
 
-	if (spd_file_len < SPD_LEN)
+	if (spd_file_len < SPD_SIZE_MAX_DDR3)
 		die("Missing SPD data.");
 
 	/* MRC only uses index 0, but coreboot uses the other indices */
-	memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_LEN), SPD_LEN);
+	memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_SIZE_MAX_DDR3),
+		SPD_SIZE_MAX_DDR3);
 
 	for (size_t i = 1; i < ARRAY_SIZE(spdi->addresses); i++) {
 		if (spdi->addresses[i] == SPD_MEMORY_DOWN)
-			memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_LEN);
+			memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_SIZE_MAX_DDR3);
 	}
 }
 

src/northbridge/intel/haswell/native_raminit/raminit_native.h

@@ -6,7 +6,8 @@
 #include <device/dram/ddr3.h>
 #include <northbridge/intel/haswell/haswell.h>
 
-#define SPD_LEN 256
+/** TODO (Angel): Remove this after in-review patches are submitted **/
+#define SPD_LEN SPD_SIZE_MAX_DDR3
 
 /* 8 data lanes + 1 ECC lane */
 #define NUM_LANES		9

src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c

@@ -27,24 +27,24 @@ static const uint8_t *get_spd_data_from_cbfs(struct spd_info *spdi)
 		return NULL;
 	}
 
-	if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) {
+	if (spd_file_len < ((spdi->spd_index + 1) * SPD_SIZE_MAX_DDR3)) {
 		printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
 		spdi->spd_index = 0;
 	}
 
-	if (spd_file_len < SPD_LEN) {
+	if (spd_file_len < SPD_SIZE_MAX_DDR3) {
 		printk(BIOS_ERR, "Invalid SPD data in CBFS\n");
 		return NULL;
 	}
 
-	return spd_file + (spdi->spd_index * SPD_LEN);
+	return spd_file + (spdi->spd_index * SPD_SIZE_MAX_DDR3);
 }
 
 static void get_spd_for_dimm(struct raminit_dimm_info *const dimm, const uint8_t *cbfs_spd)
 {
 	if (dimm->spd_addr == SPD_MEMORY_DOWN) {
 		if (cbfs_spd) {
-			memcpy(dimm->raw_spd, cbfs_spd, SPD_LEN);
+			memcpy(dimm->raw_spd, cbfs_spd, SPD_SIZE_MAX_DDR3);
 			dimm->valid = true;
 			printk(RAM_DEBUG, "memory-down\n");
 			return;
@@ -60,9 +60,9 @@ static void get_spd_for_dimm(struct raminit_dimm_info *const dimm, const uint8_t
 		return;
 	}
 	printk(RAM_DEBUG, "and DDR3\n");
-	if (i2c_eeprom_read(dimm->spd_addr, 0, SPD_LEN, dimm->raw_spd) != SPD_LEN) {
+	if (i2c_eeprom_read(dimm->spd_addr, 0, SPD_SIZE_MAX_DDR3, dimm->raw_spd) != SPD_SIZE_MAX_DDR3) {
 		printk(BIOS_WARNING, "I2C block read failed, trying SMBus byte reads\n");
-		for (uint32_t i = 0; i < SPD_LEN; i++)
+		for (uint32_t i = 0; i < SPD_SIZE_MAX_DDR3; i++)
 			dimm->raw_spd[i] = smbus_read_byte(dimm->spd_addr, i);
 	}
 	dimm->valid = true;

src/soc/amd/common/block/psp/Kconfig

@@ -96,6 +96,7 @@ config PSP_INCLUDES_HSP
 	  Select this config to indicate SoC includes Hardware Security Processor(HSP).
 
 config AMD_FWM_POSITION_20000_DEFAULT
+	# This is the default if nothing else is selected
 	bool
 
 config AMD_FWM_POSITION_420000_DEFAULT

src/soc/amd/genoa_poc/chipset.cb

@@ -16,78 +16,78 @@ chip soc/amd/genoa_poc
 		device pci 00.3 alias rcec_0 off end
 
 		device pci 01.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.1 alias gpp_bridge_0_0_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.2 alias gpp_bridge_0_1_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.3 alias gpp_bridge_0_2_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.4 alias gpp_bridge_0_3_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.5 alias gpp_bridge_0_4_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.6 alias gpp_bridge_0_5_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.7 alias gpp_bridge_0_6_a off end
 		end
 
 		device pci 02.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 02.1 alias gpp_bridge_0_7_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 02.2 alias gpp_bridge_0_8_a off end
 		end
 
 		device pci 03.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.1 alias gpp_bridge_0_0_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.2 alias gpp_bridge_0_1_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.3 alias gpp_bridge_0_2_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.4 alias gpp_bridge_0_3_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.5 alias gpp_bridge_0_4_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.6 alias gpp_bridge_0_5_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.7 alias gpp_bridge_0_6_b off end
 		end
 
 		device pci 04.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 04.1 alias gpp_bridge_0_7_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 04.2 alias gpp_bridge_0_8_b off end
 		end
 
 		device pci 05.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 05.1 alias gpp_bridge_0_0_c off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 05.2 alias gpp_bridge_0_1_c off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 05.3 alias gpp_bridge_0_2_c off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 05.4 alias gpp_bridge_0_3_c off end
 		end
 
@@ -128,64 +128,64 @@ chip soc/amd/genoa_poc
 		device pci 00.3 alias rcec_1 off end
 
 		device pci 01.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.1 alias gpp_bridge_1_0_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.2 alias gpp_bridge_1_1_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.3 alias gpp_bridge_1_2_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.4 alias gpp_bridge_1_3_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.5 alias gpp_bridge_1_4_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.6 alias gpp_bridge_1_5_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.7 alias gpp_bridge_1_6_a off end
 		end
 
 		device pci 02.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 02.1 alias gpp_bridge_1_7_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 02.2 alias gpp_bridge_1_8_a off end
 		end
 
 		device pci 03.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.1 alias gpp_bridge_1_0_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.2 alias gpp_bridge_1_1_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.3 alias gpp_bridge_1_2_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.4 alias gpp_bridge_1_3_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.5 alias gpp_bridge_1_4_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.6 alias gpp_bridge_1_5_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.7 alias gpp_bridge_1_6_b off end
 		end
 
 		device pci 04.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 04.1 alias gpp_bridge_1_7_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 04.2 alias gpp_bridge_1_8_b off end
 		end
 
@@ -207,64 +207,64 @@ chip soc/amd/genoa_poc
 		device pci 00.3 alias rcec_2 off end
 
 		device pci 01.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.1 alias gpp_bridge_2_0_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.2 alias gpp_bridge_2_1_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.3 alias gpp_bridge_2_2_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.4 alias gpp_bridge_2_3_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.5 alias gpp_bridge_2_4_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.6 alias gpp_bridge_2_5_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.7 alias gpp_bridge_2_6_a off end
 		end
 
 		device pci 02.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 02.1 alias gpp_bridge_2_7_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 02.2 alias gpp_bridge_2_8_a off end
 		end
 
 		device pci 03.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.1 alias gpp_bridge_2_0_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.2 alias gpp_bridge_2_1_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.3 alias gpp_bridge_2_2_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.4 alias gpp_bridge_2_3_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.5 alias gpp_bridge_2_4_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.6 alias gpp_bridge_2_5_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.7 alias gpp_bridge_2_6_b off end
 		end
 
 		device pci 04.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 04.1 alias gpp_bridge_2_7_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 04.2 alias gpp_bridge_2_8_b off end
 		end
 
@@ -286,78 +286,78 @@ chip soc/amd/genoa_poc
 		device pci 00.3 alias rcec_3 off end
 
 		device pci 01.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.1 alias gpp_bridge_3_0_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.2 alias gpp_bridge_3_1_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.3 alias gpp_bridge_3_2_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.4 alias gpp_bridge_3_3_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.5 alias gpp_bridge_3_4_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.6 alias gpp_bridge_3_5_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 01.7 alias gpp_bridge_3_6_a off end
 		end
 
 		device pci 02.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 02.1 alias gpp_bridge_3_7_a off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 02.2 alias gpp_bridge_3_8_a off end
 		end
 
 		device pci 03.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.1 alias gpp_bridge_3_0_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.2 alias gpp_bridge_3_1_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.3 alias gpp_bridge_3_2_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.4 alias gpp_bridge_3_3_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.5 alias gpp_bridge_3_4_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.6 alias gpp_bridge_3_5_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 03.7 alias gpp_bridge_3_6_b off end
 		end
 
 		device pci 04.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 04.1 alias gpp_bridge_3_7_b off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 04.2 alias gpp_bridge_3_8_b off end
 		end
 
 		device pci 05.0 on end # Dummy device function, do not disable
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 05.1 alias gpp_bridge_3_0_c off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 05.2 alias gpp_bridge_3_1_c off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 05.3 alias gpp_bridge_3_2_c off end
 		end
-		chip vendorcode/amd/opensil/genoa_poc/mpio
+		chip vendorcode/amd/opensil/chip/mpio
 			device pci 05.4 alias gpp_bridge_3_3_c off end
 		end
 

src/soc/intel/common/block/cnvi/cnvi.c

@@ -21,6 +21,14 @@ static struct device_operations cnvi_wifi_ops = {
 };
 
 static const unsigned short wifi_pci_device_ids[] = {
+	PCI_DID_INTEL_PTL_CNVI_WIFI_0,
+	PCI_DID_INTEL_PTL_CNVI_WIFI_1,
+	PCI_DID_INTEL_PTL_CNVI_WIFI_2,
+	PCI_DID_INTEL_PTL_CNVI_WIFI_3,
+	PCI_DID_INTEL_LNL_CNVI_WIFI_0,
+	PCI_DID_INTEL_LNL_CNVI_WIFI_1,
+	PCI_DID_INTEL_LNL_CNVI_WIFI_2,
+	PCI_DID_INTEL_LNL_CNVI_WIFI_3,
 	PCI_DID_INTEL_MTL_CNVI_WIFI_0,
 	PCI_DID_INTEL_MTL_CNVI_WIFI_1,
 	PCI_DID_INTEL_MTL_CNVI_WIFI_2,

src/soc/intel/common/block/cpu/mp_init.c

@@ -32,7 +32,9 @@ static struct device_operations cpu_dev_ops = {
 };
 
 static const struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, CPUID_PANTHERLAKE_A0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_1, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_2, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_2, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_B0, CPUID_EXACT_MATCH_MASK },

src/soc/intel/common/block/cse/cse.c

@@ -1475,6 +1475,7 @@ struct device_operations cse_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_PTL_CSE0,
 	PCI_DID_INTEL_LNL_CSE0,
 	PCI_DID_INTEL_MTL_CSE0,
 	PCI_DID_INTEL_APL_CSE0,

src/soc/intel/common/block/dsp/dsp.c

@@ -13,6 +13,14 @@ static struct device_operations dsp_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_PTL_AUDIO_1,
+	PCI_DID_INTEL_PTL_AUDIO_2,
+	PCI_DID_INTEL_PTL_AUDIO_3,
+	PCI_DID_INTEL_PTL_AUDIO_4,
+	PCI_DID_INTEL_PTL_AUDIO_5,
+	PCI_DID_INTEL_PTL_AUDIO_6,
+	PCI_DID_INTEL_PTL_AUDIO_7,
+	PCI_DID_INTEL_PTL_AUDIO_8,
 	PCI_DID_INTEL_LNL_AUDIO_1,
 	PCI_DID_INTEL_LNL_AUDIO_2,
 	PCI_DID_INTEL_LNL_AUDIO_3,

src/soc/intel/common/block/graphics/graphics.c

@@ -343,6 +343,7 @@ const struct device_operations graphics_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_PTL_GT2,
 	PCI_DID_INTEL_LNL_M_GT2,
 	PCI_DID_INTEL_RPL_U_GT1,
 	PCI_DID_INTEL_RPL_U_GT2,

src/soc/intel/common/block/hda/hda.c

@@ -21,6 +21,14 @@ struct device_operations hda_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_PTL_AUDIO_1,
+	PCI_DID_INTEL_PTL_AUDIO_2,
+	PCI_DID_INTEL_PTL_AUDIO_3,
+	PCI_DID_INTEL_PTL_AUDIO_4,
+	PCI_DID_INTEL_PTL_AUDIO_5,
+	PCI_DID_INTEL_PTL_AUDIO_6,
+	PCI_DID_INTEL_PTL_AUDIO_7,
+	PCI_DID_INTEL_PTL_AUDIO_8,
 	PCI_DID_INTEL_LNL_AUDIO_1,
 	PCI_DID_INTEL_LNL_AUDIO_2,
 	PCI_DID_INTEL_LNL_AUDIO_3,

src/soc/intel/common/block/i2c/i2c.c

@@ -174,6 +174,12 @@ struct device_operations i2c_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_PTL_I2C0,
+	PCI_DID_INTEL_PTL_I2C1,
+	PCI_DID_INTEL_PTL_I2C2,
+	PCI_DID_INTEL_PTL_I2C3,
+	PCI_DID_INTEL_PTL_I2C4,
+	PCI_DID_INTEL_PTL_I2C5,
 	PCI_DID_INTEL_LNL_I2C0,
 	PCI_DID_INTEL_LNL_I2C1,
 	PCI_DID_INTEL_LNL_I2C2,

src/soc/intel/common/block/ipu/ipu.c

@@ -12,6 +12,7 @@ struct device_operations ipu_pci_ops = {
 };
 
 static const uint16_t pci_device_ids[] = {
+	PCI_DID_INTEL_PTL_IPU,
 	PCI_DID_INTEL_LNL_IPU,
 	PCI_DID_INTEL_RPL_IPU,
 	PCI_DID_INTEL_MTL_IPU,

src/soc/intel/common/block/lpc/lpc.c

@@ -141,6 +141,14 @@ struct device_operations lpc_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_PTL_ESPI_0,
+	PCI_DID_INTEL_PTL_ESPI_1,
+	PCI_DID_INTEL_PTL_ESPI_2,
+	PCI_DID_INTEL_PTL_ESPI_3,
+	PCI_DID_INTEL_PTL_ESPI_4,
+	PCI_DID_INTEL_PTL_ESPI_5,
+	PCI_DID_INTEL_PTL_ESPI_6,
+	PCI_DID_INTEL_PTL_ESPI_7,
 	PCI_DID_INTEL_LNL_ESPI_0,
 	PCI_DID_INTEL_LNL_ESPI_1,
 	PCI_DID_INTEL_LNL_ESPI_2,

src/soc/intel/common/block/pcie/pcie.c

@@ -67,6 +67,14 @@ struct device_operations pcie_rp_ops = {
 };
 
 static const unsigned short pcie_device_ids[] = {
+	PCI_DID_INTEL_PTL_PCIE_RP1,
+	PCI_DID_INTEL_PTL_PCIE_RP2,
+	PCI_DID_INTEL_PTL_PCIE_RP3,
+	PCI_DID_INTEL_PTL_PCIE_RP4,
+	PCI_DID_INTEL_PTL_PCIE_RP5,
+	PCI_DID_INTEL_PTL_PCIE_RP6,
+	PCI_DID_INTEL_PTL_PCIE_RP7,
+	PCI_DID_INTEL_PTL_PCIE_RP8,
 	PCI_DID_INTEL_LNL_PCIE_RP1,
 	PCI_DID_INTEL_LNL_PCIE_RP2,
 	PCI_DID_INTEL_LNL_PCIE_RP3,