Compare commits
7 Commits
upstream-8
...
main
| Author | SHA1 | Date | |
|---|---|---|---|
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96084d5957 | ||
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b152f10d5a | ||
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b870b66834 | ||
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79be6da071 | ||
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397a4965b2 | ||
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78bd2710a7 | ||
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b62f86be43 |
@@ -28,6 +28,7 @@ payloads/external/edk2 \
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payloads/external/GRUB2 \
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payloads/external/LinuxBoot \
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payloads/external/skiboot \
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payloads/external/leanefi \
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payloads/external/coreDOOM \
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force-payload:
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7
payloads/external/Makefile.mk
vendored
7
payloads/external/Makefile.mk
vendored
@@ -436,6 +436,13 @@ payloads/external/skiboot/build/skiboot.elf:
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$(MAKE) -C payloads/external/skiboot all \
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CONFIG_SKIBOOT_GIT_REPO=$(CONFIG_SKIBOOT_GIT_REPO) \
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CONFIG_SKIBOOT_REVISION=$(CONFIG_SKIBOOT_REVISION)
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# leanefi
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payloads/external/leanefi/leanefi/build/leanefi.elf: FORCE $(DOTCONFIG)
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$(MAKE) -C payloads/external/leanefi
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FORCE: ;
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# COREDOOM
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payloads/external/coreDOOM/coredoom/doomgeneric/coredoom.elf coredoom:
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58
payloads/external/leanefi/Kconfig
vendored
Normal file
58
payloads/external/leanefi/Kconfig
vendored
Normal file
@@ -0,0 +1,58 @@
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if PAYLOAD_LEANEFI
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menu "leanEFI configuration"
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config PAYLOAD_FILE
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string
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default "payloads/external/leanefi/leanefi/build/leanefi.elf"
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config LEANEFI_EFI_ECPT
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bool
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default y if ARCH_ARM64
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config LEANEFI_HEAP_SIZE
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int "Heap size"
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default 131072
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help
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This is the heap size (malloc'able size) available
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to the payload.
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If unsure, set to 131072 (128K)
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config LEANEFI_STACK_SIZE
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int "Stack size"
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default 16384
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help
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This is the stack size available to the payload.
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If unsure, set to 16384 (16K)
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config LEANEFI_BASE_ADDRESS
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hex "Base address"
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default 0x62000000 if BOARD_EMULATION_QEMU_AARCH64
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#default 0x10023300000 if BOARD_EMULATION_QEMU_SBSA
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help
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This is the base address for the payload.
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config LEANEFI_PAYLOAD
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bool "Add a payload"
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default y
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help
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If selected leanEFI will start a payload.
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This option should only be unselected for debug purposes.
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config LEANEFI_PAYLOAD_PATH
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string "path to leanefi payload"
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depends on LEANEFI_PAYLOAD
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config LEANEFI_FDT
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bool "Add an FDT that is propagated as EFI configuration table"
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default y if BOARD_EMULATION_QEMU_AARCH64
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config LEANEFI_FDT_PATH
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string "path to FDT"
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depends on LEANEFI_FDT
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endmenu
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endif
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6
payloads/external/leanefi/Kconfig.name
vendored
Normal file
6
payloads/external/leanefi/Kconfig.name
vendored
Normal file
@@ -0,0 +1,6 @@
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config PAYLOAD_LEANEFI
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bool "leanefi"
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depends on ARCH_ARM64
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help
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Select this option if you want to build a coreboot image
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with an leanefi payload.
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22
payloads/external/leanefi/Makefile
vendored
Normal file
22
payloads/external/leanefi/Makefile
vendored
Normal file
@@ -0,0 +1,22 @@
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unexport KCONFIG_AUTOHEADER
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unexport KCONFIG_AUTOCONFIG
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unexport KCONFIG_DEPENDENCIES
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unexport KCONFIG_SPLITCONFIG
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unexport KCONFIG_TRISTATE
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unexport KCONFIG_NEGATIVES
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unexport $(COREBOOT_EXPORTS)
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build: leanefi
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$(MAKE) -C leanefi
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leanefi:
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git clone "https://review.coreboot.org/leanefi"
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distclean:
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rm -rf leanefi
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clean:
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rm -rf leanefi/build
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.PHONY: build clean distclean
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@@ -159,14 +159,15 @@ chip soc/intel/alderlake
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end
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device ref i2c0 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5650""
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register "hid" = ""RTL5682""
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register "name" = ""RT58""
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register "desc" = ""Realtek RT5650""
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register "desc" = ""Headset Codec""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-mode""
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register "property_list[0].integer" = "2"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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end # I2C0
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@@ -63,6 +63,8 @@ static const struct mb_cfg variant_memcfg = {
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.ccc_config = 0xff,
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},
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.LpDdrDqDqsReTraining = 1,
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.ect = 1, /* Early Command Training */
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.UserBd = BOARD_TYPE_ULT_ULX,
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@@ -1,96 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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config BOARD_SYSTEM76_MTL_COMMON
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def_bool n
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_GENERIC_BAYHUB_LV2
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select DRIVERS_GENERIC_CBFS_SERIAL
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select DRIVERS_GENERIC_CBFS_UUID
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select DRIVERS_I2C_HID
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select EC_SYSTEM76_EC
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_TPM2
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select MEMORY_MAPPED_TPM
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select NO_UART_ON_SUPERIO
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select PCIEXP_SUPPORT_RESIZABLE_BARS
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_CRASHLOG
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select SOC_INTEL_METEORLAKE
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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select TPM_RDRESP_NEED_DELAY
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config BOARD_SYSTEM76_DARP10
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select BOARD_SYSTEM76_MTL_COMMON
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select MAINBOARD_USES_IFD_GBE_REGION
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select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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select SOC_INTEL_METEORLAKE_U_H
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config BOARD_SYSTEM76_DARP10_B
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select BOARD_SYSTEM76_MTL_COMMON
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select MAINBOARD_USES_IFD_GBE_REGION
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select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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select SOC_INTEL_METEORLAKE_U_H
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if BOARD_SYSTEM76_MTL_COMMON
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config MAINBOARD_DIR
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default "system76/mtl"
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config VARIANT_DIR
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default "darp10" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config MAINBOARD_PART_NUMBER
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default "darp10" if BOARD_SYSTEM76_DARP10
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default "darp10-b" if BOARD_SYSTEM76_DARP10_B
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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default "Darter Pro" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B
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config MAINBOARD_VERSION
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default "darp10" if BOARD_SYSTEM76_DARP10
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default "darp10-b" if BOARD_SYSTEM76_DARP10_B
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config CMOS_DEFAULT_FILE
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default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
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config CONSOLE_POST
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default y
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config D3COLD_SUPPORT
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default n
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config DIMM_SPD_SIZE
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default 1024
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config FMDFILE
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
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||||
config ONBOARD_VGA_IS_PRIMARY
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default y
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||||
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||||
config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS
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default 36
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||||
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||||
config POST_DEVICE
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default n
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||||
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||||
config TPM_MEASURED_BOOT
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default y
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||||
config UART_FOR_CONSOLE
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default 0
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||||
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||||
# PM Timer Disabled, saves power
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||||
config USE_PM_ACPI_TIMER
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default n
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||||
endif
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@@ -1,7 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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||||
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||||
config BOARD_SYSTEM76_DARP10
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bool "darp10"
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||||
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||||
config BOARD_SYSTEM76_DARP10_B
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||||
bool "darp10-b"
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||||
@@ -1,14 +0,0 @@
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||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
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||||
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
|
||||
|
||||
bootblock-y += bootblock.c
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||||
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
|
||||
|
||||
romstage-y += variants/$(VARIANT_DIR)/romstage.c
|
||||
|
||||
ramstage-y += ramstage.c
|
||||
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
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||||
ramstage-y += variants/$(VARIANT_DIR)/gpio.c
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||||
ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
|
||||
ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
|
||||
@@ -1,31 +0,0 @@
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||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <drivers/intel/gma/acpi/gma.asl>
|
||||
|
||||
Scope (GFX0)
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||||
{
|
||||
Name (BRIG, Package (22) {
|
||||
100, /* default AC */
|
||||
100, /* default Battery */
|
||||
5,
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||||
10,
|
||||
15,
|
||||
20,
|
||||
25,
|
||||
30,
|
||||
35,
|
||||
40,
|
||||
45,
|
||||
50,
|
||||
55,
|
||||
60,
|
||||
65,
|
||||
70,
|
||||
75,
|
||||
80,
|
||||
85,
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||||
90,
|
||||
95,
|
||||
100
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||||
})
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||||
}
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||||
@@ -1,12 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#define EC_GPE_SCI 0x6E
|
||||
#define EC_GPE_SWI 0x6B
|
||||
#include <ec/system76/ec/acpi/ec.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
#include "sleep.asl"
|
||||
Scope (PCI0) {
|
||||
#include "backlight.asl"
|
||||
}
|
||||
}
|
||||
@@ -1,9 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
External(\TBTS, MethodObj)
|
||||
|
||||
Method(MPTS, 1, Serialized) {
|
||||
If (CondRefOf(\TBTS)) {
|
||||
\TBTS()
|
||||
}
|
||||
}
|
||||
@@ -1,6 +0,0 @@
|
||||
Vendor name: System76
|
||||
Category: laptop
|
||||
ROM package: WSON-8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
@@ -1,9 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <bootblock_common.h>
|
||||
#include <mainboard/gpio.h>
|
||||
|
||||
void bootblock_mainboard_early_init(void)
|
||||
{
|
||||
mainboard_configure_early_gpios();
|
||||
}
|
||||
@@ -1,5 +0,0 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
boot_option=Fallback
|
||||
debug_level=Debug
|
||||
me_state=Disable
|
||||
@@ -1,43 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
|
||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
|
||||
# RTC_CLK_ALTCENTURY
|
||||
400 8 r 0 century
|
||||
|
||||
412 4 e 6 debug_level
|
||||
416 1 e 2 me_state
|
||||
417 3 h 0 me_state_counter
|
||||
|
||||
# CMOS_VSTART_ramtop
|
||||
800 80 r 0 ramtop
|
||||
|
||||
984 16 h 0 check_sum
|
||||
|
||||
enumerations
|
||||
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
|
||||
6 0 Emergency
|
||||
6 1 Alert
|
||||
6 2 Critical
|
||||
6 3 Error
|
||||
6 4 Warning
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
|
||||
checksums
|
||||
|
||||
checksum 408 799 984
|
||||
@@ -1,67 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/meteorlake
|
||||
register "common_soc_config" = "{
|
||||
// Touchpad I2C bus
|
||||
.i2c[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 80,
|
||||
.fall_time_ns = 110,
|
||||
},
|
||||
}"
|
||||
|
||||
# Enable Enhanced Intel SpeedStep
|
||||
register "eist_enable" = "1"
|
||||
|
||||
# Thermal
|
||||
register "tcc_offset" = "8"
|
||||
|
||||
device cpu_cluster 0 on end
|
||||
|
||||
device domain 0 on
|
||||
device ref system_agent on end
|
||||
device ref igpu on
|
||||
# DDIA is eDP, TCP2 is HDMI
|
||||
register "ddi_port_A_config" = "1"
|
||||
register "ddi_ports_config" = "{
|
||||
[DDI_PORT_A] = DDI_ENABLE_HPD,
|
||||
[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
|
||||
}"
|
||||
|
||||
#register "gfx" = "GMA_DEFAULT_PANEL(0)"
|
||||
end
|
||||
device ref ioe_shared_sram on end
|
||||
device ref pmc_shared_sram on end
|
||||
device ref cnvi_wifi on
|
||||
register "cnvi_bt_core" = "true"
|
||||
register "cnvi_bt_audio_offload" = "true"
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref i2c1 on
|
||||
register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
|
||||
end
|
||||
|
||||
device ref heci1 on end
|
||||
device ref soc_espi on
|
||||
register "gen1_dec" = "0x00040069" # EC PM channel
|
||||
register "gen2_dec" = "0x00fc0e01" # AP/EC command
|
||||
register "gen3_dec" = "0x00fc0f01" # AP/EC debug
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end
|
||||
device ref p2sb on end
|
||||
device ref hda on
|
||||
register "pch_hda_audio_link_hda_enable" = "1"
|
||||
register "pch_hda_sdi_enable[0]" = "1"
|
||||
register "pch_hda_idisp_codec_enable" = "1"
|
||||
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
|
||||
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
|
||||
end
|
||||
device ref smbus on end
|
||||
device ref fast_spi on end
|
||||
end
|
||||
end
|
||||
@@ -1,36 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
//TODO: HACK FOR MISSING MISCCFG_GPIO_PM_CONFIG_BITS
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
ACPI_DSDT_REV_2,
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20110725
|
||||
)
|
||||
{
|
||||
#include <acpi/dsdt_top.asl>
|
||||
#include <soc/intel/common/block/acpi/acpi/platform.asl>
|
||||
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
Device (\_SB.PCI0)
|
||||
{
|
||||
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
|
||||
#include <soc/intel/meteorlake/acpi/southbridge.asl>
|
||||
#include <soc/intel/meteorlake/acpi/tcss.asl>
|
||||
}
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
}
|
||||
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
@@ -1,9 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
void mainboard_configure_early_gpios(void);
|
||||
void mainboard_configure_gpios(void);
|
||||
|
||||
#endif
|
||||
@@ -1,13 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <mainboard/gpio.h>
|
||||
#include <soc/ramstage.h>
|
||||
|
||||
static void mainboard_init(void *chip_info)
|
||||
{
|
||||
mainboard_configure_gpios();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.init = mainboard_init,
|
||||
};
|
||||
@@ -1,13 +0,0 @@
|
||||
FLASH 32M {
|
||||
SI_DESC 16K
|
||||
SI_GBE 8K
|
||||
SI_ME 10640K
|
||||
SI_BIOS@16M 16M {
|
||||
RW_MRC_CACHE 64K
|
||||
SMMSTORE(PRESERVE) 256K
|
||||
WP_RO {
|
||||
FMAP 4K
|
||||
COREBOOT(CBFS)
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,2 +0,0 @@
|
||||
Board name: darp10
|
||||
Release year: 2024
|
||||
Binary file not shown.
@@ -1,216 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <mainboard/gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0_EC
|
||||
PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1_EC
|
||||
PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC
|
||||
PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC
|
||||
PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC#
|
||||
PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), // ESPI_CLK_EC
|
||||
PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET_N
|
||||
// GPP_A07 missing
|
||||
// GPP_A08 missing
|
||||
// GPP_A09 missing
|
||||
// GPP_A10 missing
|
||||
PAD_CFG_GPO(GPP_A11, 0, DEEP), // ADDS_CODE
|
||||
PAD_CFG_GPI(GPP_A12, NONE, DEEP), // WLAN_WAKEUP#
|
||||
PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), // M2_SSD2_RST#
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
PAD_NC(GPP_A15, NONE), // CPU_SWI# (test point)
|
||||
PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), // ESPI_ALRT0#
|
||||
PAD_NC(GPP_A17, NONE), // TP_ATTN#_A17
|
||||
PAD_NC(GPP_A18, NONE),
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), // PMC_I2C_INT
|
||||
|
||||
PAD_CFG_GPI_INT(GPP_B00, NONE, PLTRST, LEVEL), // TP_ATTN#_B00
|
||||
PAD_NC(GPP_B01, NONE),
|
||||
PAD_NC(GPP_B02, NONE),
|
||||
PAD_NC(GPP_B03, NONE),
|
||||
PAD_CFG_GPO(GPP_B04, 0, DEEP), // NO REBOOT strap
|
||||
PAD_CFG_GPO(GPP_B05, 0, DEEP), // CPU_KBCRST# (test point)
|
||||
PAD_CFG_GPO(GPP_B06, 0, DEEP), // ROM_I2C_EN
|
||||
PAD_NC(GPP_B07, NONE),
|
||||
PAD_NC(GPP_B08, NONE),
|
||||
PAD_NC(GPP_B09, NONE),
|
||||
PAD_NC(GPP_B10, NONE),
|
||||
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), // HDMI_HPD
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLTRST#
|
||||
PAD_CFG_GPI(GPP_B14, NONE, DEEP), // Top swap override strap
|
||||
PAD_CFG_GPI(GPP_B15, NONE, DEEP), // GPP_B15_USB2_OC0_N
|
||||
PAD_NC(GPP_B16, NONE),
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
PAD_CFG_GPO(GPP_B18, 1, DEEP), // PCH_BT_EN
|
||||
PAD_CFG_GPO(GPP_B19, 1, DEEP), // WIFI_RF_EN
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
PAD_CFG_GPO(GPP_B21, 0, PLTRST), // TCP_RETIMER_FORCE_PWR
|
||||
PAD_NC(GPP_B22, NONE),
|
||||
PAD_NC(GPP_B23, NONE),
|
||||
|
||||
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK
|
||||
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA
|
||||
PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1), // TLS confidentiality strap
|
||||
PAD_CFG_NF(GPP_C03, UP_20K, DEEP, NF1), // SML0_CLK
|
||||
PAD_CFG_NF(GPP_C04, UP_20K, DEEP, NF1), // SML0_DATA
|
||||
PAD_CFG_NF(GPP_C05, UP_20K, DEEP, NF1), // eSPI disabled strap
|
||||
PAD_CFG_NF(GPP_C06, UP_20K, DEEP, NF1), // PMC_I2C_SCL
|
||||
PAD_CFG_NF(GPP_C07, UP_20K, DEEP, NF1), // PMC_I2C_SDA
|
||||
PAD_NC(GPP_C08, NONE),
|
||||
PAD_NC(GPP_C09, NONE),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_CFG_NF(GPP_C11, NONE, PWROK, NF1), // CPU_LAN_CLKREQ#
|
||||
PAD_CFG_NF(GPP_C12, NONE, PWROK, NF1), // CPU_CARD_CLKREQ#
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
// GPP_C14 missing
|
||||
PAD_CFG_GPO(GPP_C15, 0, DEEP), // GPP_C15_STRAP
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // TBT_LSX0_TXD
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // TBT_LSX0_RXD
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF2), // HDMI_CTRLCLK
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF2), // HDMI_CTRLDATA
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
|
||||
PAD_CFG_GPO(GPP_D00, 1, DEEP), // SB_BLON
|
||||
PAD_CFG_GPO(GPP_D01, 1, DEEP), // SSD2_PWR_EN
|
||||
PAD_CFG_GPO(GPP_D02, 1, DEEP), // M2_SSD1_RST#
|
||||
PAD_NC(GPP_D03, NONE),
|
||||
PAD_NC(GPP_D04, NONE),
|
||||
PAD_CFG_GPO(GPP_D05, 1, DEEP), // SSD1_PWR_EN
|
||||
PAD_NC(GPP_D06, NONE),
|
||||
PAD_NC(GPP_D07, NONE),
|
||||
PAD_NC(GPP_D08, NONE),
|
||||
PAD_NC(GPP_D09, NONE),
|
||||
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // HDA_BITCLK
|
||||
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), // HDA_SYNC
|
||||
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE
|
||||
PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), // HDA_SDI0
|
||||
PAD_NC(GPP_D14, NONE),
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
PAD_CFG_GPO(GPP_D16, 0, DEEP), // GPIO_SPK_MUTE
|
||||
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), // HDA_RST#
|
||||
PAD_NC(GPP_D18, NONE),
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // CPU_SSD1_CLKREQ#
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // CPU_SSD2_CLKREQ#
|
||||
PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), // CPU_WLAN_CLKREQ#
|
||||
PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1),
|
||||
|
||||
PAD_NC(GPP_E00, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_E01, 0x40100100, 0x3000), // TPM_PIRQ#
|
||||
PAD_CFG_GPI(GPP_E02, NONE, DEEP), // BOARD_ID4
|
||||
PAD_CFG_GPI(GPP_E03, NONE, DEEP), // CNVI_WAKE#
|
||||
PAD_NC(GPP_E04, NONE),
|
||||
PAD_NC(GPP_E05, NONE),
|
||||
PAD_CFG_GPO(GPP_E06, 0, DEEP), // JTAG ODT disable strap
|
||||
PAD_NC(GPP_E07, NONE),
|
||||
PAD_NC(GPP_E08, NONE),
|
||||
PAD_CFG_GPI(GPP_E09, NONE, DEEP), // GPP_E9_USB2_OC0_N
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID6
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
PAD_NC(GPP_E13, NONE),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
|
||||
PAD_NC(GPP_E15, NONE),
|
||||
PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), // VRALERT#
|
||||
PAD_CFG_GPO(GPP_E17, 0, DEEP), // BOARD_ID5
|
||||
// GPP_E18 missing
|
||||
// GPP_E19 missing
|
||||
// GPP_E20 missing
|
||||
// GPP_E21 missing
|
||||
PAD_CFG_GPO(GPP_E22, 0, DEEP), // DNX_FORCE_RELOAD
|
||||
|
||||
PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), // CNVI_BRI_DT
|
||||
PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
|
||||
PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), // CNVI_RGI_DT
|
||||
PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
|
||||
PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), // CNVI_RST#
|
||||
PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), // CNVI_CLKREQ
|
||||
PAD_CFG_GPO(GPP_F06, 0, DEEP), // CNVI_GNSS_PA_BLANKING
|
||||
PAD_NC(GPP_F07, NONE),
|
||||
PAD_NC(GPP_F08, NONE),
|
||||
PAD_CFG_GPI(GPP_F09, NONE, DEEP), // TPM_DET
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
PAD_CFG_GPO(GPP_F11, 0, DEEP), // BOARD_ID3
|
||||
PAD_NC(GPP_F12, NONE), // I2C_SCL_CODEC
|
||||
PAD_NC(GPP_F13, NONE), // I2C_SDA_CODEC
|
||||
PAD_CFG_GPO(GPP_F14, 0, DEEP), // BOARD_ID1
|
||||
PAD_CFG_GPO(GPP_F15, 0, DEEP), // BOARD_ID2
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
PAD_NC(GPP_F17, NONE),
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP), // CPU_CCD_WP#
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
PAD_CFG_GPO(GPP_F20, 0, DEEP), // SVID support strap
|
||||
PAD_NC(GPP_F21, NONE),
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
|
||||
PAD_CFG_GPO(GPP_H00, 0, DEEP), // eSPI flash sharing mode strap
|
||||
PAD_CFG_GPO(GPP_H01, 0, DEEP), // SPI flash descriptor recovery strap
|
||||
PAD_NC(GPP_H02, NONE),
|
||||
// GPP_H03 missing
|
||||
PAD_CFG_GPO(GPP_H04, 0, DEEP), // CNVI_MFUART2_RXD
|
||||
PAD_CFG_GPO(GPP_H05, 0, DEEP), // CNVI_MFUART2_TXD
|
||||
PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), // I2C3_SDA (Pantone)
|
||||
PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), // I2C3_SCL (Pantone)
|
||||
// GPP_H08 (UART0_RXD) configured in bootblock
|
||||
// GPP_H09 (UART0_TXD) configured in bootblock
|
||||
PAD_CFG_GPO(GPP_H10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H12, 0, DEEP),
|
||||
PAD_NC(GPP_H13, NONE),
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
PAD_NC(GPP_H16, NONE),
|
||||
PAD_NC(GPP_H17, NONE),
|
||||
// GPP_H18 missing
|
||||
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // I2C_SDA_TP
|
||||
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // I2C_SCL_TP
|
||||
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), // PCH_I2C_SDA
|
||||
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), // PCH_I2C_SCL
|
||||
|
||||
PAD_NC(GPP_S00, NONE),
|
||||
PAD_NC(GPP_S01, NONE),
|
||||
PAD_NC(GPP_S02, NONE), // DMIC_CLK_A1
|
||||
PAD_NC(GPP_S03, NONE), // DMIC_DATA_A1
|
||||
PAD_NC(GPP_S04, NONE),
|
||||
PAD_NC(GPP_S05, NONE),
|
||||
PAD_NC(GPP_S06, NONE),
|
||||
PAD_NC(GPP_S07, NONE),
|
||||
|
||||
PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), // PM_BATLOW#
|
||||
PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), // AC_PRESENT
|
||||
PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), // LAN_WAKEUP#
|
||||
PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), // PWR_BTN#
|
||||
PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), // SUSB#_PCH
|
||||
PAD_CFG_NF(GPP_V05, UP_20K, DEEP, NF1), // SUSC#_PCH
|
||||
PAD_CFG_NF(GPP_V06, NATIVE, DEEP, NF1), // SLP_A#
|
||||
// GPP_V07 missing
|
||||
PAD_CFG_NF(GPP_V08, UP_20K, DEEP, NF1), // SUS_CLK
|
||||
PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), // SLP_WLAN#
|
||||
PAD_NC(GPP_V10, NONE),
|
||||
PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), // LANPHYPC
|
||||
PAD_CFG_GPO(GPP_V12, 0, DEEP), // SLP_LAN#
|
||||
// GPP_V13 missing
|
||||
PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), // PCIE_WAKE#
|
||||
// GPP_V15 missing
|
||||
// GPP_V16 missing
|
||||
// GPP_V17 missing
|
||||
// GPP_V18 missing
|
||||
// GPP_V19 missing
|
||||
// GPP_V20 missing
|
||||
// GPP_V21 missing
|
||||
PAD_NC(GPP_V22, NONE),
|
||||
PAD_NC(GPP_V23, NONE),
|
||||
};
|
||||
|
||||
void mainboard_configure_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
@@ -1,16 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <mainboard/gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK
|
||||
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA
|
||||
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX
|
||||
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX
|
||||
};
|
||||
|
||||
void mainboard_configure_early_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
@@ -1,59 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC245 */
|
||||
0x10ec0245, /* Vendor ID */
|
||||
0x1558a763, /* Subsystem ID */
|
||||
40, /* Number of entries */
|
||||
//AZALIA_SUBVENDOR(0, 0x1558a763),
|
||||
AZALIA_SUBVENDOR(0, 0x1558a743),
|
||||
AZALIA_RESET(1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40789b2d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x04211020),
|
||||
|
||||
0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b,
|
||||
0x0205004a, 0x02042010, 0x02050038, 0x02047909,
|
||||
0x05c50000, 0x05c43d82, 0x05c50000, 0x05c43d82,
|
||||
0x05350000, 0x0534201a, 0x05350000, 0x0534201a,
|
||||
0x0535001d, 0x05340800, 0x0535001e, 0x05340800,
|
||||
0x05350003, 0x05341ec4, 0x05350004, 0x05340000,
|
||||
0x05450000, 0x05442000, 0x0545001d, 0x05440800,
|
||||
0x0545001e, 0x05440800, 0x05450003, 0x05441ec4,
|
||||
0x05450004, 0x05440000, 0x05350000, 0x0534a01a,
|
||||
0x0205003c, 0x0204f175, 0x0205003c, 0x0204f135,
|
||||
0x02050040, 0x02048800, 0x05a50001, 0x05a4001f,
|
||||
0x02050010, 0x02040020, 0x02050010, 0x02040020,
|
||||
0x0205006b, 0x0204a390, 0x0205006b, 0x0204a390,
|
||||
0x0205006c, 0x02040c9e, 0x0205006d, 0x02040c00,
|
||||
0x00170500, 0x00170500, 0x05a50004, 0x05a40113,
|
||||
0x02050008, 0x02046a8c, 0x02050076, 0x0204f000,
|
||||
0x0205000e, 0x020465c0, 0x02050033, 0x02048580,
|
||||
0x02050069, 0x0204fda8, 0x02050068, 0x02040000,
|
||||
0x02050003, 0x02040002, 0x02050069, 0x02040000,
|
||||
0x02050068, 0x02040001, 0x0205002e, 0x0204290e,
|
||||
0x02236100, 0x02235100, 0x00920011, 0x00970610,
|
||||
0x00936000, 0x00935000, 0x0205000d, 0x0204a020,
|
||||
0x00220011, 0x00270610, 0x0023a046, 0x00239046,
|
||||
0x0173b000, 0x01770740, 0x05a50001, 0x05a4001f,
|
||||
0x05c5000f, 0x05c40003, 0x02050036, 0x020437d7,
|
||||
0x0143b000, 0x01470740, 0x02050010, 0x02040020,
|
||||
0x01470c02, 0x01470c02,
|
||||
|
||||
// XXX: Duplicate last 2 u32s to keep in 4-dword blocks
|
||||
0x01470c02, 0x01470c02,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@@ -1,93 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/meteorlake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0xa743 inherit
|
||||
|
||||
device ref tbt_pcie_rp0 on end
|
||||
device ref tcss_xhci on end
|
||||
device ref tcss_dma0 on end
|
||||
device ref xhci on
|
||||
register "usb2_ports" = "{
|
||||
[0] = USB2_PORT_MID(OC_SKIP), /* J_AUD1 / AJ_USB3_1 */
|
||||
[1] = USB2_PORT_MID(OC_SKIP), /* J_TYPEC1 */
|
||||
[2] = USB2_PORT_MID(OC_SKIP), /* J_USB3_1 */
|
||||
[5] = USB2_PORT_MID(OC_SKIP), /* TBT */
|
||||
[6] = USB2_PORT_MID(OC_SKIP), /* Camera */
|
||||
[9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
|
||||
}"
|
||||
register "usb3_ports" = "{
|
||||
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* J_AUD1 / AJ_USB3_1 */
|
||||
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_1 */
|
||||
}"
|
||||
end
|
||||
device ref i2c0 on
|
||||
# Touchpad I2C bus
|
||||
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ELAN0412""
|
||||
register "generic.desc" = ""ELAN Touchpad""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 15 on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""FTCS1000""
|
||||
register "generic.desc" = ""FocalTech Touchpad""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 38 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp5 on
|
||||
# GLAN
|
||||
register "pcie_rp[PCH_RP(5)]" = "{
|
||||
.clk_src = 2,
|
||||
.clk_req = 2,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,
|
||||
}"
|
||||
register "pcie_clk_config_flag[2]" = "PCIE_CLK_FREE_RUNNING"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
device ref pcie_rp6 on
|
||||
# Card Reader
|
||||
register "pcie_rp[PCH_RP(6)]" = "{
|
||||
.clk_src = 3,
|
||||
.clk_req = 3,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
device ref pcie_rp8 on
|
||||
# WLAN
|
||||
register "pcie_rp[PCH_RP(8)]" = "{
|
||||
.clk_src = 5,
|
||||
.clk_req = 5,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
device ref pcie_rp10 on
|
||||
# SSD2
|
||||
# XXX: Schematics show RP[13:16] used
|
||||
register "pcie_rp[PCH_RP(10)]" = "{
|
||||
.clk_src = 8,
|
||||
.clk_req = 8,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
device ref pcie_rp11 on
|
||||
# SSD1
|
||||
# XXX: Schematics show RP[17:20] used
|
||||
register "pcie_rp[PCH_RP(11)]" = "{
|
||||
.clk_src = 7,
|
||||
.clk_req = 7,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
device ref hda on
|
||||
subsystemid 0x1558 0xa763
|
||||
end
|
||||
device ref gbe on end
|
||||
end
|
||||
end
|
||||
@@ -1,10 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
|
||||
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
|
||||
{
|
||||
// XXX: Enabling C10 reporting causes system to constantly enter and
|
||||
// exit opportunistic suspend when idle.
|
||||
params->PchEspiHostC10ReportEnable = 0;
|
||||
}
|
||||
@@ -1,25 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
const struct mb_cfg board_cfg = {
|
||||
.type = MEM_TYPE_DDR5,
|
||||
.ect = true,
|
||||
};
|
||||
const struct mem_spd spd_info = {
|
||||
.topo = MEM_TOPO_DIMM_MODULE,
|
||||
.smbus = {
|
||||
[0] = { .addr_dimm[0] = 0x50, },
|
||||
[1] = { .addr_dimm[0] = 0x52, },
|
||||
},
|
||||
};
|
||||
const bool half_populated = false;
|
||||
|
||||
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
|
||||
mupd->FspmConfig.GpioOverride = 0;
|
||||
|
||||
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
|
||||
}
|
||||
@@ -0,0 +1,68 @@
|
||||
/** @file
|
||||
Header file for Firmware Version Information
|
||||
|
||||
@copyright
|
||||
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License which accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
|
||||
#define _FIRMWARE_VERSION_INFO_HOB_H_
|
||||
|
||||
#include <Uefi/UefiMultiPhase.h>
|
||||
#include <Pi/PiBootMode.h>
|
||||
#include <Pi/PiHob.h>
|
||||
|
||||
#pragma pack(1)
|
||||
///
|
||||
/// Firmware Version Structure
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 MajorVersion;
|
||||
UINT8 MinorVersion;
|
||||
UINT8 Revision;
|
||||
UINT16 BuildNumber;
|
||||
} FIRMWARE_VERSION;
|
||||
|
||||
///
|
||||
/// Firmware Version Information Structure
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
|
||||
UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
|
||||
FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
|
||||
} FIRMWARE_VERSION_INFO;
|
||||
|
||||
#ifndef __SMBIOS_STANDARD_H__
|
||||
///
|
||||
/// The Smbios structure header.
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
UINT16 Handle;
|
||||
} SMBIOS_STRUCTURE;
|
||||
#endif
|
||||
|
||||
///
|
||||
/// Firmware Version Information HOB Structure
|
||||
///
|
||||
typedef struct {
|
||||
EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
|
||||
SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
|
||||
UINT8 Count; ///< Offset 28 Number of FVI elements included.
|
||||
///
|
||||
/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
|
||||
///
|
||||
} FIRMWARE_VERSION_INFO_HOB;
|
||||
#pragma pack()
|
||||
|
||||
#endif // _FIRMWARE_VERSION_INFO_HOB_H_
|
||||
@@ -0,0 +1,78 @@
|
||||
/** @file
|
||||
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
**/
|
||||
#ifndef _FSP_PRODUCER_DATA_HEADER_H_
|
||||
#define _FSP_PRODUCER_DATA_HEADER_H_
|
||||
|
||||
#include <Guid/FspHeaderFile.h>
|
||||
|
||||
#define BUILD_TIME_STAMP_SIZE 12
|
||||
|
||||
//
|
||||
// FSP Header Data structure from FspHeader driver.
|
||||
//
|
||||
#pragma pack(1)
|
||||
///
|
||||
/// FSP Producer Data Subtype - 1
|
||||
///
|
||||
typedef struct {
|
||||
///
|
||||
/// Byte 0x00: Length of this FSP producer data type record.
|
||||
///
|
||||
UINT16 Length;
|
||||
///
|
||||
/// Byte 0x02: FSP producer data type.
|
||||
///
|
||||
UINT8 Type;
|
||||
///
|
||||
/// Byte 0x03: Revision of this FSP producer data type.
|
||||
///
|
||||
UINT8 Revision;
|
||||
///
|
||||
/// Byte 0x04: 4 byte field of RC version which is used to build this FSP image.
|
||||
///
|
||||
UINT32 RcVersion;
|
||||
///
|
||||
/// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM".
|
||||
///
|
||||
UINT8 BuildTimeStamp[BUILD_TIME_STAMP_SIZE];
|
||||
} FSP_PRODUCER_DATA_TYPE1;
|
||||
|
||||
///
|
||||
/// FSP Producer Data Subtype - 2
|
||||
///
|
||||
typedef struct {
|
||||
///
|
||||
/// Byte 0x00: Length of this FSP producer data type record.
|
||||
///
|
||||
UINT16 Length;
|
||||
///
|
||||
/// Byte 0x02: FSP producer data type.
|
||||
///
|
||||
UINT8 Type;
|
||||
///
|
||||
/// Byte 0x03: Revision of this FSP producer data type.
|
||||
///
|
||||
UINT8 Revision;
|
||||
///
|
||||
/// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image.
|
||||
///
|
||||
UINT8 MrcVersion [4];
|
||||
} FSP_PRODUCER_DATA_TYPE2;
|
||||
|
||||
typedef struct {
|
||||
FSP_INFO_HEADER FspInfoHeader;
|
||||
FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader;
|
||||
FSP_PRODUCER_DATA_TYPE1 FspProduceDataType1;
|
||||
FSP_PRODUCER_DATA_TYPE2 FspProduceDataType2;
|
||||
FSP_PATCH_TABLE FspPatchTable;
|
||||
} FSP_PRODUCER_DATA_TABLES;
|
||||
#pragma pack()
|
||||
|
||||
#endif // _FSP_PRODUCER_DATA_HEADER_H
|
||||
48
src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspUpd.h
Normal file
48
src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspUpd.h
Normal file
@@ -0,0 +1,48 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is automatically generated. Please do NOT modify !!!
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __FSPUPD_H__
|
||||
#define __FSPUPD_H__
|
||||
|
||||
#include <FspEas.h>
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
#define FSPT_UPD_SIGNATURE 0x545F4450554C4441 /* 'ADLUPD_T' */
|
||||
|
||||
#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4441 /* 'ADLUPD_M' */
|
||||
|
||||
#define FSPS_UPD_SIGNATURE 0x535F4450554C4441 /* 'ADLUPD_S' */
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
3244
src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h
Normal file
3244
src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h
Normal file
File diff suppressed because it is too large
Load Diff
3981
src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h
Normal file
3981
src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h
Normal file
File diff suppressed because it is too large
Load Diff
320
src/vendorcode/intel/fsp/fsp2_0/alderlake_n/MemInfoHob.h
Normal file
320
src/vendorcode/intel/fsp/fsp2_0/alderlake_n/MemInfoHob.h
Normal file
@@ -0,0 +1,320 @@
|
||||
/** @file
|
||||
This file contains definitions required for creation of
|
||||
Memory S3 Save data, Memory Info data and Memory Platform
|
||||
data hobs.
|
||||
|
||||
@copyright
|
||||
Copyright (c) 1999 - 2022, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
@par Specification Reference:
|
||||
**/
|
||||
#ifndef _MEM_INFO_HOB_H_
|
||||
#define _MEM_INFO_HOB_H_
|
||||
|
||||
|
||||
#pragma pack (push, 1)
|
||||
|
||||
extern EFI_GUID gSiMemoryS3DataGuid;
|
||||
extern EFI_GUID gSiMemoryInfoDataGuid;
|
||||
extern EFI_GUID gSiMemoryPlatformDataGuid;
|
||||
|
||||
#define MAX_NODE 2
|
||||
#define MAX_CH 4
|
||||
#define MAX_DIMM 2
|
||||
// Must match definitions in
|
||||
// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
|
||||
#define HOB_MAX_SAGV_POINTS 4
|
||||
|
||||
///
|
||||
/// Host reset states from MRC.
|
||||
///
|
||||
#define WARM_BOOT 2
|
||||
|
||||
#define R_MC_CHNL_RANK_PRESENT 0x7C
|
||||
#define B_RANK0_PRS BIT0
|
||||
#define B_RANK1_PRS BIT1
|
||||
#define B_RANK2_PRS BIT4
|
||||
#define B_RANK3_PRS BIT5
|
||||
|
||||
// @todo remove and use the MdePkg\Include\Pi\PiHob.h
|
||||
#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
|
||||
#ifndef __HOB__H__
|
||||
typedef struct _EFI_HOB_GENERIC_HEADER {
|
||||
UINT16 HobType;
|
||||
UINT16 HobLength;
|
||||
UINT32 Reserved;
|
||||
} EFI_HOB_GENERIC_HEADER;
|
||||
|
||||
typedef struct _EFI_HOB_GUID_TYPE {
|
||||
EFI_HOB_GENERIC_HEADER Header;
|
||||
EFI_GUID Name;
|
||||
///
|
||||
/// Guid specific data goes here
|
||||
///
|
||||
} EFI_HOB_GUID_TYPE;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
///
|
||||
/// Defines taken from MRC so avoid having to include MrcInterface.h
|
||||
///
|
||||
|
||||
//
|
||||
// Matches MAX_SPD_SAVE define in MRC
|
||||
//
|
||||
#ifndef MAX_SPD_SAVE
|
||||
#define MAX_SPD_SAVE 29
|
||||
#endif
|
||||
|
||||
//
|
||||
// MRC version description.
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Major; ///< Major version number
|
||||
UINT8 Minor; ///< Minor version number
|
||||
UINT8 Rev; ///< Revision number
|
||||
UINT8 Build; ///< Build number
|
||||
} SiMrcVersion;
|
||||
|
||||
//
|
||||
// Matches MrcChannelSts enum in MRC
|
||||
//
|
||||
#ifndef CHANNEL_NOT_PRESENT
|
||||
#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
|
||||
#endif
|
||||
#ifndef CHANNEL_DISABLED
|
||||
#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
|
||||
#endif
|
||||
#ifndef CHANNEL_PRESENT
|
||||
#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcDimmSts enum in MRC
|
||||
//
|
||||
#ifndef DIMM_ENABLED
|
||||
#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
|
||||
#endif
|
||||
#ifndef DIMM_DISABLED
|
||||
#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
|
||||
#endif
|
||||
#ifndef DIMM_PRESENT
|
||||
#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
|
||||
#endif
|
||||
#ifndef DIMM_NOT_PRESENT
|
||||
#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcBootMode enum in MRC
|
||||
//
|
||||
#ifndef __MRC_BOOT_MODE__
|
||||
#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
|
||||
#ifndef INT32_MAX
|
||||
#define INT32_MAX (0x7FFFFFFF)
|
||||
#endif //INT32_MAX
|
||||
typedef enum {
|
||||
bmCold, ///< Cold boot
|
||||
bmWarm, ///< Warm boot
|
||||
bmS3, ///< S3 resume
|
||||
bmFast, ///< Fast boot
|
||||
MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
|
||||
MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
|
||||
} MRC_BOOT_MODE;
|
||||
#endif //__MRC_BOOT_MODE__
|
||||
|
||||
//
|
||||
// Matches MrcDdrType enum in MRC
|
||||
//
|
||||
#ifndef MRC_DDR_TYPE_DDR5
|
||||
#define MRC_DDR_TYPE_DDR5 1
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_LPDDR5
|
||||
#define MRC_DDR_TYPE_LPDDR5 2
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_LPDDR4
|
||||
#define MRC_DDR_TYPE_LPDDR4 3
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_UNKNOWN
|
||||
#define MRC_DDR_TYPE_UNKNOWN 4
|
||||
#endif
|
||||
|
||||
#define MAX_PROFILE_NUM 7 // number of memory profiles supported
|
||||
#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported
|
||||
|
||||
#define MAX_TRACE_REGION 5
|
||||
#define MAX_TRACE_CACHE_TYPE 2
|
||||
|
||||
//
|
||||
// DIMM timings
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 tCK; ///< Memory cycle time, in femtoseconds.
|
||||
UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
|
||||
UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
|
||||
UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
|
||||
UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
|
||||
UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
|
||||
UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
|
||||
UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
|
||||
UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
|
||||
UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
|
||||
UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
|
||||
UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
|
||||
UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
|
||||
UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
|
||||
UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
|
||||
UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
|
||||
UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
|
||||
UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
|
||||
UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
|
||||
} MRC_CH_TIMING;
|
||||
|
||||
typedef struct {
|
||||
UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay
|
||||
} MRC_IP_TIMING;
|
||||
|
||||
///
|
||||
/// Memory SMBIOS & OC Memory Data Hob
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
|
||||
UINT8 DimmId;
|
||||
UINT32 DimmCapacity; ///< DIMM size in MBytes.
|
||||
UINT16 MfgId;
|
||||
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
|
||||
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
|
||||
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
|
||||
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
|
||||
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
|
||||
UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
|
||||
UINT16 Speed; ///< The maximum capable speed of the device, in MHz
|
||||
UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
|
||||
} DIMM_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Status; ///< Indicates whether this channel should be used.
|
||||
UINT8 ChannelId;
|
||||
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
|
||||
MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
|
||||
DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
|
||||
} CHANNEL_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Status; ///< Indicates whether this controller should be used.
|
||||
UINT16 DeviceId; ///< The PCI device id of this memory controller.
|
||||
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
|
||||
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
|
||||
CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
|
||||
} CONTROLLER_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT64 BaseAddress; ///< Trace Base Address
|
||||
UINT64 TotalSize; ///< Total Trace Region of Same Cache type
|
||||
UINT8 CacheType; ///< Trace Cache Type
|
||||
UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
|
||||
UINT8 Rsvd[2];
|
||||
} PSMI_MEM_INFO;
|
||||
|
||||
/// This data structure contains per-SaGv timing values that are considered output by the MRC.
|
||||
typedef struct {
|
||||
UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s
|
||||
MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec
|
||||
MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific
|
||||
} HOB_SAGV_TIMING_OUT;
|
||||
|
||||
/// This data structure contains SAGV config values that are considered output by the MRC.
|
||||
typedef struct {
|
||||
UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled.
|
||||
UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point.
|
||||
HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS];
|
||||
} HOB_SAGV_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Revision;
|
||||
UINT16 DataWidth; ///< Data width, in bits, of this memory device
|
||||
/** As defined in SMBIOS 3.0 spec
|
||||
Section 7.18.2 and Table 75
|
||||
**/
|
||||
UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
|
||||
UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
|
||||
UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
|
||||
/** As defined in SMBIOS 3.0 spec
|
||||
Section 7.17.3 and Table 72
|
||||
**/
|
||||
UINT8 ErrorCorrectionType;
|
||||
|
||||
SiMrcVersion Version;
|
||||
BOOLEAN EccSupport;
|
||||
UINT8 MemoryProfile;
|
||||
UINT8 IsDMBRunning; ///< Deprecated.
|
||||
UINT32 TotalPhysicalMemorySize;
|
||||
UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
|
||||
///
|
||||
/// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported.
|
||||
/// Bit 0: XMP Profile 1 capability status
|
||||
/// Bit 1: XMP Profile 2 capability status
|
||||
/// Bit 2: XMP Profile 3 capability status
|
||||
/// Bit 3: User Profile 4 capability status
|
||||
/// Bit 4: User Profile 5 capability status
|
||||
///
|
||||
UINT8 XmpProfileEnable;
|
||||
UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed
|
||||
UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255
|
||||
UINT8 RefClk;
|
||||
UINT32 VddVoltage[MAX_PROFILE_NUM];
|
||||
UINT32 VddqVoltage[MAX_PROFILE_NUM];
|
||||
UINT32 VppVoltage[MAX_PROFILE_NUM];
|
||||
CONTROLLER_INFO Controller[MAX_NODE];
|
||||
UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255
|
||||
UINT32 NumPopulatedChannels; ///< Total number of memory channels populated
|
||||
HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC.
|
||||
UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels
|
||||
BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population
|
||||
BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config
|
||||
BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
|
||||
} MEMORY_INFO_DATA_HOB;
|
||||
|
||||
/**
|
||||
Memory Platform Data Hob
|
||||
|
||||
<b>Revision 1:</b>
|
||||
- Initial version.
|
||||
<b>Revision 2:</b>
|
||||
- Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
|
||||
**/
|
||||
typedef struct {
|
||||
UINT8 Revision;
|
||||
UINT8 Reserved[3];
|
||||
UINT32 BootMode;
|
||||
UINT32 TsegSize;
|
||||
UINT32 TsegBase;
|
||||
UINT32 PrmrrSize;
|
||||
UINT64 PrmrrBase;
|
||||
UINT32 GttBase;
|
||||
UINT32 MmioSize;
|
||||
UINT32 PciEBaseAddress;
|
||||
PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
|
||||
PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION];
|
||||
BOOLEAN MrcBasicMemoryTestPass;
|
||||
} MEMORY_PLATFORM_DATA;
|
||||
|
||||
typedef struct {
|
||||
EFI_HOB_GUID_TYPE EfiHobGuidType;
|
||||
MEMORY_PLATFORM_DATA Data;
|
||||
UINT8 *Buffer;
|
||||
} MEMORY_PLATFORM_DATA_HOB;
|
||||
|
||||
#pragma pack (pop)
|
||||
|
||||
#endif // _MEM_INFO_HOB_H_
|
||||
@@ -201,6 +201,13 @@ detect_special_flags() {
|
||||
CFLAGS_GCC="$CFLAGS_GCC -Wno-address-of-packed-member"
|
||||
testcc "$GCC" "$CFLAGS_GCC --param=min-pagesize=1024 $FLAGS_GCC" &&
|
||||
CFLAGS_GCC="$CFLAGS_GCC --param=min-pagesize=1024"
|
||||
|
||||
testcc "$GCC" "$CFLAGS_GCC -Wflex-array-member-not-at-end" &&
|
||||
CFLAGS_GCC="$CFLAGS_GCC -Wflex-array-member-not-at-end"
|
||||
|
||||
testcc "$GCC" "$CFLAGS_GCC -Wcalloc-transposed-args" &&
|
||||
CFLAGS_GCC="$CFLAGS_GCC -Wcalloc-transposed-args"
|
||||
|
||||
case "$architecture" in
|
||||
x86)
|
||||
;;
|
||||
|
||||
Reference in New Issue
Block a user