mb/system76/rpl: Enable discrete TBT device

The HX boards, using PCH-S, use a discrete Thunderbolt device (Intel
Maple Ridge), as opposed to a built-in one like the boards using PCH-P.

Fixes Thunderbolt on RPL-HX boards using the Maple Ridge controller.

Change-Id: I53d18f3ec5a084431e1113782c791bcb42728350
Signed-off-by: Tim Crawford <tcrawford@system76.com>

src/drivers/gfx/nvidia/Kconfig

@@ -1,38 +0,0 @@
-config DRIVERS_GFX_NVIDIA
-	bool
-	default n
-	help
-	  Support for NVIDIA Optimus graphics
-
-config DRIVERS_GFX_NVIDIA_BRIDGE
-	hex "PCI bridge for the GPU device"
-	default 0x01
-	depends on DRIVERS_GFX_NVIDIA
-
-config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
-	depends on DRIVERS_GFX_NVIDIA
-	bool
-	default n
-	help
-	  Support for NVIDIA Dynamic Boost
-
-config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
-	int "Total processor power offset from default TGP in watts"
-	default 45
-	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
-	help
-	  This identifies the available power for the CPU or GPU boost
-
-config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN
-	int "Minimum TGP offset from default TGP in watts"
-	default 0
-	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
-	help
-	  This is used to transfer power from the GPU to the CPU
-
-config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
-	int "Maximum TGP offset from default TGP in watts"
-	default 0
-	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
-	help
-	  This is used to transfer power from the CPU to the GPU

src/drivers/gfx/nvidia/Makefile.mk

@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
-
-ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c

src/drivers/gfx/nvidia/acpi/coffeelake.asl

@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* NVIDIA GC6 on CFL and CML CPU PCIe ports */
-
-// Memory mapped PCI express config space
-OperationRegion (PCIC, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + (CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15), 0x1000)
-
-Field (PCIC, ByteAcc, NoLock, Preserve) {
-	PVID,   16,
-	PDID,   16,
-
-	Offset (0x248),
-		,   7,
-	L23E,   1,      /* L23_Rdy Entry Request */
-	L23R,   1,      /* L23_Rdy to Detect Transition */
-
-	Offset (0xC20),
-		,   4,
-	P0AP,   2,      /* Additional power savings */
-
-	Offset (0xC38),
-		,   3,
-	P0RM,   1,      /* Robust squelch mechanism */
-}
-
-// Enter L23
-Method (DL23, 0, Serialized) {
-	Printf("      GPU PORT DL23 START")
-
-	L23E = 1
-	Sleep (16)
-	Local0 = 0
-	While (L23E) {
-		If ((Local0 > 4)) {
-			Break
-		}
-
-		Sleep (16)
-		Local0++
-	}
-
-	P0RM = 1
-	P0AP = 3
-
-	Printf("      GPU PORT DL23 FINISH")
-}
-
-// Exit L23
-Method (L23D, 0, Serialized) {
-	Printf("      GPU PORT L23D START")
-
-	L23R = 1
-	Sleep (16)
-	Local0 = 0
-	While (L23R) {
-		If ((Local0 > 4)) {
-			Break
-		}
-
-		Sleep (16)
-		Local0++
-	}
-
-	P0RM = 0
-	P0AP = 0
-
-	Printf("      GPU PORT L23D FINISH")
-}
-
-// Main power resource
-PowerResource (PWRR, 0, 0) {
-	Name (_STA, 1)
-
-	Method (_ON, 0, Serialized) {
-		Printf("GPU PORT PWRR._ON")
-
-		^^DEV0._ON()
-
-		_STA = 1
-	}
-
-	Method (_OFF, 0, Serialized) {
-		Printf("GPU PORT PWRR._OFF")
-
-		^^DEV0._OFF()
-
-		_STA = 0
-	}
-}
-
-// Power resources for entering D0
-Name (_PR0, Package () { PWRR })
-
-// Power resources for entering D3
-Name (_PR3, Package () { PWRR })
-
-#include "common/gpu.asl"

src/drivers/gfx/nvidia/acpi/common/dsm.asl

@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#define NV_ERROR_SUCCESS 0x0
-#define NV_ERROR_UNSPECIFIED 0x80000001
-#define NV_ERROR_UNSUPPORTED 0x80000002
-
-#include "gps.asl"
-#include "nvjt.asl"
-
-Method (_DSM, 4, Serialized) {
-	Printf("GPU _DSM")
-	If (Arg0 == ToUUID (JT_DSM_GUID)) {
-		If (ToInteger(Arg1) >= JT_REVISION_ID_MIN) {
-			Return (NVJT(Arg2, Arg3))
-		} Else {
-			Printf("  Unsupported JT revision: %o", SFST(Arg1))
-			Return (NV_ERROR_UNSUPPORTED)
-		}
-	} ElseIf (Arg0 == ToUUID (GPS_DSM_GUID)) {
-		If (ToInteger(Arg1) == GPS_REVISION_ID) {
-			Return (GPS(Arg2, Arg3))
-		} Else {
-			Printf("  Unsupported GPS revision: %o", SFST(Arg1))
-			Return (NV_ERROR_UNSUPPORTED)
-		}
-	} Else {
-		Printf("  Unsupported GUID: %o", IDST(Arg0))
-		Return (NV_ERROR_UNSPECIFIED)
-	}
-}

src/drivers/gfx/nvidia/acpi/common/gps.asl

@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#define GPS_DSM_GUID "A3132D01-8CDA-49BA-A52E-BC9D46DF6B81"
-#define GPS_REVISION_ID 0x00000200
-#define GPS_FUNC_SUPPORT 0x00000000
-#define GPS_FUNC_PSHARESTATUS 0x00000020
-#define GPS_FUNC_PSHAREPARAMS 0x0000002A
-
-Method(GPS, 2, Serialized) {
-	Printf("  GPU GPS")
-	Switch(ToInteger(Arg0)) {
-		Case(GPS_FUNC_SUPPORT) {
-			Printf("    Supported Functions")
-			Return(ITOB(
-				(1 << GPS_FUNC_SUPPORT) |
-				(1 << GPS_FUNC_PSHARESTATUS) |
-				(1 << GPS_FUNC_PSHAREPARAMS)
-			))
-		}
-		Case(GPS_FUNC_PSHARESTATUS) {
-			Printf("    Power Share Status")
-			Return(ITOB(0))
-		}
-		Case(GPS_FUNC_PSHAREPARAMS) {
-			Printf("    Power Share Parameters")
-
-			CreateField(Arg1, 0, 4, QTYP) // Query type
-
-			Name(GPSP, Buffer(36) { 0x00 })
-			CreateDWordField(GPSP, 0, RSTS) // Response status
-			CreateDWordField(GPSP, 4, VERS) // Version
-
-			// Set query type of response
-			RSTS = QTYP
-			// Set version of response
-			VERS = 0x00010000
-
-			Switch(ToInteger(QTYP)) {
-				Case(0) {
-					Printf("      Request Current Information")
-					// No required information
-					Return(GPSP)
-				}
-				Case(1) {
-					Printf("      Request Supported Fields")
-					// Support GPU temperature field
-					RSTS |= (1 << 8)
-					Return(GPSP)
-				}
-				Case(2) {
-					Printf("      Request Current Limits")
-					// No required limits
-					Return(GPSP)
-				}
-				Default {
-					Printf("      Unknown Query: %o", SFST(QTYP))
-					Return(NV_ERROR_UNSUPPORTED)
-				}
-			}
-		}
-		Default {
-			Printf("    Unsupported function: %o", SFST(Arg0))
-			Return(NV_ERROR_UNSUPPORTED)
-		}
-	}
-}

src/drivers/gfx/nvidia/acpi/common/gpu.asl

@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Device (DEV0) {
-	Name(_ADR, 0x00000000)
-
-	#include "utility.asl"
-	#include "dsm.asl"
-	#include "power.asl"
-}
-
-#if CONFIG(DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST)
-Scope (\_SB) {
-	Device(NPCF) {
-		#include "utility.asl"
-		#include "nvpcf.asl"
-	}
-}
-#endif

src/drivers/gfx/nvidia/acpi/common/nvjt.asl

@@ -1,152 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#define JT_DSM_GUID "CBECA351-067B-4924-9CBD-B46B00B86F34"
-#define JT_REVISION_ID_MIN 0x00000100
-#define JT_REVISION_ID_MAX 0x00000200
-#define JT_FUNC_SUPPORT 0x00000000
-#define JT_FUNC_CAPS 0x00000001
-#define JT_FUNC_POWERCONTROL 0x00000003
-
-//TODO: SMI traps and EGIN/XCLM
-#define JT_GPC_GSS 0 // Get current GPU GCx sleep status
-#define JT_GPC_EGNS 1 // Enter GC6 without self-refresh
-#define JT_GPC_EGIS 2 // Enter GC6 with self-refresh
-#define JT_GPC_XGXS 3 // Exit GC6 and stop self-refresh
-#define JT_GPC_XGIS 4 // Exit GC6 for self-refresh update
-
-#define JT_DFGC_NONE 0 // Handle request immediately
-#define JT_DFGC_DEFER 1 // Defer GPC and GPCX
-//TODO #define JT_DFGC_CLEAR 2 // Clear pending requests
-
-// Deferred GC6 enter/exit until D3-cold (saved DFGC)
-Name(DFEN, 0)
-
-// Deferred GC6 enter control (saved GPC)
-Name(DFCI, 0)
-
-// Deferred GC6 exit control (saved GPCX)
-Name(DFCO, 0)
-
-Method (NVJT, 2, Serialized) {
-	Printf("  GPU NVJT")
-	Switch (ToInteger(Arg0)) {
-		Case (JT_FUNC_SUPPORT) {
-			Printf("    Supported Functions")
-			Return(ITOB(
-				(1 << JT_FUNC_SUPPORT) |
-				(1 << JT_FUNC_CAPS) |
-				(1 << JT_FUNC_POWERCONTROL)
-			))
-		}
-		Case (JT_FUNC_CAPS) {
-			Printf("    Capabilities")
-			Return(ITOB(
-				(1 << 0) | // G-SYNC NSVR power-saving features are enabled
-				(1 << 1) | // NVSR disabled
-				(2 << 3) | // Panel power and backlight are on the suspend rail
-				(0 << 5) | // self-refresh controller remains powered while panel is powered
-				(0 << 6) | // FB is not on the suspend rail but is powered on in GC6
-				(0 << 8) | // Combined power rail for all GPUs
-				(0 << 10) | // External SPI ROM
-				(1 << 11) | // No SMI handler for kernel panic exit while in GC6
-				(0 << 12) | // Supports notify on GC6 state done
-				(1 << 13) | // Support deferred GC6
-				(1 << 14) | // Support fine-grained root port control
-				(2 << 15) | // GC6 version is GC6-R
-				(0 << 17) | // GC6 exit ISR is not supported
-				(0 << 18) | // GC6 self wakeup not supported
-				(JT_REVISION_ID_MAX << 20) // Highest revision supported
-			))
-		}
-		Case (JT_FUNC_POWERCONTROL) {
-			Printf("    Power Control: %o", SFST(Arg1))
-
-			CreateField (Arg1, 0, 3, GPC) // GPU power control
-			CreateField (Arg1, 4, 1, PPC) // Panel power control
-			CreateField (Arg1, 14, 2, DFGC) // Defer GC6 enter/exit until D3 cold
-			CreateField (Arg1, 16, 3, GPCX) // Deferred GC6 exit control
-
-			// Save deferred GC6 request
-			If ((ToInteger(GPC) != 0) || (ToInteger(DFGC) != 0)) {
-				DFEN = DFGC
-				DFCI = GPC
-				DFCO = GPCX
-			}
-
-			// Buffer to cache current state
-			Name (JTBF, Buffer (4) { 0, 0, 0, 0 })
-			CreateField (JTBF, 0, 3, CGCS) // Current GC state
-			CreateField (JTBF, 3, 1, CGPS) // Current GPU power status
-			CreateField (JTBF, 7, 1, CPSS) // Current panel and SRC state (0 when on)
-
-			// If doing deferred GC6 request, return now
-			If (ToInteger(DFGC) != 0) {
-				CGCS = 1
-				CGPS = 1
-				Return (JTBF)
-			}
-
-			// Apply requested state
-			Switch (ToInteger(GPC)) {
-				Case (JT_GPC_GSS) {
-					Printf("    Get current GPU GCx sleep status")
-					//TODO: include transitions!
-					If (GTXS(DGPU_RST_N)) {
-						// GPU powered on
-						CGCS = 1
-						CGPS = 1
-					} ElseIf (GTXS(DGPU_PWR_EN)) {
-						// GPU powered off, GC6
-						CGCS = 3
-						CGPS = 0
-					} Else {
-						// GPU powered off, D3 cold
-						CGCS = 2
-						CGPS = 0
-					}
-				}
-				Case (JT_GPC_EGNS) {
-					Printf("    Enter GC6 without self-refresh")
-					GC6I()
-					CPSS = 1
-				}
-				Case (JT_GPC_EGIS) {
-					Printf("    Enter GC6 with self-refresh")
-					GC6I()
-					If (ToInteger(PPC) == 0) {
-						CPSS = 0
-					}
-				}
-				Case (JT_GPC_XGXS) {
-					Printf("    Exit GC6 and stop self-refresh")
-					GC6O()
-
-					CGCS = 1
-					CGPS = 1
-					If (ToInteger(PPC) != 0) {
-						CPSS = 0
-					}
-				}
-				Case (JT_GPC_XGIS) {
-					Printf("    Exit GC6 for self-refresh update")
-					GC6O()
-
-					CGCS = 1
-					CGPS = 1
-					If (ToInteger(PPC) != 0) {
-						CPSS = 0
-					}
-				}
-				Default {
-					Printf("    Unsupported GPU power control: %o", SFST(GPC))
-				}
-			}
-
-			Return (JTBF)
-		}
-		Default {
-			Printf("    Unsupported function: %o", SFST(Arg0))
-			Return (NV_ERROR_UNSUPPORTED)
-		}
-	}
-}

src/drivers/gfx/nvidia/acpi/common/nvpcf.asl

@@ -1,113 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#define NVPCF_DSM_GUID "36b49710-2483-11e7-9598-0800200c9a66"
-#define NVPCF_REVISION_ID 0x00000200
-#define NVPCF_ERROR_SUCCESS 0x0
-#define NVPCF_ERROR_GENERIC 0x80000001
-#define NVPCF_ERROR_UNSUPPORTED 0x80000002
-#define NVPCF_FUNC_GET_SUPPORTED 0x00000000
-#define NVPCF_FUNC_GET_STATIC_CONFIG_TABLES 0x00000001
-#define NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS 0x00000002
-
-Name(_HID, "NVDA0820")
-
-Name(_UID, "NPCF")
-
-Method(_DSM, 4, Serialized) {
-	Printf("NVPCF _DSM")
-	If (Arg0 == ToUUID(NVPCF_DSM_GUID)) {
-		If (ToInteger(Arg1) == NVPCF_REVISION_ID) {
-			Return(NPCF(Arg2, Arg3))
-		} Else {
-			Printf("  Unsupported NVPCF revision: %o", SFST(Arg1))
-			Return(NVPCF_ERROR_GENERIC)
-		}
-	} Else {
-		Printf("  Unsupported GUID: %o", IDST(Arg0))
-		Return(NVPCF_ERROR_GENERIC)
-	}
-}
-
-Method(NPCF, 2, Serialized) {
-	Printf("  NVPCF NPCF")
-	Switch(ToInteger(Arg0)) {
-		Case(NVPCF_FUNC_GET_SUPPORTED) {
-			Printf("    Supported Functions")
-			Return(ITOB(
-				(1 << NVPCF_FUNC_GET_SUPPORTED) |
-				(1 << NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) |
-				(1 << NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS)
-			))
-		}
-		Case(NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) {
-			Printf("    Get Static Config")
-			Return(Buffer(14) {
-				// Device table header
-				0x20, 0x03, 0x01,
-				// Intel + NVIDIA
-				0x00,
-				// Controller table header
-				0x23, 0x04, 0x05, 0x01,
-				// Dynamic boost controller
-				0x01,
-				// Supports DC
-				0x01,
-				// Reserved
-				0x00, 0x00, 0x00,
-				// Checksum
-				0xAD
-			})
-		}
-		Case(NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS) {
-			Printf("    Update Dynamic Boost")
-
-			CreateField(Arg1, 0x28, 2, ICMD) // Input command
-
-			Name(PCFP, Buffer(49) {
-				// Table version
-				0x23,
-				// Table header size
-				0x05,
-				// Size of common status in bytes
-				0x10,
-				// Size of controller entry in bytes
-				0x1C,
-				// Other fields filled in later
-			})
-			CreateByteField(PCFP, 0x04, CCNT) // Controller count
-			CreateWordField(PCFP, 0x19, ATPP) // AC TPP offset
-			CreateWordField(PCFP, 0x1D, AMXP) // AC maximum TGP offset
-			CreateWordField(PCFP, 0x21, AMNP) // AC minimum TGP offset
-
-			Switch(ToInteger(ICMD)) {
-				Case(0) {
-					Printf("      Get Controller Params")
-					// Number of controllers
-					CCNT = 1
-					// AC total processor power offset from default TGP in 1/8 watt units
-					ATPP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP << 3)
-					// AC maximum TGP offset from default TGP in 1/8 watt units
-					AMXP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX << 3)
-					// AC minimum TGP offset from default TGP in 1/8 watt units
-					AMNP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN << 3)
-					Printf("PCFP: %o", SFST(PCFP))
-					Return(PCFP)
-				}
-				Case(1) {
-					Printf("      Set Controller Status")
-					//TODO
-					Printf("PCFP: %o", SFST(PCFP))
-					Return(PCFP)
-				}
-				Default {
-					Printf("      Unknown Input Command: %o", SFST(ICMD))
-					Return(NV_ERROR_UNSUPPORTED)
-				}
-			}
-		}
-		Default {
-			Printf("    Unsupported function: %o", SFST(Arg0))
-			Return(NVPCF_ERROR_UNSUPPORTED)
-		}
-	}
-}

src/drivers/gfx/nvidia/acpi/common/power.asl

@@ -1,120 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-//TODO: evaluate sleeps
-
-OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
-Field (PCIC, DwordAcc, NoLock, Preserve) {
-	Offset (0x40),
-	SSID, 32, // Subsystem vendor and product ID
-}
-
-// Enter GC6
-Method(GC6I, 0, Serialized) {
-	Printf("    GPU GC6I START")
-
-	// Enter L23
-	^^DL23()
-	Sleep(5)
-
-	// Put GPU into reset
-	Printf("      Put GPU into reset")
-	CTXS(DGPU_RST_N)
-	Sleep(5)
-
-	Printf("    GPU GC6I FINISH")
-}
-
-// Exit GC6
-Method(GC6O, 0, Serialized) {
-	Printf("    GPU GC6O START")
-
-	// Bring GPU out of reset
-	Printf("      Bring GPU out of reset")
-	STXS(DGPU_RST_N)
-	Sleep(5)
-
-	// Exit L23
-	^^L23D()
-	Sleep(5)
-
-	Printf("    GPU GC6O FINISH")
-}
-
-Method (_ON, 0, Serialized) {
-	Printf("  GPU _ON START")
-
-	If (DFEN == JT_DFGC_DEFER) {
-		Switch (ToInteger(DFCO)) {
-			Case (JT_GPC_XGXS) {
-				Printf("    Exit GC6 and stop self-refresh")
-				GC6O()
-			}
-			Default {
-				Printf("    Unsupported DFCO: %o", SFST(DFCO))
-			}
-		}
-		DFEN = JT_DFGC_NONE
-	} Else {
-		Printf("    Standard RTD3 power on")
-		STXS(DGPU_PWR_EN)
-		Sleep(5)
-		GC6O()
-	}
-
-	Printf("  GPU _ON FINISH")
-}
-
-Method (_OFF, 0, Serialized) {
-	Printf("  GPU _OFF START")
-
-	If (DFEN == JT_DFGC_DEFER) {
-		Switch (ToInteger(DFCI)) {
-			Case (JT_GPC_EGNS) {
-				Printf("    Enter GC6 without self-refresh")
-				GC6I()
-			}
-			Case (JT_GPC_EGIS) {
-				Printf("    Enter GC6 with self-refresh")
-				GC6I()
-			}
-			Default {
-				Printf("    Unsupported DFCI: %o", SFST(DFCI))
-			}
-		}
-		DFEN = JT_DFGC_NONE
-	} Else {
-		Printf("    Standard RTD3 power off")
-		GC6I()
-		CTXS(DGPU_PWR_EN)
-		Sleep(5)
-	}
-
-	Printf("  GPU _OFF FINISH")
-}
-
-// Main power resource
-PowerResource (PWRR, 0, 0) {
-	Name (_STA, 1)
-
-	Method (_ON, 0, Serialized) {
-		Printf("GPU PWRR._ON")
-
-		// Restore SSID
-		^^SSID = DGPU_SSID
-		Printf("  Restore SSID: %o", SFST(^^SSID))
-
-		_STA = 1
-	}
-
-	Method (_OFF, 0, Serialized) {
-		Printf("GPU PWRR._OFF")
-
-		_STA = 0
-	}
-}
-
-// Power resources for entering D0
-Name (_PR0, Package () { PWRR })
-
-// Power resources for entering D3
-Name (_PR3, Package () { PWRR })

src/drivers/gfx/nvidia/acpi/common/utility.asl

@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// Convert a byte to a hex string, trimming extra parts
-Method (BHEX, 1) {
-	Local0 = ToHexString(Arg0)
-	Return (Mid(Local0, SizeOf(Local0) - 2, 2))
-}
-
-// UUID to string
-Method (IDST, 1) {
-	Local0 = ""
-	Fprintf(
-		Local0,
-		"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
-		BHEX(DerefOf(Arg0[3])),
-		BHEX(DerefOf(Arg0[2])),
-		BHEX(DerefOf(Arg0[1])),
-		BHEX(DerefOf(Arg0[0])),
-		BHEX(DerefOf(Arg0[5])),
-		BHEX(DerefOf(Arg0[4])),
-		BHEX(DerefOf(Arg0[7])),
-		BHEX(DerefOf(Arg0[6])),
-		BHEX(DerefOf(Arg0[8])),
-		BHEX(DerefOf(Arg0[9])),
-		BHEX(DerefOf(Arg0[10])),
-		BHEX(DerefOf(Arg0[11])),
-		BHEX(DerefOf(Arg0[12])),
-		BHEX(DerefOf(Arg0[13])),
-		BHEX(DerefOf(Arg0[14])),
-		BHEX(DerefOf(Arg0[15]))
-	)
-	Return (Local0)
-}
-
-// Safe hex conversion, checks type first
-Method (SFST, 1) {
-	Local0 = ObjectType(Arg0)
-	If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
-		Return (ToHexString(Arg0))
-	} Else {
-		Return (Concatenate("Type: ", Arg0))
-	}
-}
-
-// Convert from 4-byte buffer to 32-bit integer
-Method (BTOI, 1) {
-	Return(
-		DerefOf(Arg0[0]) |
-		(DerefOf(Arg0[1]) << 8) |
-		(DerefOf(Arg0[2]) << 16) |
-		(DerefOf(Arg0[3]) << 24)
-	)
-}
-
-// Convert from 32-bit integer to 4-byte buffer
-Method (ITOB, 1) {
-	Local0 = Buffer(4) { 0, 0, 0, 0 }
-	Local0[0] = Arg0 & 0xFF
-	Local0[1] = (Arg0 >> 8) & 0xFF
-	Local0[2] = (Arg0 >> 16) & 0xFF
-	Local0[3] = (Arg0 >> 24) & 0xFF
-	Return (Local0)
-}

src/drivers/gfx/nvidia/acpi/tigerlake.asl

@@ -1,140 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* NVIDIA GC6 on (TGL and ADL) (CPU and PCH) PCIe ports */
-
-// Port mapped PCI express config space
-OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
-
-Field (PCIC, AnyAcc, NoLock, Preserve) {
-	Offset(0x52),  /* LSTS - Link Status Register */
-	, 13,
-	LASX, 1,       /* 0, Link Active Status */
-
-	Offset(0x60),  /* RSTS - Root Status Register */
-	, 16,
-	PSPX, 1,       /* 16,  PME Status */
-
-	Offset(0xD8),  /* 0xD8, MPC - Miscellaneous Port Configuration Register */
-	, 30,
-	HPEX, 1,       /* 30,  Hot Plug SCI Enable */
-	PMEX, 1,       /* 31,  Power Management SCI Enable */
-
-	Offset (0xE0), /* 0xE0, SPR - Scratch Pad Register */
-	SCB0, 1,       /* Scratch bit 0 */
-
-	Offset(0xE2),  /* 0xE2, RPPGEN - Root Port Power Gating Enable */
-	, 2,
-	L23E, 1,       /* 2,   L23_Rdy Entry Request (L23ER) */
-	L23R, 1,       /* 3,   L23_Rdy to Detect Transition (L23R2DT) */
-}
-
-Field (PCIC, AnyAcc, NoLock, WriteAsZeros) {
-	Offset(0xDC),  /* 0xDC, SMSCS - SMI/SCI Status Register */
-	, 30,
-	HPSX, 1,       /* 30,  Hot Plug SCI Status */
-	PMSX, 1        /* 31,  Power Management SCI Status */
-}
-
-// Enter L23
-Method (DL23, 0, Serialized) {
-	Printf("      GPU PORT DL23 START")
-
-	L23E = 1
-	Sleep (16)
-	Local0 = 0
-	While (L23E) {
-		If ((Local0 > 4)) {
-			Break
-		}
-
-		Sleep (16)
-		Local0++
-	}
-	SCB0 = 1
-
-	Printf("      GPU PORT DL23 FINISH")
-}
-
-// Exit L23
-Method (L23D, 0, Serialized) {
-	Printf("      GPU PORT L23D START")
-
-	If ((SCB0 == 1)) {
-		L23R = 1
-		Local0 = 0
-		While (L23R) {
-			If ((Local0 > 4)) {
-				Break
-			}
-			Sleep (16)
-			Local0++
-		}
-
-		SCB0 = 0
-		Local0 = 0
-		While ((LASX == 0)) {
-			If ((Local0 > 8)) {
-				Break
-			}
-			Sleep (16)
-			Local0++
-		}
-	}
-
-	Printf("      GPU PORT L23D FINISH")
-}
-
-Method (HPME, 0, Serialized) {
-	Printf("  GPU PORT HPME START")
-
-	If (PMSX == 1) {
-		Printf("    Notify GPU driver of PME SCI")
-		Notify(DEV0, 0x2)
-		Printf("    Clear PME SCI")
-		PMSX = 1
-		Printf("    Consume PME notification")
-		PSPX = 1
-	}
-
-	Printf("  GPU PORT HPME FINISH")
-}
-
-// Main power resource
-PowerResource (PWRR, 0, 0) {
-	Name (_STA, 1)
-
-	Method (_ON, 0, Serialized) {
-		Printf("GPU PORT PWRR._ON")
-
-		HPME();
-		If (PMEX == 1) {
-			Printf("  Disable power management SCI")
-			PMEX = 0
-		}
-
-		^^DEV0._ON()
-
-		_STA = 1
-	}
-
-	Method (_OFF, 0, Serialized) {
-		Printf("GPU PORT PWRR._OFF")
-
-		^^DEV0._OFF()
-
-		If (PMEX == 0) {
-			Printf("  Enable power management SCI")
-			PMEX = 1
-			HPME()
-		}
-
-		_STA = 0
-	}
-}
-
-// Power resources for entering D0
-Name (_PR0, Package () { PWRR })
-
-// Power resources for entering D3
-Name (_PR3, Package () { PWRR })
-
-#include "common/gpu.asl"

src/drivers/gfx/nvidia/chip.h

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_
-#define _DRIVERS_GFX_NVIDIA_CHIP_H_
-
-struct drivers_gfx_nvidia_config {
-	/* TODO: Set GPIOs in devicetree? */
-};
-
-#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */

src/drivers/gfx/nvidia/gpu.h

@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_
-#define _DRIVERS_GFX_NVIDIA_GPU_H_
-
-#include <stdbool.h>
-
-struct nvidia_gpu_config {
-	/* GPIO for GPU_PWR_EN */
-	unsigned int power_gpio;
-	/* GPIO for GPU_RST# */
-	unsigned int reset_gpio;
-	/* Enable or disable GPU power */
-	bool enable;
-};
-
-void nvidia_set_power(const struct nvidia_gpu_config *config);
-
-#endif /* _DRIVERS_NVIDIA_GPU_H_ */

src/drivers/gfx/nvidia/nvidia.c

@@ -1,71 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include "chip.h"
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40
-
-static void nvidia_read_resources(struct device *dev)
-{
-	printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev));
-
-	pci_dev_read_resources(dev);
-
-	// Find all BARs on GPU, mark them above 4g if prefetchable
-	for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
-		struct resource *res = probe_resource(dev, bar);
-
-		if (res) {
-			if (res->flags & IORESOURCE_PREFETCH) {
-				printk(BIOS_INFO, "  BAR at 0x%02x marked above 4g\n", bar);
-				res->flags |= IORESOURCE_ABOVE_4G;
-			} else {
-				printk(BIOS_DEBUG, "  BAR at 0x%02x not prefetch\n", bar);
-			}
-		} else {
-			printk(BIOS_DEBUG, "  BAR at 0x%02x not found\n", bar);
-		}
-	}
-}
-
-static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
-{
-	pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET,
-		((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
-static struct pci_operations nvidia_device_ops_pci = {
-	.set_subsystem = nvidia_set_subsystem,
-};
-
-static struct device_operations nvidia_device_ops = {
-	.read_resources   = nvidia_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-#if CONFIG(HAVE_ACPI_TABLES)
-	.write_acpi_tables = pci_rom_write_acpi_tables,
-	.acpi_fill_ssdt    = pci_rom_ssdt,
-#endif
-	.init             = pci_dev_init,
-	.ops_pci          = &nvidia_device_ops_pci,
-
-};
-
-static void nvidia_enable(struct device *dev)
-{
-	if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
-		return;
-
-	if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_NVIDIA)
-		return;
-
-	dev->ops = &nvidia_device_ops;
-}
-
-struct chip_operations drivers_gfx_nvidia_ops = {
-	.name = "NVIDIA Optimus Graphics Device",
-	.enable_dev = nvidia_enable
-};

src/drivers/gfx/nvidia/romstage.c

@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <gpio.h>
-#include "chip.h"
-#include "gpu.h"
-
-void nvidia_set_power(const struct nvidia_gpu_config *config)
-{
-	if (!config->power_gpio || !config->reset_gpio) {
-		printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__);
-		return;
-	}
-
-	printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio);
-	printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio);
-
-	gpio_set(config->reset_gpio, 0);
-	mdelay(10);
-
-	if (config->enable) {
-		gpio_set(config->power_gpio, 1);
-		mdelay(25);
-		gpio_set(config->reset_gpio, 1);
-	} else {
-		gpio_set(config->power_gpio, 0);
-	}
-
-	mdelay(10);
-}

src/drivers/intel/dtbt/Kconfig

@@ -0,0 +1,4 @@
+config DRIVERS_INTEL_DTBT
+	def_bool n
+	help
+	  Support for discrete Thunderbolt controllers

src/drivers/intel/dtbt/Makefile.mk

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_DRIVERS_INTEL_DTBT) += dtbt.c

src/drivers/intel/dtbt/chip.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_INTEL_DTBT_CHIP_H_
+#define _DRIVERS_INTEL_DTBT_CHIP_H_
+
+struct drivers_intel_dtbt_config {};
+
+#endif /* _DRIVERS_INTEL_DTBT_CHIP_H_ */

src/drivers/intel/dtbt/dtbt.c

@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include <acpi/acpigen.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include <device/pci_ids.h>
+#include <timer.h>
+
+#define PCIE2TBT 0x54C
+#define PCIE2TBT_VALID BIT(0)
+#define PCIE2TBT_GO2SX			2
+#define PCIE2TBT_GO2SX_NO_WAKE		3
+#define PCIE2TBT_SX_EXIT_TBT_CONNECTED	4
+#define PCIE2TBT_OS_UP			6
+#define PCIE2TBT_SET_SECURITY_LEVEL	8
+#define PCIE2TBT_GET_SECURITY_LEVEL	9
+#define PCIE2TBT_BOOT_ON		24
+#define PCIE2TBT_USB_ON			25
+#define PCIE2TBT_GET_ENUMERATION_METHOD	26
+#define PCIE2TBT_SET_ENUMERATION_METHOD	27
+#define PCIE2TBT_POWER_CYCLE		28
+#define PCIE2TBT_SX_START		29
+#define PCIE2TBT_ACL_BOOT		30
+#define PCIE2TBT_CONNECT_TOPOLOGY	31
+
+#define TBT2PCIE 0x548
+#define TBT2PCIE_DONE BIT(0)
+
+// Default timeout for mailbox commands unless otherwise specified.
+#define TIMEOUT_MS 1000
+// Default timeout for controller to ack GO2SX/GO2SX_NO_WAKE mailbox command.
+#define GO2SX_TIMEOUT_MS 600
+
+static void dtbt_cmd(struct device *dev, u32 command, u32 data, u32 timeout)
+{
+	u32 reg = (data << 8) | (command << 1) | PCIE2TBT_VALID;
+	u32 status;
+
+	printk(BIOS_DEBUG, "dTBT send command %08x\n", command);
+	pci_write_config32(dev, PCIE2TBT, reg);
+
+	if (!wait_ms(timeout, (status = pci_read_config32(dev, TBT2PCIE)) & TBT2PCIE_DONE)) {
+		printk(BIOS_ERR, "dTBT command %08x send timeout %08x\n", command, status);
+	}
+
+	pci_write_config32(dev, PCIE2TBT, 0);
+	if (!wait_ms(timeout, !(pci_read_config32(dev, TBT2PCIE) & TBT2PCIE_DONE))) {
+		printk(BIOS_ERR, "dTBT command %08x clear timeout\n", command);
+	}
+}
+
+static void dtbt_write_dsd(void)
+{
+	struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
+
+	acpi_device_add_hotplug_support_in_d3(dsd);
+	acpi_device_add_external_facing_port(dsd);
+	acpi_dp_write(dsd);
+}
+
+static void dtbt_write_opregion(const struct bus *bus)
+{
+	uintptr_t mmconf_base = (uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS
+			+ (((uintptr_t)(bus->secondary)) << 20);
+	const struct opregion opregion = OPREGION("PXCS", SYSTEMMEMORY, mmconf_base, 0x1000);
+	const struct fieldlist fieldlist[] = {
+		FIELDLIST_OFFSET(TBT2PCIE),
+		FIELDLIST_NAMESTR("TB2P", 32),
+		FIELDLIST_OFFSET(PCIE2TBT),
+		FIELDLIST_NAMESTR("P2TB", 32),
+	};
+
+	acpigen_write_opregion(&opregion);
+	acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist),
+			    FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE);
+}
+
+static void dtbt_fill_ssdt(const struct device *dev)
+{
+	struct bus *bus;
+	struct device *parent;
+	const char *parent_scope;
+	const char *dev_name = acpi_device_name(dev);
+
+	bus = dev->upstream;
+	if (!bus) {
+		printk(BIOS_ERR, "dTBT bus invalid\n");
+		return;
+	}
+
+	parent = bus->dev;
+	if (!parent || parent->path.type != DEVICE_PATH_PCI) {
+		printk(BIOS_ERR, "dTBT parent invalid\n");
+		return;
+	}
+
+	parent_scope = acpi_device_path(parent);
+	if (!parent_scope) {
+		printk(BIOS_ERR, "dTBT parent scope not valid\n");
+		return;
+	}
+
+	/* Scope */
+	acpigen_write_scope(parent_scope);
+	dtbt_write_dsd();
+
+	/* Device */
+	acpigen_write_device(dev_name);
+	acpigen_write_name_integer("_ADR", 0);
+	dtbt_write_opregion(bus);
+
+	/* Method */
+	acpigen_write_method_serialized("PTS", 0);
+
+	acpigen_write_debug_string("dTBT prepare to sleep");
+	acpigen_write_store_int_to_namestr(PCIE2TBT_GO2SX_NO_WAKE << 1, "P2TB");
+	acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", PCIE2TBT_GO2SX_NO_WAKE << 1);
+
+	acpigen_write_debug_namestr("TB2P");
+	acpigen_write_store_int_to_namestr(0, "P2TB");
+	acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", 0);
+	acpigen_write_debug_namestr("TB2P");
+
+	acpigen_write_method_end();
+	acpigen_write_device_end();
+	acpigen_write_scope_end();
+
+	printk(BIOS_DEBUG, "dTBT fill SSDT\n");
+	printk(BIOS_DEBUG, "  Dev %s\n", dev_path(dev));
+	//printk(BIOS_DEBUG, "  Bus %s\n", bus_path(bus));
+	printk(BIOS_DEBUG, "  Parent %s\n", dev_path(parent));
+	printk(BIOS_DEBUG, "  Scope %s\n", parent_scope);
+	printk(BIOS_DEBUG, "    Device %s\n", dev_name);
+
+	// \.TBTS Method
+	acpigen_write_scope("\\");
+	acpigen_write_method("TBTS", 0);
+	acpigen_emit_namestring(acpi_device_path_join(dev, "PTS"));
+	acpigen_write_method_end();
+	acpigen_write_scope_end();
+}
+
+static const char *dtbt_acpi_name(const struct device *dev)
+{
+	return "DTBT";
+}
+
+static struct pci_operations dtbt_device_ops_pci = {
+	.set_subsystem = 0,
+};
+
+static struct device_operations dtbt_device_ops = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.acpi_fill_ssdt   = dtbt_fill_ssdt,
+	.acpi_name        = dtbt_acpi_name,
+	.scan_bus         = pciexp_scan_bridge,
+	.reset_bus        = pci_bus_reset,
+	.ops_pci          = &dtbt_device_ops_pci,
+};
+
+static void dtbt_enable(struct device *dev)
+{
+	if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
+		return;
+
+	if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_INTEL)
+		return;
+
+	// TODO: check device ID
+
+	dev->ops = &dtbt_device_ops;
+
+	printk(BIOS_INFO, "dTBT controller found at %s\n", dev_path(dev));
+
+	// XXX: Recommendation is to set SL1 ("User Authorization")
+	printk(BIOS_DEBUG, "dTBT set security level SL0\n");
+	dtbt_cmd(dev, PCIE2TBT_SET_SECURITY_LEVEL, 0, TIMEOUT_MS);
+	// XXX: Must verify change or rollback all controllers
+
+	if (acpi_is_wakeup_s3()) {
+		printk(BIOS_DEBUG, "dTBT SX exit\n");
+		dtbt_cmd(dev, PCIE2TBT_SX_EXIT_TBT_CONNECTED, 0, TIMEOUT_MS);
+		// TODO: "wait for fast link bring-up" loop (timeout: 5s)
+	} else {
+		printk(BIOS_DEBUG, "dTBT boot on\n");
+		dtbt_cmd(dev, PCIE2TBT_BOOT_ON, 0, TIMEOUT_MS);
+	}
+}
+
+struct chip_operations drivers_intel_dtbt_ops = {
+	.name = "Intel Discrete Thunderbolt",
+	.enable_dev = dtbt_enable,
+};

src/mainboard/system76/addw1/Kconfig

@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
-	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC

src/mainboard/system76/addw1/Makefile.mk

@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

src/mainboard/system76/addw1/acpi/mainboard.asl

@@ -1,19 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <variant/gpio.h>
-
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
 
 Scope (\_SB) {
 	#include "sleep.asl"
-	Scope (PCI0) {
-		Device (PEGP) {
-			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
-			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
-		}
-	}
 }
 
 Scope (\_GPE) {

src/mainboard/system76/addw1/devicetree.cb

@@ -56,12 +56,6 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
-			chip drivers/gfx/nvidia
-				device pci 00.0 on end # VGA controller
-				device pci 00.1 on end # Audio device
-				device pci 00.2 on end # USB xHCI Host controller
-				device pci 00.3 on end # USB Type-C UCSI controller
-			end
 		end
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 on      # SA Thermal device

src/mainboard/system76/addw1/include/variant/gpio.h

@@ -3,16 +3,7 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_F8
-#define DGPU_PWR_EN	GPP_F9
-#define DGPU_GC6	GPP_K11
-#define DGPU_SSID	0x50151558
-
-#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
-#endif
 
 #endif

src/mainboard/system76/addw1/romstage.c

@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
-#include <variant/gpio.h>
 
 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@@ -22,17 +20,5 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
-	// Set primary display to internal graphics
-	memupd->FspmConfig.PrimaryDisplay = 0;
-
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
 }

src/mainboard/system76/addw1/variants/addw2/include/variant/gpio.h

@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_F22
-#define DGPU_PWR_EN	GPP_F23
-#define DGPU_GC6	GPP_C12
-#define DGPU_SSID	0x65e11558
-
-#ifndef __ACPI__
-void variant_configure_early_gpios(void);
-void variant_configure_gpios(void);
-#endif
-
-#endif

src/mainboard/system76/adl/Kconfig

@@ -35,12 +35,10 @@ config BOARD_SYSTEM76_GALP6
 
 config BOARD_SYSTEM76_GAZE17_3050
 	select BOARD_SYSTEM76_ADL_COMMON
-	select DRIVERS_GFX_NVIDIA
 	select EC_SYSTEM76_EC_DGPU
 
 config BOARD_SYSTEM76_GAZE17_3060_B
 	select BOARD_SYSTEM76_ADL_COMMON
-	select DRIVERS_GFX_NVIDIA
 	select EC_SYSTEM76_EC_DGPU
 	select MAINBOARD_USES_IFD_GBE_REGION
 
@@ -50,15 +48,11 @@ config BOARD_SYSTEM76_LEMP11
 
 config BOARD_SYSTEM76_ORYP9
 	select BOARD_SYSTEM76_ADL_COMMON
-	select DRIVERS_GFX_NVIDIA
-	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC_DGPU
 
 config BOARD_SYSTEM76_ORYP10
 	select BOARD_SYSTEM76_ADL_COMMON
-	select DRIVERS_GFX_NVIDIA
-	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select EC_SYSTEM76_EC_DGPU
 
 if BOARD_SYSTEM76_ADL_COMMON
@@ -109,12 +103,6 @@ config CONSOLE_POST
 config D3COLD_SUPPORT
 	default n
 
-config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
-	default 45 if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
-
-config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
-	default 25 if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
-
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
 

src/mainboard/system76/adl/Makefile.mk

@@ -2,10 +2,6 @@
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
-ifeq ($(CONFIG_DRIVERS_GFX_NVIDIA),y)
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
-endif
-
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
 

src/mainboard/system76/adl/acpi/mainboard.asl

@@ -1,9 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#if CONFIG(DRIVERS_GFX_NVIDIA)
-#include <variant/gpio.h>
-#endif
-
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
@@ -12,11 +8,5 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
-
-#if CONFIG(DRIVERS_GFX_NVIDIA)
-		Scope (PEG2) {
-			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
-		}
-#endif
 	}
 }

src/mainboard/system76/adl/variants/gaze17-3050/include/variant/gpio.h

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_B2
-#define DGPU_PWR_EN	GPP_A14
-#define DGPU_GC6	GPP_F13
-#define DGPU_SSID	0x866d1558
-
-#endif

src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb

@@ -38,10 +38,6 @@ chip soc/intel/alderlake
 				.clk_req = 3,
 				.flags = PCIE_RP_LTR,
 			}"
-			chip drivers/gfx/nvidia
-				device pci 00.0 on end # VGA controller
-				device pci 00.1 on end # Audio device
-			end
 		end
 		device ref pcie4_0 on
 			# PCIe PEG0 x4, Clock 0 (SSD2)

src/mainboard/system76/adl/variants/gaze17-3050/romstage.c

@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
-#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -19,14 +17,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/adl/variants/gaze17-3060-b/include/variant/gpio.h

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_B2
-#define DGPU_PWR_EN	GPP_A14
-#define DGPU_GC6	GPP_F13
-#define DGPU_SSID	0x867c1558
-
-#endif

src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb

@@ -38,10 +38,6 @@ chip soc/intel/alderlake
 				.clk_req = 3,
 				.flags = PCIE_RP_LTR,
 			}"
-			chip drivers/gfx/nvidia
-				device pci 00.0 on end # VGA controller
-				device pci 00.1 on end # Audio device
-			end
 		end
 		device ref igpu on
 			# DDIA is eDP

src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c

@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
-#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -19,14 +17,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/adl/variants/oryp10/include/variant/gpio.h

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_B2
-#define DGPU_PWR_EN	GPP_A14
-#define DGPU_GC6	GPP_A7
-#define DGPU_SSID	0x65f51558
-
-#endif

src/mainboard/system76/adl/variants/oryp10/overridetree.cb

@@ -23,10 +23,6 @@ chip soc/intel/alderlake
 				.clk_req = 3,
 				.flags = PCIE_RP_LTR,
 			}"
-			chip drivers/gfx/nvidia
-				device pci 00.0 on end # VGA controller
-				device pci 00.1 on end # Audio device
-			end
 		end
 		device ref igpu on
 			register "ddi_portA_config" = "1"

src/mainboard/system76/adl/variants/oryp10/romstage.c

@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
-#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -22,14 +20,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/adl/variants/oryp9/include/variant/gpio.h

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_B2
-#define DGPU_PWR_EN	GPP_A14
-#define DGPU_GC6	GPP_A7
-#define DGPU_SSID	0x65f51558
-
-#endif

src/mainboard/system76/adl/variants/oryp9/overridetree.cb

@@ -23,10 +23,6 @@ chip soc/intel/alderlake
 				.clk_req = 3,
 				.flags = PCIE_RP_LTR,
 			}"
-			chip drivers/gfx/nvidia
-				device pci 00.0 on end # VGA controller
-				device pci 00.1 on end # Audio device
-			end
 		end
 		device ref igpu on
 			register "ddi_portA_config" = "1"

src/mainboard/system76/adl/variants/oryp9/romstage.c

@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
-#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -19,14 +17,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/bonw14/Kconfig

@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
-	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_DGPU

src/mainboard/system76/bonw14/devicetree.cb

@@ -59,12 +59,11 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU)
 			register "PcieClkSrcUsage[7]" = "0x40"
 			register "PcieClkSrcClkReq[7]" = "7"
-			chip drivers/gfx/nvidia
-				device pci 00.0 on end # VGA controller
-				device pci 00.1 on end # Audio device
-				device pci 00.2 on end # USB xHCI Host controller
-				device pci 00.3 on end # USB Type-C UCSI controller
-			end
+
+			device pci 00.0 on end # VGA controller
+			device pci 00.1 on end # Audio device
+			device pci 00.2 on end # USB xHCI Host controller
+			device pci 00.3 on end # USB Type-C UCSI controller
 		end
 		# TODO: is this enough to disable iGPU?
 		device pci 02.0 off end # Integrated Graphics Device

src/mainboard/system76/gaze15/Kconfig

@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
-	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_DGPU

src/mainboard/system76/gaze15/Makefile.mk

@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

src/mainboard/system76/gaze15/acpi/mainboard.asl

@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <variant/gpio.h>
-
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
@@ -10,10 +8,6 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
-		Device (PEGP) {
-			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
-			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
-		}
 	}
 }
 

src/mainboard/system76/gaze15/devicetree.cb

@@ -55,12 +55,6 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
-			chip drivers/gfx/nvidia
-				device pci 00.0 on end # VGA controller
-				device pci 00.1 on end # Audio device
-				device pci 00.2 on end # USB xHCI Host controller
-				device pci 00.3 on end # USB Type-C UCSI controller
-			end
 		end
 		device pci 02.0 on      # Integrated Graphics Device
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"

src/mainboard/system76/gaze15/include/variant/gpio.h

@@ -3,16 +3,7 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_F8
-#define DGPU_PWR_EN	GPP_F9
-#define DGPU_GC6	GPP_K11
-#define DGPU_SSID	0x50e11558
-
-#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
-#endif
 
 #endif

src/mainboard/system76/gaze15/romstage.c

@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
-#include <variant/gpio.h>
 
 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@@ -22,17 +20,5 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
-	// Set primary display to internal graphics
-	memupd->FspmConfig.PrimaryDisplay = 0;
-
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
 }

src/mainboard/system76/gaze15/variants/gaze14/include/variant/gpio.h

@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_F22
-#define DGPU_PWR_EN	GPP_F23
-#define DGPU_GC6	GPP_K21
-#define DGPU_SSID	0x85501558
-
-#ifndef __ACPI__
-void variant_configure_early_gpios(void);
-void variant_configure_gpios(void);
-#endif
-
-#endif

src/mainboard/system76/gaze15/variants/gaze15/include/variant/gpio.h

@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_F22
-#define DGPU_PWR_EN	GPP_F23
-#define DGPU_GC6	GPP_K21
-#define DGPU_SSID	0x85201558
-
-#ifndef __ACPI__
-void variant_configure_early_gpios(void);
-void variant_configure_gpios(void);
-#endif
-
-#endif

src/mainboard/system76/oryp5/Kconfig

@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
-	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC

src/mainboard/system76/oryp5/acpi/mainboard.asl

@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <mainboard/gpio.h>
-
 #define EC_GPE_SCI 0x17 /* GPP_B23 */
 #define EC_GPE_SWI 0x26 /* GPP_G6 */
 #include <ec/system76/ec/acpi/ec.asl>
@@ -11,10 +9,6 @@ Scope (\_SB)
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
-		Device (PEGP) {
-			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
-			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
-		}
 	}
 }
 

src/mainboard/system76/oryp5/devicetree.cb

@@ -63,12 +63,6 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
-			chip drivers/gfx/nvidia
-				device pci 00.0 on end # VGA controller
-				device pci 00.1 on end # Audio device
-				device pci 00.2 on end # USB xHCI Host controller
-				device pci 00.3 on end # USB Type-C UCSI controller
-			end
 		end
 		device pci 02.0 on      # Integrated Graphics Device
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"

src/mainboard/system76/oryp5/include/mainboard/gpio.h

@@ -3,16 +3,7 @@
 #ifndef MAINBOARD_GPIO_H
 #define MAINBOARD_GPIO_H
 
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_F22
-#define DGPU_PWR_EN	GPP_F23
-#define DGPU_GC6	GPP_C12
-#define DGPU_SSID	0x95e61558
-
-#ifndef __ACPI__
 void mainboard_configure_early_gpios(void);
 void mainboard_configure_gpios(void);
-#endif
 
 #endif

src/mainboard/system76/oryp5/romstage.c

@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/gfx/nvidia/gpu.h>
-#include <mainboard/gpio.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
 
@@ -22,18 +20,6 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
-	// Set primary display to internal graphics
-	memupd->FspmConfig.PrimaryDisplay = 0;
-
 	// Allow memory speeds higher than 2666 MT/s
 	memupd->FspmConfig.SaOcSupport = 1;
 

src/mainboard/system76/oryp6/Kconfig

@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
-	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC

src/mainboard/system76/oryp6/Makefile.mk

@@ -1,7 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

src/mainboard/system76/oryp6/acpi/mainboard.asl

@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <variant/gpio.h>
-
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
@@ -10,10 +8,6 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
-		Device (PEGP) {
-			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
-			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
-		}
 	}
 }
 

src/mainboard/system76/oryp6/devicetree.cb

@@ -60,12 +60,6 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
-			chip drivers/gfx/nvidia
-				device pci 00.0 on end # VGA controller
-				device pci 00.1 on end # Audio device
-				device pci 00.2 on end # USB xHCI Host controller
-				device pci 00.3 on end # USB Type-C UCSI controller
-			end
 		end
 		device pci 02.0 on      # Integrated Graphics Device
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"

src/mainboard/system76/oryp6/include/variant/gpio.h

@@ -3,16 +3,7 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_F8
-#define DGPU_PWR_EN	GPP_F9
-#define DGPU_GC6	GPP_K11
-#define DGPU_SSID	0x65f11558
-
-#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
-#endif
 
 #endif

src/mainboard/system76/oryp6/romstage.c

@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
-#include <variant/gpio.h>
 #include <variant/romstage.h>
 
 static const struct cnl_mb_cfg memcfg = {
@@ -23,18 +21,6 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
-	// Set primary display to internal graphics
-	memupd->FspmConfig.PrimaryDisplay = 0;
-
 	variant_configure_fspm(memupd);
 
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);

src/mainboard/system76/oryp6/variants/oryp6/include/variant/gpio.h

@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_F22
-#define DGPU_PWR_EN	GPP_F23
-#define DGPU_GC6	GPP_K21
-#define DGPU_SSID	0x50d31558
-
-#ifndef __ACPI__
-void variant_configure_early_gpios(void);
-void variant_configure_gpios(void);
-#endif
-
-#endif

src/mainboard/system76/oryp6/variants/oryp7/include/variant/gpio.h

@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_F22
-#define DGPU_PWR_EN	GPP_F23
-#define DGPU_GC6	GPP_K21
-#define DGPU_SSID	0x65e51558
-
-#ifndef __ACPI__
-void variant_configure_early_gpios(void);
-void variant_configure_gpios(void);
-#endif
-
-#endif

src/mainboard/system76/rpl/Kconfig

@@ -27,8 +27,7 @@ config BOARD_SYSTEM76_RPL_COMMON
 
 config BOARD_SYSTEM76_ADDW3
 	select BOARD_SYSTEM76_RPL_COMMON
-	select DRIVERS_GFX_NVIDIA
-	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	select DRIVERS_INTEL_DTBT
 	select EC_SYSTEM76_EC_DGPU
 	select MAINBOARD_USES_IFD_GBE_REGION
 	select PCIEXP_HOTPLUG
@@ -36,16 +35,13 @@ config BOARD_SYSTEM76_ADDW3
 
 config BOARD_SYSTEM76_ADDW4
 	select BOARD_SYSTEM76_RPL_COMMON
-	select DRIVERS_GFX_NVIDIA
-	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select EC_SYSTEM76_EC_DGPU
 	select PCIEXP_HOTPLUG
 	select SOC_INTEL_ALDERLAKE_PCH_S
 
 config BOARD_SYSTEM76_BONW15
 	select BOARD_SYSTEM76_RPL_COMMON
-	select DRIVERS_GFX_NVIDIA
-	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	select DRIVERS_INTEL_DTBT
 	select EC_SYSTEM76_EC_DGPU
 	select PCIEXP_HOTPLUG
 	select SOC_INTEL_ALDERLAKE_PCH_S
@@ -62,8 +58,6 @@ config BOARD_SYSTEM76_GALP7
 
 config BOARD_SYSTEM76_GAZE18
 	select BOARD_SYSTEM76_RPL_COMMON
-	select DRIVERS_GFX_NVIDIA
-	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select EC_SYSTEM76_EC_DGPU
 	select SOC_INTEL_ALDERLAKE_PCH_P
 
@@ -75,25 +69,21 @@ config BOARD_SYSTEM76_LEMP12
 
 config BOARD_SYSTEM76_ORYP11
 	select BOARD_SYSTEM76_RPL_COMMON
-	select DRIVERS_GFX_NVIDIA
-	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select EC_SYSTEM76_EC_DGPU
 	select SOC_INTEL_ALDERLAKE_PCH_P
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 
 config BOARD_SYSTEM76_ORYP12
 	select BOARD_SYSTEM76_RPL_COMMON
-	select DRIVERS_GFX_NVIDIA
-	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select DRIVERS_I2C_TAS5825M
+	select DRIVERS_INTEL_DTBT
 	select EC_SYSTEM76_EC_DGPU
 	select PCIEXP_HOTPLUG
 	select SOC_INTEL_ALDERLAKE_PCH_S
 
 config BOARD_SYSTEM76_SERW13
 	select BOARD_SYSTEM76_RPL_COMMON
-	select DRIVERS_GFX_NVIDIA
-	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	select DRIVERS_INTEL_DTBT
 	select EC_SYSTEM76_EC_DGPU
 	select PCIEXP_HOTPLUG
 	select SOC_INTEL_ALDERLAKE_PCH_S
@@ -158,17 +148,6 @@ config CONSOLE_POST
 config D3COLD_SUPPORT
 	default n
 
-config DRIVERS_GFX_NVIDIA_BRIDGE
-	default 0x02 if BOARD_SYSTEM76_BONW15
-
-config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
-	default 45 if BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12
-	default 55 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_SERW13
-	default 80 if BOARD_SYSTEM76_BONW15
-
-config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
-	default 25 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12 || BOARD_SYSTEM76_SERW13
-
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
 

src/mainboard/system76/rpl/Makefile.mk

@@ -2,10 +2,6 @@
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
-ifeq ($(CONFIG_DRIVERS_GFX_NVIDIA),y)
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
-endif
-
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
 

src/mainboard/system76/rpl/acpi/mainboard.asl

@@ -1,9 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#if CONFIG(DRIVERS_GFX_NVIDIA)
-#include <variant/gpio.h>
-#endif
-
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
@@ -12,17 +8,5 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
-
-#if CONFIG(DRIVERS_GFX_NVIDIA)
-#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) || CONFIG(BOARD_SYSTEM76_BONW15)
-		Scope (PEG2) {
-			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
-		}
-#else
-		Scope (PEG1) {
-			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
-		}
-#endif
-#endif // CONFIG(DRIVERS_GFX_NVIDIA)
 	}
 }

src/mainboard/system76/rpl/variants/addw3/include/variant/gpio.h

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_R16
-#define DGPU_PWR_EN	GPP_F9
-#define DGPU_GC6	GPP_F8
-#define DGPU_SSID	0xa6711558
-
-#endif

src/mainboard/system76/rpl/variants/addw3/overridetree.cb

@@ -101,6 +101,9 @@ chip soc/intel/alderlake
 				.clk_req = 15,
 				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR,
 			}"
+			chip drivers/intel/dtbt
+				device pci 00.0 on end
+			end
 		end
 
 		device ref pcie_rp25 on

src/mainboard/system76/rpl/variants/addw3/romstage.c

@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
-#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -24,15 +22,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/rpl/variants/addw4/include/variant/gpio.h

@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_R16
-#define DGPU_PWR_EN	GPP_F9
-#define DGPU_SSID	0x03531558
-
-#endif

src/mainboard/system76/rpl/variants/addw4/romstage.c

@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
-#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -24,15 +22,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
 	// Set primary display to hybrid graphics
 	mupd->FspmConfig.PrimaryDisplay = 4;
 

src/mainboard/system76/rpl/variants/bonw15/include/variant/gpio.h

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_R16
-#define DGPU_PWR_EN	GPP_F22
-#define DGPU_GC6	GPP_F8
-#define DGPU_SSID	0x37021558
-
-#endif

src/mainboard/system76/rpl/variants/bonw15/overridetree.cb

@@ -97,6 +97,9 @@ chip soc/intel/alderlake
 				.clk_req = 15,
 				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR,
 			}"
+			chip drivers/intel/dtbt
+				device pci 00.0 on end
+			end
 		end
 
 		device ref pcie_rp21 on

src/mainboard/system76/rpl/variants/bonw15/romstage.c

@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
-#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -24,15 +22,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/rpl/variants/gaze18/include/variant/gpio.h

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_B2
-#define DGPU_PWR_EN	GPP_A14
-#define DGPU_GC6	GPP_F13
-#define DGPU_SSID	0x56301558
-
-#endif

src/mainboard/system76/rpl/variants/gaze18/romstage.c

@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
-#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -21,15 +19,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/rpl/variants/oryp11/include/variant/gpio.h

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_B2
-#define DGPU_PWR_EN	GPP_A14
-#define DGPU_GC6	GPP_F13
-#define DGPU_SSID	0x66a21558
-
-#endif

src/mainboard/system76/rpl/variants/oryp11/romstage.c

@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
-#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -21,15 +19,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/rpl/variants/oryp12/include/variant/gpio.h

@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_R16
-#define DGPU_PWR_EN	GPP_F9
-#define DGPU_SSID	0x66a61558
-
-#endif

src/mainboard/system76/rpl/variants/oryp12/overridetree.cb

@@ -116,6 +116,9 @@ chip soc/intel/alderlake
 				.clk_req = 15,
 				.flags = PCIE_RP_LTR | PCIE_RP_HOTPLUG,
 			}"
+			chip drivers/intel/dtbt
+				device pci 00.0 on end
+			end
 		end
 	end
 end

src/mainboard/system76/rpl/variants/oryp12/romstage.c

@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
-#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -24,15 +22,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
 	// Set primary display to hybrid graphics
 	mupd->FspmConfig.PrimaryDisplay = 4;
 

src/mainboard/system76/rpl/variants/serw13/include/variant/gpio.h

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_R16
-#define DGPU_PWR_EN	GPP_F9
-#define DGPU_GC6	GPP_A11
-#define DGPU_SSID	0xd5021558
-
-#endif

src/mainboard/system76/rpl/variants/serw13/overridetree.cb

@@ -106,6 +106,9 @@ chip soc/intel/alderlake
 				.clk_req = 15,
 				.flags = PCIE_RP_LTR | PCIE_RP_HOTPLUG, // XXX: AER causes UnsupReq warnings
 			}"
+			chip drivers/intel/dtbt
+				device pci 00.0 on end
+			end
 		end
 	end
 end

src/mainboard/system76/rpl/variants/serw13/romstage.c

@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
-#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -24,14 +22,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/tgl-h/Kconfig

@@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
-	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M if BOARD_SYSTEM76_ORYP8
 	select EC_SYSTEM76_EC

src/mainboard/system76/tgl-h/Makefile.mk

@@ -1,7 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

src/mainboard/system76/tgl-h/acpi/mainboard.asl

@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <variant/gpio.h>
-
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
@@ -10,8 +8,5 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
-		Scope (PEG1) {
-			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
-		}
 	}
 }

src/mainboard/system76/tgl-h/include/variant/gpio.h

@@ -3,16 +3,7 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_F22
-#define DGPU_PWR_EN	GPP_F23
-#define DGPU_GC6	GPP_C12
-#define DGPU_SSID	0x65d11558
-
-#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
-#endif
 
 #endif

src/mainboard/system76/tgl-h/romstage.c

@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
-#include <variant/gpio.h>
 #include <variant/romstage.h>
 
 static const struct mb_cfg board_cfg = {
@@ -23,21 +21,9 @@ static const struct mem_spd spd_info = {
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
-	const bool half_populated = false;
-
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
-	// Set primary display to internal graphics
-	mupd->FspmConfig.PrimaryDisplay = 0;
-
 	variant_memory_init_params(mupd);
 
+	const bool half_populated = false;
+
 	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
 }

src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb

@@ -6,11 +6,15 @@ chip soc/intel/tigerlake
 			# PCIe PEG2 (remapped to PEG1 by FSP) x8, Clock 0 (DGPU)
 			register "PcieClkSrcUsage[0]" = "0x42"
 			register "PcieClkSrcClkReq[0]" = "0"
-			chip drivers/gfx/nvidia
-				device pci 00.0 on end # VGA controller
-				device pci 00.1 on end # Audio device
-				device pci 00.2 on end # USB xHCI Host controller
-				device pci 00.3 on end # USB Type-C UCSI controller
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
+				register "enable_delay_ms" = "16"
+				register "enable_off_delay_ms" = "4"
+				register "reset_delay_ms" = "10"
+				register "reset_off_delay_ms" = "4"
+				register "srcclk_pin" = "0" # GFX_CLKREQ0#
+				device generic 0 on end
 			end
 		end
 		device ref igpu on

src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb

@@ -6,11 +6,15 @@ chip soc/intel/tigerlake
 			# PCIe PEG1 x16, Clock 9 (DGPU)
 			register "PcieClkSrcUsage[9]" = "0x41"
 			register "PcieClkSrcClkReq[9]" = "9"
-			chip drivers/gfx/nvidia
-				device pci 00.0 on end # VGA controller
-				device pci 00.1 on end # Audio device
-				device pci 00.2 on end # USB xHCI Host controller
-				device pci 00.3 on end # USB Type-C UCSI controller
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
+				register "enable_delay_ms" = "16"
+				register "enable_off_delay_ms" = "4"
+				register "reset_delay_ms" = "10"
+				register "reset_off_delay_ms" = "4"
+				register "srcclk_pin" = "9" # PEG_CLKREQ#
+				device generic 0 on end
 			end
 		end
 		device ref igpu on

src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb

@@ -19,11 +19,15 @@ chip soc/intel/tigerlake
 			# PCIe PEG1 x16, Clock 9 (DGPU)
 			register "PcieClkSrcUsage[9]" = "0x41"
 			register "PcieClkSrcClkReq[9]" = "9"
-			chip drivers/gfx/nvidia
-				device pci 00.0 on end # VGA controller
-				device pci 00.1 on end # Audio device
-				device pci 00.2 on end # USB xHCI Host controller
-				device pci 00.3 on end # USB Type-C UCSI controller
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
+				register "enable_delay_ms" = "16"
+				register "enable_off_delay_ms" = "4"
+				register "reset_delay_ms" = "10"
+				register "reset_off_delay_ms" = "4"
+				register "srcclk_pin" = "9" # PEG_CLKREQ#
+				device generic 0 on end
 			end
 		end
 		device ref peg0 on

src/mainboard/system76/tgl-u/Kconfig

@@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
-	select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_GALP5
 	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_USB4_RETIMER
@@ -74,15 +73,4 @@ config UART_FOR_CONSOLE
 config USE_PM_ACPI_TIMER
 	default n
 
-# For galp5 with dGPU
-if DRIVERS_GFX_NVIDIA
-
-config ONBOARD_VGA_IS_PRIMARY
-	default y
-
-config DRIVERS_GFX_NVIDIA_BRIDGE
-	default 0x1c
-
-endif # DRIVERS_GFX_NVIDIA
-
 endif

src/mainboard/system76/tgl-u/acpi/mainboard.asl

@@ -1,9 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#if CONFIG(BOARD_SYSTEM76_GALP5)
-#include <variant/gpio.h>
-#endif
-
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
@@ -12,10 +8,5 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
-#if CONFIG(BOARD_SYSTEM76_GALP5)
-		Scope (RP01) { // Remapped from RP05
-			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
-		}
-#endif
 	}
 }

src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb

@@ -144,11 +144,15 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[4]" = "1"
 			register "PcieClkSrcUsage[2]" = "4"
 			register "PcieClkSrcClkReq[2]" = "2"
-			chip drivers/gfx/nvidia
-				device pci 00.0 on end # VGA controller
-				device pci 00.1 on end # Audio device
-				device pci 00.2 on end # USB xHCI Host controller
-				device pci 00.3 on end # USB Type-C UCSI controller
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U5)" # DGPU_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_U4)" # DGPU_RST#_PCH
+				register "enable_delay_ms" = "16"
+				register "enable_off_delay_ms" = "4"
+				register "reset_delay_ms" = "10"
+				register "reset_off_delay_ms" = "4"
+				register "srcclk_pin" = "2" # PEG_CLKREQ#
+				device generic 0 on end
 			end
 		end
 		device ref pcie_rp9 on

src/mainboard/system76/tgl-u/variants/galp5/romstage.c

@@ -1,9 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <drivers/gfx/nvidia/gpu.h>
+#include <fsp/util.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
-#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -19,17 +18,5 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
-	// Set primary display to internal graphics
-	mupd->FspmConfig.PrimaryDisplay = 0;
-
 	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
 }

src/soc/intel/common/block/crashlog/crashlog.c

@@ -112,7 +112,7 @@ int cpu_cl_poll_mailbox_ready(u32 cl_mailbox_addr)
 	u16 stall_cnt = 0;
 
 	do {
-		cl_mailbox_interface.data = read32((u32 *)(uintptr_t)cl_mailbox_addr);
+		cl_mailbox_interface.data = read32((u32 *)cl_mailbox_addr);
 		udelay(CPU_CRASHLOG_WAIT_STALL);
 		stall_cnt++;
 	} while ((cl_mailbox_interface.fields.busy == 1)
@@ -140,7 +140,7 @@ int cpu_cl_mailbox_cmd(u8 cmd, u8 param)
 	cl_mailbox_intf.fields.param = param;
 	cl_mailbox_intf.fields.busy = 1;
 
-	write32((u32 *)(uintptr_t)(cl_base_addr + cl_get_cpu_mb_int_addr()),
+	write32((u32 *)(cl_base_addr + cl_get_cpu_mb_int_addr()),
 		cl_mailbox_intf.data);
 
 	cpu_cl_poll_mailbox_ready(cl_base_addr + cl_get_cpu_mb_int_addr());
@@ -167,7 +167,7 @@ int pmc_cl_gen_descriptor_table(u32 desc_table_addr,
 				pmc_crashlog_desc_table_t *descriptor_table)
 {
 	int total_data_size = 0;
-	descriptor_table->numb_regions = read32((u32 *)(uintptr_t)desc_table_addr);
+	descriptor_table->numb_regions = read32((u32 *)desc_table_addr);
 	printk(BIOS_DEBUG, "CL PMC desc table: numb of regions is 0x%x at addr 0x%x\n",
 	       descriptor_table->numb_regions, desc_table_addr);
 	for (int i = 0; i < descriptor_table->numb_regions; i++) {
@@ -178,7 +178,7 @@ int pmc_cl_gen_descriptor_table(u32 desc_table_addr,
 			break;
 		}
 		desc_table_addr += 4;
-		descriptor_table->regions[i].data = read32((u32 *)(uintptr_t)(desc_table_addr));
+		descriptor_table->regions[i].data = read32((u32 *)(desc_table_addr));
 		total_data_size += descriptor_table->regions[i].bits.size * sizeof(u32);
 		printk(BIOS_DEBUG, "CL PMC desc table: region 0x%x has size 0x%x at offset 0x%x\n",
 			i, descriptor_table->regions[i].bits.size,
@@ -295,7 +295,7 @@ bool cl_copy_data_from_sram(u32 src_bar,
 
 	u32 src_addr = src_bar + offset;
 
-	u32 data =  read32((u32 *)(uintptr_t)src_addr);
+	u32 data =  read32((u32 *)src_addr);
 
 	/* First 32bits of the record must not be 0xdeadbeef */
 	if (data == INVALID_CRASHLOG_RECORD) {
@@ -320,7 +320,7 @@ bool cl_copy_data_from_sram(u32 src_bar,
 	u32 copied = 0;
 	while (copied < size) {
 		/* DW by DW copy: byte access to PMC SRAM not allowed */
-		*dest_addr = read32((u32 *)(uintptr_t)src_addr);
+		*dest_addr = read32((u32 *)src_addr);
 		dest_addr++;
 		src_addr += 4;
 		copied++;

src/soc/intel/meteorlake/crashlog.c

@@ -34,7 +34,7 @@ static u32 disc_tab_addr;
 
 static u64 get_disc_tab_header(void)
 {
-	return read64((void *)(uintptr_t)disc_tab_addr);
+	return read64((void *)disc_tab_addr);
 }
 
 /* Get the SRAM BAR. */
@@ -338,7 +338,7 @@ static bool cpu_cl_gen_discovery_table(void)
 
 	disc_tab_addr = bar_addr + get_disc_table_offset();
 
-	u32 dw0 = read32((u32 *)(uintptr_t)disc_tab_addr);
+	u32 dw0 = read32((u32 *)disc_tab_addr);
 	if (!is_crashlog_data_valid(dw0))
 		return false;
 
@@ -351,7 +351,7 @@ static bool cpu_cl_gen_discovery_table(void)
 	for (int i = 0; i < cpu_cl_disc_tab.header.fields.count; i++) {
 		cur_offset = 8 + 24 * i;
 
-		dw0 = read32((u32 *)(uintptr_t)disc_tab_addr + cur_offset);
+		dw0 = read32((u32 *)disc_tab_addr + cur_offset);
 		if (!is_crashlog_data_valid(dw0))
 			continue;
 
@@ -361,7 +361,7 @@ static bool cpu_cl_gen_discovery_table(void)
 			break;
 		}
 
-		cpu_cl_disc_tab.buffers[i].data = read64((void *)(uintptr_t)(disc_tab_addr + cur_offset));
+		cpu_cl_disc_tab.buffers[i].data = read64((void *)(disc_tab_addr + cur_offset));
 		printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size: "
 			"0x%x offset: 0x%x\n", i,  cpu_cl_disc_tab.buffers[i].fields.size,
 			cpu_cl_disc_tab.buffers[i].fields.offset);
@@ -450,7 +450,7 @@ void cpu_cl_rearm(void)
 	cl_punit_control_interface_t punit_ctrl_intfc;
 	memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
 	punit_ctrl_intfc.fields.set_re_arm = 1;
-	write32((u32 *)(uintptr_t)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
+	write32((u32 *)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
 
 	if (!wait_and_check(CRASHLOG_RE_ARM_STATUS_MASK))
 		printk(BIOS_ERR, "CPU crashlog re_arm not asserted\n");
@@ -480,7 +480,7 @@ void cpu_cl_cleanup(void)
 	cl_punit_control_interface_t punit_ctrl_intfc;
 	memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
 	punit_ctrl_intfc.fields.set_storage_off = 1;
-	write32((u32 *)(uintptr_t)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
+	write32((u32 *)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
 
 	if (!wait_and_check(CRASHLOG_PUNIT_STORAGE_OFF_MASK))
 		printk(BIOS_ERR, "CPU crashlog storage_off not asserted\n");