c7cb5e434b
Intel chipsets from ICH7 through Lynxpoint use the same GPIO register format and thus mainboards using using these platforms have similar gpio.c files. Factor out the code to generate gpio.c from bd82x6x.go so that it other chipsets added to autoport can use it. This was originally written by Iru Cai in his Haswell autoport patch in CB:30890; I have simply split out the code to a separate commit as it is a separate logical change. TEST=Generated output is identical before and after this patch when run against logs from a Dell Latitude E6430 Change-Id: If1f506f6ad10144bd6acc42505592426bb7193b7 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83286 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
114 lines
3.0 KiB
Go
114 lines
3.0 KiB
Go
/* code to generate common GPIO code for Intel 6/7/8 Series Chipset */
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package main
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import (
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"fmt"
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"os"
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)
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func writeGPIOSet(ctx Context, sb *os.File,
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val uint32, set uint, partno int, constraint uint32) {
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max := uint(32)
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if set == 3 {
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max = 12
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}
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bits := [6][2]string{
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{"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"},
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{"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"},
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{"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"},
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{"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"},
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{"GPIO_NO_INVERT", "GPIO_INVERT"},
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{"GPIO_NO_BLINK", "GPIO_BLINK"},
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}
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for i := uint(0); i < max; i++ {
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if (constraint>>i)&1 == 1 {
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fmt.Fprintf(sb, " .gpio%d = %s,\n",
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(set-1)*32+i,
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bits[partno][(val>>i)&1])
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}
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}
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}
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func GPIO(ctx Context, inteltool InteltoolData) {
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var constraint uint32
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gpio := Create(ctx, "gpio.c")
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defer gpio.Close()
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AddBootBlockFile("gpio.c", "")
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AddROMStageFile("gpio.c", "")
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Add_gpl(gpio)
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gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n")
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addresses := [3][6]int{
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{0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18},
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{0x30, 0x34, 0x38, 0x64, -1, -1},
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{0x40, 0x44, 0x48, 0x68, -1, -1},
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}
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for set := 1; set <= 3; set++ {
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for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} {
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addr := addresses[set-1][partno]
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if addr < 0 {
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continue
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}
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fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n",
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set, set, part)
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constraint = 0xffffffff
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switch part {
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case "direction":
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/* Ignored on native mode */
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constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
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case "level":
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/* Level doesn't matter for input */
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constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
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constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
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case "reset":
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/* Only show reset */
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constraint = inteltool.GPIO[uint16(addresses[set-1][3])]
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case "invert":
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/* Only on input and only show inverted GPIO */
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constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
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constraint &= inteltool.GPIO[uint16(addresses[set-1][1])]
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constraint &= inteltool.GPIO[uint16(addresses[set-1][4])]
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case "blink":
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/* Only on output and only show blinking GPIO */
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constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
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constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
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constraint &= inteltool.GPIO[uint16(addresses[set-1][5])]
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}
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writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint)
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gpio.WriteString("};\n\n")
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}
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}
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gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = {
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.set1 = {
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.mode = &pch_gpio_set1_mode,
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.direction = &pch_gpio_set1_direction,
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.level = &pch_gpio_set1_level,
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.blink = &pch_gpio_set1_blink,
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.invert = &pch_gpio_set1_invert,
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.reset = &pch_gpio_set1_reset,
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},
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.set2 = {
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.mode = &pch_gpio_set2_mode,
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.direction = &pch_gpio_set2_direction,
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.level = &pch_gpio_set2_level,
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.reset = &pch_gpio_set2_reset,
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},
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.set3 = {
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.mode = &pch_gpio_set3_mode,
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.direction = &pch_gpio_set3_direction,
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.level = &pch_gpio_set3_level,
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.reset = &pch_gpio_set3_reset,
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},
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};
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`)
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}
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