Gerd Hoffmann 082d2a0ab7 qemu: fix IRQ routing setup
Do the setup for all PCI slots, not only the third.

Also remove the bogus message, as slot 3 may carry
any device, not only NICs.

This makes IRQ setup simliar to SeaBIOS.

SeaBIOS assignments (with patch for logging added,
and a bunch of pci devices for testing purposes):

    PCI IRQ [piix]: bdf=00:01.3 pin=1 line=10
    PCI IRQ [piix]: bdf=00:03.0 pin=1 line=11
    PCI IRQ [piix]: bdf=00:04.0 pin=1 line=11
    PCI IRQ [piix]: bdf=00:05.0 pin=1 line=10
    PCI IRQ [piix]: bdf=00:06.0 pin=1 line=10
    PCI IRQ [piix]: bdf=00:1d.0 pin=1 line=10
    PCI IRQ [piix]: bdf=00:1d.1 pin=2 line=10
    PCI IRQ [piix]: bdf=00:1d.2 pin=3 line=11
    PCI IRQ [piix]: bdf=00:1d.7 pin=4 line=11

Coreboot assignments without this patch:

    Assigning IRQ 11 to 0:3.0

Coreboot assignments with this patch:

    Assigning IRQ 10 to 0:1.3
    Assigning IRQ 11 to 0:3.0
    Assigning IRQ 11 to 0:4.0
    Assigning IRQ 10 to 0:5.0
    Assigning IRQ 10 to 0:6.0
    Assigning IRQ 10 to 0:1d.0
    Assigning IRQ 10 to 0:1d.1
    Assigning IRQ 11 to 0:1d.2
    Assigning IRQ 11 to 0:1d.7

Change-Id: Ie96be39185f2f1cbde3c9fc50e29faff59c28493
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3334
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-05 12:49:00 +02:00
2013-06-05 12:49:00 +02:00
2013-01-10 22:51:20 +01:00
2012-11-01 23:13:39 +01:00
2006-08-12 22:03:36 +00:00

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.

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