96ecb77905
Apollo Lake uses yet another descriptor format where only two masters are used: CPU/BIOS and CSE/TXE. CSE stores data in a region number 5 that has not been used previously and CPU must not write it. Add quirk (-p aplk) that locks descriptor according to recommended values. BUG=chrome-os-partner:58974 TEST=ifdtool -p aplk -l bios.bin; ifdtool -d bios.bin.new. Make sure FLMSTR1 and FLMSTR2 are set correctly. unlock with -l and make sure FLMSTRs are restored. Change-Id: I3f33372bef3ff75d0e34030694c79cd07d5540de Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17202 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
146 lines
2.9 KiB
C
146 lines
2.9 KiB
C
/*
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* ifdtool - dump Intel Firmware Descriptor information
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*
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#define IFDTOOL_VERSION "1.2"
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enum ifd_version {
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IFD_VERSION_1,
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IFD_VERSION_2,
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};
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enum platform {
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PLATFORM_APOLLOLAKE
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};
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#define LAYOUT_LINELEN 80
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enum spi_frequency {
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SPI_FREQUENCY_20MHZ = 0,
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SPI_FREQUENCY_33MHZ = 1,
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SPI_FREQUENCY_48MHZ = 2,
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SPI_FREQUENCY_50MHZ_30MHZ = 4,
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SPI_FREQUENCY_17MHZ = 6,
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};
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enum component_density {
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COMPONENT_DENSITY_512KB = 0,
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COMPONENT_DENSITY_1MB = 1,
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COMPONENT_DENSITY_2MB = 2,
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COMPONENT_DENSITY_4MB = 3,
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COMPONENT_DENSITY_8MB = 4,
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COMPONENT_DENSITY_16MB = 5,
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COMPONENT_DENSITY_32MB = 6,
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COMPONENT_DENSITY_64MB = 7,
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COMPONENT_DENSITY_UNUSED = 0xf
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};
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// flash descriptor
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typedef struct {
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uint32_t flvalsig;
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uint32_t flmap0;
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uint32_t flmap1;
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uint32_t flmap2;
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uint8_t reserved[0xefc - 0x20];
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uint32_t flumap1;
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} __attribute__((packed)) fdbar_t;
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// regions
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#define MAX_REGIONS 9
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#define MAX_REGIONS_OLD 5
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typedef struct {
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uint32_t flreg0;
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uint32_t flreg1;
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uint32_t flreg2;
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uint32_t flreg3;
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uint32_t flreg4;
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uint32_t flreg5;
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uint32_t flreg6;
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uint32_t flreg7;
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uint32_t flreg8;
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} __attribute__((packed)) frba_t;
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// component section
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typedef struct {
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uint32_t flcomp;
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uint32_t flill;
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uint32_t flpb;
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} __attribute__((packed)) fcba_t;
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// pch strap
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typedef struct {
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uint32_t pchstrp0;
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uint32_t pchstrp1;
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uint32_t pchstrp2;
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uint32_t pchstrp3;
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uint32_t pchstrp4;
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uint32_t pchstrp5;
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uint32_t pchstrp6;
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uint32_t pchstrp7;
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uint32_t pchstrp8;
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uint32_t pchstrp9;
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uint32_t pchstrp10;
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uint32_t pchstrp11;
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uint32_t pchstrp12;
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uint32_t pchstrp13;
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uint32_t pchstrp14;
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uint32_t pchstrp15;
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uint32_t pchstrp16;
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uint32_t pchstrp17;
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} __attribute__((packed)) fpsba_t;
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/*
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* WR / RD bits start at different locations within the flmstr regs, but
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* otherwise have identical meaning.
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*/
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#define FLMSTR_WR_SHIFT_V1 24
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#define FLMSTR_WR_SHIFT_V2 20
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#define FLMSTR_RD_SHIFT_V1 16
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#define FLMSTR_RD_SHIFT_V2 8
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// master
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typedef struct {
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uint32_t flmstr1;
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uint32_t flmstr2;
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uint32_t flmstr3;
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uint32_t flmstr4;
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uint32_t flmstr5;
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} __attribute__((packed)) fmba_t;
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// processor strap
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typedef struct {
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uint32_t data[8];
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} __attribute__((packed)) fmsba_t;
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// ME VSCC
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typedef struct {
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uint32_t jid;
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uint32_t vscc;
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} vscc_t;
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typedef struct {
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// Actual number of entries specified in vtl
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vscc_t entry[8];
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} vtba_t;
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typedef struct {
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int base, limit, size;
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} region_t;
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struct region_name {
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char *pretty;
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char *terse;
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};
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