904538bcc1
According to datasheets for Intel ICH/PCH, it works for chipsets from ICH7 to 9-series PCH, with PCI device address D31:F2. Change-Id: If1ddd7208108bda949b5a94894a7bf9e8bfe1e5f Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/15106 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
78 lines
2.1 KiB
C
78 lines
2.1 KiB
C
/*
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* ahci.c: dump AHCI registers
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*
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* Copyright (C) 2016 Iru Cai
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the
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* License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <inttypes.h>
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#include "inteltool.h"
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#define NUM_SATA_PORTS 6
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#define MMIO_SIZE 0x400
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static const char *ghc_regs[] = {
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"CAP", "GHC", "IS", "PI",
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"VS", "CCC_CTL", "CCC_PORTS", "EM_LOC",
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"EM_CTL", "CAP2", "BOHC"
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};
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static const char *port_ctl_regs[] = {
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"PxCLB", "PxCLBU", "PxFB", "PxFBU",
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"PxIS", "PxIE", "PxCMD", "Reserved",
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"PxTFD", "PxSIG", "PxSSTS", "PxSCTL",
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"PxSERR", "PxSACT", "PxCI", "PxSNTF",
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"PxFBS", "PxDEVSLP", "Reserved"
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};
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#define NUM_GHC (sizeof(ghc_regs)/sizeof(ghc_regs[0]))
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#define NUM_PORTCTL (sizeof(port_ctl_regs)/sizeof(port_ctl_regs[0]))
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int print_ahci(struct pci_dev *ahci)
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{
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uint64_t mmio_phys;
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uint8_t *mmio;
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uint32_t i, j;
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if (!ahci) {
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puts("No SATA device found");
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return 0;
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}
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printf("\n============= AHCI Registers ==============\n\n");
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mmio_phys = ahci->base_addr[5] & ~0x7ULL;
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printf("ABAR = 0x%08llx (MEM)\n\n", (unsigned long long)mmio_phys);
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mmio = map_physical(mmio_phys, MMIO_SIZE);
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if (mmio == NULL) {
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perror("Error mapping MMIO");
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exit(1);
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}
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puts("Generic Host Control Registers:");
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for (i = 0; i < 0x100; i += 4) {
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printf("0x%02x: 0x%08x (%s)\n", i, *(uint32_t *)(mmio + i),
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(i / 4 < NUM_GHC) ? ghc_regs[i / 4]:"Reserved");
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}
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for (i = 0; i < NUM_SATA_PORTS; i++) {
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printf("\nPort %d Control Registers:\n", i);
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uint8_t *mmio_port = mmio + 0x100 + i * 0x80;
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for (j = 0; j < 0x80; j += 4) {
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printf("0x%03x: 0x%08x (%s)\n", 0x100+i*0x80+j, *(uint32_t *)(mmio_port + j),
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(j / 4 < NUM_PORTCTL) ? port_ctl_regs[j / 4]:"Reserved");
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}
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}
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unmap_physical((void *)mmio, MMIO_SIZE);
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return 0;
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}
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