system76-coreboot

Files

Jeremy Compostella 117770d324 soc/intel/alderlake: Enable Energy/Performance Bias control

According to document 619503 ADL EDS Vol2, bit 18 of MSR_POWER_CTL
must be set to be able to set the Energy/Performance Bias using MSR
IA32_ENERGY_PERF_BIAS.

Note that since this bit was not set until this patch, the
`set_energy_perf_bias(ENERGY_POLICY_NORMAL);' call in
`soc_core_init()` was systematically failing.

BRANCH=firmware-brya-14505.B
BUG=b:239853069
TEST=verify that EPB is set by coreboot

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ic24abdd7f63f4707b8996da4755a26be148efe4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

2022-07-28 14:57:54 +00:00

amd

soc/amd/sabrina: Disable CCP DMA and HW MODEXP

2022-07-27 13:41:30 +00:00

cavium

soc/cavium,ti: Do resource transition

2022-06-29 11:55:01 +00:00

example/min86

src/soc: Get rid of most src/soc/Kconfig files

2022-06-24 03:59:36 +00:00

intel

soc/intel/alderlake: Enable Energy/Performance Bias control