treewide: Unify Google branding
Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Jon Murphy
Felix Held
parent
dc86804a7d
commit
c4e90454f4
@ -185,7 +185,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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Unit**](http://en.wikipedia.org/wiki/Central_processing_unit)
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* CPUID - x86: [**CPU Identification**](https://en.wikipedia.org/wiki/CPUID) opcode
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* Cr50 - Google: The first generation Google Security Chip (GSC) used on
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Chrome OS devices.
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ChromeOS devices.
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* CRB - Customer Reference Board
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* CRLF - Carriage Return, Line Feed - \\r\\n - The standard window EOL
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(End-of-Line) marker.
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@ -914,7 +914,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
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* TGL - Intel: Tigerlake
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* THC - Touch Host Controller
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* Ti50 - Google: The next generation GSC (Google Security chip) on
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Chrome OS devices after Cr50
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ChromeOS devices after Cr50
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* TLA - Techtronics Logic Analyzer
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* TLA - Three Letter Acronym
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* TLB - [**Translation Lookside
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@ -4,7 +4,7 @@
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[Flashmap](https://code.google.com/p/flashmap) (FMAP) is a binary format to
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describe partitions in a flash chip. It was added to coreboot to support the
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requirements of Chromium OS firmware but then was also used in other scenarios
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requirements of ChromiumOS firmware but then was also used in other scenarios
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where precise placement of data in flash was necessary, or for data that is
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written to at runtime, as CBFS is considered too fragile for such situations.
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The Flashmap implementation inside coreboot is the de facto standard today.
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@ -8,8 +8,8 @@ BIOS image to be used across a wide variety of devices which may have key differ
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otherwise similar enough to use the same coreboot build target.
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The initial implementation is designed to take advantage of a bitmask returned by the Embedded
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Controller on Google Chrome OS devices which allows the manufacturer to use the same firmware
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image across multiple devices by selecting various options at runtime. See the Chromium OS
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Controller on Google ChromeOS devices which allows the manufacturer to use the same firmware
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image across multiple devices by selecting various options at runtime. See the ChromiumOS
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[Firmware Config][1] documentation for more information.
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This firmware configuration interface differs from the CMOS option interface in that this
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@ -91,7 +91,7 @@ file in CBFS use the value it contains when matching fields and options.
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### Embedded Controller
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Google Chrome OS devices support an Embedded Controller interface for reading and writing the
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Google ChromeOS devices support an Embedded Controller interface for reading and writing the
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firmware configuration value, along with other board-specific information. It is possible for
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coreboot to read this value at boot on systems that support this feature.
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@ -101,9 +101,9 @@ possible by enabling the CBFS source and coreboot will look in CBFS first for a
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before asking the embedded controller.
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It is also possible to adjust the value in the embedded controller *(after disabling write
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protection)* with the `ectool` command in a Chrome OS environment.
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protection)* with the `ectool` command in a ChromeOS environment.
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For more information on the firmware configuration field on Chrome OS devices see the Chromium
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For more information on the firmware configuration field on ChromeOS devices see the Chromium
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documentation for [Firmware Config][1] and [Board Info][2].
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[1]: http://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/firmware_config.md
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@ -3,7 +3,7 @@
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All Haswell boards supported by coreboot currently require a proprietary
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blob in order to initialise the DRAM and a few other components. The
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blob, named `mrc.bin`, largely consists of Intel's memory reference code
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(MRC), but it has been tailored specifically for Chrome OS. It is just
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(MRC), but it has been tailored specifically for ChromeOS. It is just
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under 200 KiB in size. Another name for `mrc.bin` is the system agent
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binary.
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@ -328,7 +328,7 @@ Google's Chromebooks have some special features:
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### Developer Mode
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Developer mode allows the user to use coreboot to boot another operating system.
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This may be a another (beta) version of Chrome OS, or another flavor of
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This may be a another (beta) version of ChromeOS, or another flavor of
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GNU/Linux. Use of developer mode does not void the system warranty. Upon entry
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into developer mode, all locally saved data on the system is lost.
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This prevents someone from entering developer mode to subvert the system
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@ -8,7 +8,7 @@ power transition flows.
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## Problem Statement
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Currently, on Chromium OS Systems, CSE region is not updatable. So, new CSE FW
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Currently, on ChromiumOS Systems, CSE region is not updatable. So, new CSE FW
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versions that are released by Intel to address important functional and security
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bugs post-product launch will not be available to the end-user. Hence, the proposed
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solution allows in-field CSE FW update to propagate those bug fixes
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@ -3,7 +3,7 @@ Rebuilding coreboot image generation
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Current situation
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-----------------
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Chrome OS (CrOS) probably has the most complex image bundling process in the
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ChromeOS (CrOS) probably has the most complex image bundling process in the
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coreboot ecosystem. To make CrOS features more accessible to the wider
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coreboot community, we want to move these capabilities into upstream
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coreboot’s build system.
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@ -21,7 +21,7 @@ putting more data (eg. the bitmap data, keys) as raw data into other fmap
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regions.
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With the recent addition of more files to CBFS, both on the coreboot side
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(dsdt, FSP, and so on) and with Chrome OS specifics (eg. more files describing
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(dsdt, FSP, and so on) and with ChromeOS specifics (eg. more files describing
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boot screens) we either need to expand the scope of bundle\_firmware or move
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the capability to build complex images to upstream coreboot’s build system.
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This document proposes to do the latter and outlines how this could be
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@ -41,14 +41,14 @@ images:
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variable to guarantee success if there’s enough room for the files. While that
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could be added, that becomes more make macro work indistinguishable from magic
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that people fail to understand, break and with good reason complain about
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to work around such issues, Chrome OS firmware uses a custom tool with even
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to work around such issues, ChromeOS firmware uses a custom tool with even
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more special cases to finally build the image it needs. If coreboot upstream
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is to support vboot, it should also be powerful enough not to need magic tools
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that only live within downstream projects.
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Requirements
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------------
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A complete Chrome OS coreboot image consists of (depending on the device)
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A complete ChromeOS coreboot image consists of (depending on the device)
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* platform specific data in raw fmap regions (eg IFD, ME firmware),
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* the bootblock (coming from the bootblock),
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* three copies of coreboot, consisting of the stages (verstage, romstage,
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@ -68,7 +68,7 @@ using a yet to be implemented switching scheme based on fmaps) consists of
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* payload plus data (with each of the coreboot copies),
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Since a single platform is potentially built with different payload
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configurations (eg. modding a Chromebook to not use the verified Chrome OS
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configurations (eg. modding a Chromebook to not use the verified ChromeOS
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boot scheme), some concerns need to be kept separate:
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* Platform requirements that have nothing to do with the payload or boot schemes
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* IFD, ME, … need to copied to the right place
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@ -111,11 +111,11 @@ Boot method manifest
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--------------------
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The boot method manifest can subdivide the BIOS region, eg. using it directly
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(for coreboot’s “simple” bootblock), splitting it in two (for coreboot’s
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fallback/normal) or in many parts (for Chrome OS, which requires two CBFS
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fallback/normal) or in many parts (for ChromeOS, which requires two CBFS
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regions, one for GBB, several for VPD, …).
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It also specifies which of the file lists specified earlier belong in which
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region (eg. with verstage verifying romstage, verstage needs to be only in
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Chrome OS’ RO region, while romstage belongs in RO and both RW regions).
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ChromeOS’ RO region, while romstage belongs in RO and both RW regions).
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It can also specify a post processing step that is executed before the
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chipset’s.
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@ -148,7 +148,7 @@ It specifies an IFD region, an ME, and the BIOS region. After the image is
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built, the entire image needs to be processed (although the tool likely works
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only on a small part of it)
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It’s built in a Chrome OS-like configuration (simplified at places to avoid
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It’s built in a ChromeOS-like configuration (simplified at places to avoid
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distracting from the important parts), so it has three CBFS regions, and
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several data regions for its own purpose (similar to GBB, FWID, VPD, …). After
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the regions are filled, one data region must be post-processed to contain
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@ -47,9 +47,9 @@ file `Python`
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* _rmodtool_ - Creates rmodules `C`
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* _ifwitool_ - For manipulating IFWI `C`
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* __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C`
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* __chromeos__ - These scripts can be used to access Chrome OS
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* __chromeos__ - These scripts can be used to access ChromeOS
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resources, for example to extract System Agent reference code and other
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blobs (e.g. mrc.bin, refcode, VGA option roms) from a Chrome OS
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blobs (e.g. mrc.bin, refcode, VGA option roms) from a ChromeOS
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recovery image. `C`
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* __crossgcc__ - A cross toolchain builder for -elf toolchains (ie. no
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libc support) `Bash`
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@ -29,7 +29,7 @@ way to categorize anything required by the SoC but not provided by coreboot.
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+------------+------------------+-----------+-------------------------------------------+
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| 4 | Platform Data | SI_PDR | |
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+------------+------------------+-----------+-------------------------------------------+
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| 8 | EC Firmware | SI_EC | Most Chrome OS devices do not use this |
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| 8 | EC Firmware | SI_EC | Most ChromeOS devices do not use this |
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| | | | region; EC firmware is stored in BIOS |
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| | | | region of flash |
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+------------+------------------+-----------+-------------------------------------------+
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@ -7,17 +7,17 @@ Copyright © 2012 Intel Corporation
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Copyright 2012 Red Hat Inc.
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Copyright 2013 Google Inc.
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Copyright 2014 Google Inc.
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Copyright 2014 The Chromium OS Authors. All rights reserved.
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Copyright 2014 The ChromiumOS Authors. All rights reserved.
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Copyright 2015 Google Inc.
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Copyright 2015, Google Inc.
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Copyright 2016 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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Copyright 2016 The Chromium OS Authors. All rights reserved.
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Copyright 2016 The ChromiumOS Authors. All rights reserved.
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Copyright 2017-2019 Eltan B.V.
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Copyright 2017 Google Inc.
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Copyright 2018 Generated Code
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Copyright 2018-present Facebook, Inc.
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Copyright 2019 9Elements Agency GmbH <patrick.rudolph@9elements.com>
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Copyright 2019 The Chromium OS Authors. All rights reserved.
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Copyright 2019 The ChromiumOS Authors. All rights reserved.
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Copyright (C) 2002 David S. Peterson. All rights reserved.
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Copyright (c) 2003-2016 Cavium Inc. (support@cavium.com). All rights
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Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights
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@ -35,7 +35,7 @@ Copyright (c) 2010-2017, The Regents of the University of California
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Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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Copyright (C) 2010 coresystems GmbH
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Copyright (c) 2010 Per Odlund <per.odlund@armagedon.se>
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Copyright (c) 2010 The Chromium OS Authors. All rights reserved.
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Copyright (c) 2010 The ChromiumOS Authors. All rights reserved.
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Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
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Copyright (c) 2011-2012 The Linux Foundation. All rights reserved.
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Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
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@ -52,14 +52,14 @@ Copyright (c) 2012, 2016-2019 Advanced Micro Devices, Inc.
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Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.
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Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.*
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Copyright (c) 2012, Code Aurora Forum. All rights reserved.
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Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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Copyright (c) 2012 The ChromiumOS Authors. All rights reserved.
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Copyright (c) 2012 The Linux Foundation. All rights reserved.
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Copyright (c) 2012 The Linux Foundation. All rights reserved.*
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Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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Copyright (c) 2013-2015 Intel Corporation.
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Copyright (c) 2013-2017 Intel Corporation.
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Copyright (C) 2013 Google Inc.
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Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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Copyright (c) 2013 The ChromiumOS Authors. All rights reserved.
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Copyright (c) 2013 The Linux Foundation. All rights reserved.
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Copyright (c) 2013, The Regents of the University of California (Regents).
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Copyright (C) 2014 - 2015, 2019 The Linux Foundation. All rights reserved.
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@ -69,14 +69,14 @@ Copyright (C) 2014 - 2016 The Linux Foundation. All rights reserved.
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Copyright (c) 2014 Google Inc.
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Copyright (C) 2014 Google Inc.
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Copyright (c) 2014 Google Inc. All rights reserved.
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Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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Copyright (c) 2014 The ChromiumOS Authors. All rights reserved.
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Copyright (C) 2014 The Linux Foundation. All rights reserved.
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Copyright (C) 2015-2016 Intel Corporation.
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Copyright (C) 2015-2016, Intel Corporation
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Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
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Copyright (C) 2015 Google Inc.
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Copyright (c) 2015, Intel Corporation. All rights reserved.
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Copyright (c) 2015 The Chromium OS Authors. All rights reserved.
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Copyright (c) 2015 The ChromiumOS Authors. All rights reserved.
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Copyright (C) 2015 The Linux Foundation. All rights reserved.
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Copyright (c) 2015, The Linux Foundation. All rights reserved.
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Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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@ -7,7 +7,7 @@ CONFIG_SPI_FLASH_SMM=y
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CONFIG_USE_BLOBS=y
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CONFIG_ANY_TOOLCHAIN=y
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# Chrome OS
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# ChromeOS
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CONFIG_CHROMEOS=y
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CONFIG_HAS_RECOVERY_MRC_CACHE=y
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CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN=y
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@ -56,10 +56,10 @@ config DEVELOPER
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libpayload developers.
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config CHROMEOS
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bool "Chrome OS Options"
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bool "ChromeOS Options"
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default n
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help
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Select configuration defaults appropriate for Chrome OS boards.
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Select configuration defaults appropriate for ChromeOS boards.
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choice
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prompt "Compiler to use"
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@ -1,6 +1,6 @@
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/*
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* Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc.
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* Copyright (c) 2011 The Chromium OS Authors.
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* Copyright (c) 2011 The ChromiumOS Authors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014 Chromium OS authors
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* Copyright (c) 2014 ChromiumOS authors
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*/
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#include <libpayload.h>
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@ -1,6 +1,6 @@
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/*
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*
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* Copyright (c) 2012 The Chromium OS Authors.
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* Copyright (c) 2012 The ChromiumOS Authors.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -1,6 +1,6 @@
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/*
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*
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* Copyright (c) 2012 The Chromium OS Authors.
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* Copyright (c) 2012 The ChromiumOS Authors.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -3,7 +3,7 @@
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#include <acpi/acpigen_extern.asl>
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#if CONFIG(CHROMEOS_NVS)
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/* Chrome OS specific */
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/* ChromeOS specific */
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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#endif
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@ -203,7 +203,7 @@ struct elog_event_data_wake {
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uint32_t instance;
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} __packed;
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/* Chrome OS related events */
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/* ChromeOS related events */
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#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0
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#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1
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#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02
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@ -305,7 +305,7 @@ struct elog_event_mem_cache_update {
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#define ELOG_TYPE_MI_HRPC 0xb4
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#define ELOG_TYPE_MI_HR 0xb5
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/* Chrome OS diagnostics-related events */
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/* ChromeOS diagnostics-related events */
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#define ELOG_TYPE_CROS_DIAGNOSTICS 0xb6
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#define ELOG_CROS_LAUNCH_DIAGNOSTICS 0x01
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@ -165,7 +165,7 @@ enum timestamp_id {
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TS_KERNEL_START = 1101,
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TS_KERNEL_DECOMPRESSION = 1102,
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/* 1200-1300: Chrome OS Hypervisor */
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/* 1200-1300: ChromeOS Hypervisor */
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TS_CRHV_BOOT = 1200,
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TS_CRHV_PLATFORM_INIT = 1201,
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TS_CRHV_SERVICES_STARTED = 1202,
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@ -247,10 +247,10 @@ static const struct timestamp_id_to_name {
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TS_NAME_DEF(TS_EC_HASH_READY, 0, "EC vboot hash ready"),
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TS_NAME_DEF(TS_EC_POWER_LIMIT_WAIT, 0, "waiting for EC to allow higher power draw"),
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TS_NAME_DEF(TS_EC_SYNC_END, 0, "finished EC software sync"),
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TS_NAME_DEF(TS_COPYVPD_START, TS_COPYVPD_RW_END, "starting to load Chrome OS VPD"),
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TS_NAME_DEF(TS_COPYVPD_START, TS_COPYVPD_RW_END, "starting to load ChromeOS VPD"),
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TS_NAME_DEF(TS_COPYVPD_RO_END, TS_COPYVPD_RW_END,
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"finished loading Chrome OS VPD (RO)"),
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TS_NAME_DEF(TS_COPYVPD_RW_END, 0, "finished loading Chrome OS VPD (RW)"),
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"finished loading ChromeOS VPD (RO)"),
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TS_NAME_DEF(TS_COPYVPD_RW_END, 0, "finished loading ChromeOS VPD (RW)"),
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TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_START, TS_TPM_ENABLE_UPDATE_END,
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"started TPM enable update"),
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TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_END, 0, "finished TPM enable update"),
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@ -344,7 +344,7 @@ static const struct timestamp_id_to_name {
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TS_NAME_DEF(TS_KERNEL_START, 0, "jumping to kernel"),
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TS_NAME_DEF(TS_KERNEL_DECOMPRESSION, 0, "starting kernel decompression/relocation"),
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/* Chrome OS hypervisor */
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/* ChromeOS hypervisor */
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TS_NAME_DEF(TS_CRHV_BOOT, 0, "hypervisor boot finished"),
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TS_NAME_DEF(TS_CRHV_PLATFORM_INIT, 0, "hypervisor platform initialized"),
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TS_NAME_DEF(TS_CRHV_SERVICES_STARTED, 0, "hypervisor services started"),
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@ -2,6 +2,6 @@ config CHROMEOS_CAMERA
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bool
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default n
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help
|
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Camera with identifiers following Chrome OS Camera Info. The info is
|
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Camera with identifiers following ChromeOS Camera Info. The info is
|
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usually available on MIPI camera EEPROM for identifying correct
|
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drivers and config.
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@ -42,7 +42,7 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version)
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/*
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* Save MRC Data to CBMEM. By always saving the data this forces
|
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* a retrain after a trip through Chrome OS recovery path. The
|
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* a retrain after a trip through ChromeOS recovery path. The
|
||||
* code which saves the data to flash doesn't write if the latest
|
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* training data matches this one.
|
||||
*/
|
||||
|
||||
@ -125,9 +125,9 @@ config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
|
||||
|
||||
config EC_GOOGLE_CHROMEEC_RTC
|
||||
depends on EC_GOOGLE_CHROMEEC
|
||||
bool "Enable Chrome OS EC RTC"
|
||||
bool "Enable ChromeOS EC RTC"
|
||||
help
|
||||
Enable support for the real-time clock on the Chrome OS EC. This
|
||||
Enable support for the real-time clock on the ChromeOS EC. This
|
||||
uses the EC_CMD_RTC_GET_VALUE command to read the current time.
|
||||
|
||||
choice
|
||||
@ -194,7 +194,7 @@ config EC_GOOGLE_CHROMEEC_SWITCHES
|
||||
depends on EC_GOOGLE_CHROMEEC && VBOOT
|
||||
bool
|
||||
help
|
||||
Enable support for Chrome OS mode switches provided by the Chrome OS
|
||||
Enable support for ChromeOS mode switches provided by the ChromeOS
|
||||
EC.
|
||||
|
||||
config EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/*
|
||||
* Chrome OS Embedded Controller interface
|
||||
* ChromeOS Embedded Controller interface
|
||||
*
|
||||
* Constants that should be defined:
|
||||
*
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Chromium OS Matrix Keyboard Message Protocol definitions
|
||||
* ChromiumOS Matrix Keyboard Message Protocol definitions
|
||||
*/
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
/*
|
||||
* Command interface between EC and AP, for LPC, I2C and SPI interfaces.
|
||||
*
|
||||
* This is copied from the Chromium OS Open Source Embedded Controller code.
|
||||
* This is copied from the ChromiumOS Open Source Embedded Controller code.
|
||||
*/
|
||||
enum {
|
||||
/* The header byte, which follows the preamble */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# Firmware Layout Description for Chrome OS.
|
||||
# Firmware Layout Description for ChromeOS.
|
||||
#
|
||||
# The size and address of every section must be aligned to at least 4K, except:
|
||||
# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.
|
||||
|
||||
@ -97,7 +97,7 @@ config CHROMEOS
|
||||
select HAS_RECOVERY_MRC_CACHE
|
||||
|
||||
config CHROMEOS_WIFI_SAR
|
||||
bool "Enable SAR options for Chrome OS build"
|
||||
bool "Enable SAR options for ChromeOS build"
|
||||
depends on CHROMEOS
|
||||
select DSAR_ENABLE
|
||||
select GEO_SAR_ENABLE
|
||||
|
||||
@ -36,7 +36,7 @@ DefinitionBlock(
|
||||
/* Chipset specific sleep states */
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -79,7 +79,7 @@ chip soc/intel/alderlake
|
||||
chip drivers/gfx/generic
|
||||
register "device_count" = "1"
|
||||
register "device[0].name" = ""LCD""
|
||||
# Use Chrome OS privacy screen _HID
|
||||
# Use ChromeOS privacy screen _HID
|
||||
register "device[0].hid" = ""GOOG0010""
|
||||
# Internal panel on the first port of the graphics chip
|
||||
register "device[0].addr" = "0x80010400"
|
||||
|
||||
@ -71,7 +71,7 @@ chip soc/intel/alderlake
|
||||
chip drivers/gfx/generic
|
||||
register "device_count" = "1"
|
||||
register "device[0].name" = ""LCD""
|
||||
# Use Chrome OS privacy screen _HID
|
||||
# Use ChromeOS privacy screen _HID
|
||||
register "device[0].hid" = ""GOOG0010""
|
||||
# Internal panel on the first port of the graphics chip
|
||||
register "device[0].addr" = "0x80010400"
|
||||
|
||||
@ -570,7 +570,7 @@ chip soc/intel/alderlake
|
||||
end
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""GOOG0020""
|
||||
register "desc" = ""Chrome OS HPS""
|
||||
register "desc" = ""ChromeOS HPS""
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
|
||||
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
|
||||
# HPS uses I2C addresses 0x30 and 0x51.
|
||||
|
||||
@ -571,7 +571,7 @@ chip soc/intel/alderlake
|
||||
end
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""GOOG0020""
|
||||
register "desc" = ""Chrome OS HPS""
|
||||
register "desc" = ""ChromeOS HPS""
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
|
||||
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
|
||||
# HPS uses I2C addresses 0x30 and 0x51.
|
||||
|
||||
@ -99,7 +99,7 @@ chip soc/intel/alderlake
|
||||
chip drivers/gfx/generic
|
||||
register "device_count" = "1"
|
||||
register "device[0].name" = ""LCD""
|
||||
# Use Chrome OS privacy screen _HID
|
||||
# Use ChromeOS privacy screen _HID
|
||||
register "device[0].hid" = ""GOOG0010""
|
||||
# Internal panel on the first port of the graphics chip
|
||||
register "device[0].addr" = "0x80010400"
|
||||
|
||||
@ -85,7 +85,7 @@ chip soc/intel/alderlake
|
||||
chip drivers/gfx/generic
|
||||
register "device_count" = "1"
|
||||
register "device[0].name" = ""LCD""
|
||||
# Use Chrome OS privacy screen _HID
|
||||
# Use ChromeOS privacy screen _HID
|
||||
register "device[0].hid" = ""GOOG0010""
|
||||
# Internal panel on the first port of the graphics chip
|
||||
register "device[0].addr" = "0x80010400"
|
||||
|
||||
@ -570,7 +570,7 @@ chip soc/intel/alderlake
|
||||
end
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""GOOG0020""
|
||||
register "desc" = ""Chrome OS HPS""
|
||||
register "desc" = ""ChromeOS HPS""
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
|
||||
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
|
||||
# HPS uses I2C addresses 0x30 and 0x51.
|
||||
|
||||
@ -416,7 +416,7 @@ chip soc/intel/alderlake
|
||||
device ref i2c2 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""GOOG0020""
|
||||
register "desc" = ""Chrome OS HPS""
|
||||
register "desc" = ""ChromeOS HPS""
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
|
||||
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
|
||||
# HPS uses I2C addresses 0x30 and 0x51.
|
||||
|
||||
@ -320,7 +320,7 @@ chip soc/intel/alderlake
|
||||
device ref i2c2 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""GOOG0020""
|
||||
register "desc" = ""Chrome OS HPS""
|
||||
register "desc" = ""ChromeOS HPS""
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
|
||||
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
|
||||
# HPS uses I2C addresses 0x30 and 0x51.
|
||||
|
||||
@ -94,7 +94,7 @@ chip soc/intel/alderlake
|
||||
chip drivers/gfx/generic
|
||||
register "device_count" = "1"
|
||||
register "device[0].name" = ""LCD""
|
||||
# Use Chrome OS privacy screen _HID
|
||||
# Use ChromeOS privacy screen _HID
|
||||
register "device[0].hid" = ""GOOG0010""
|
||||
# Internal panel on the first port of the graphics chip
|
||||
register "device[0].addr" = "0x80010400"
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# Firmware Layout Description for Chrome OS.
|
||||
# Firmware Layout Description for ChromeOS.
|
||||
#
|
||||
# The size and address of every section must be aligned to at least 4K, except:
|
||||
# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# Firmware Layout Description for Chrome OS.
|
||||
# Firmware Layout Description for ChromeOS.
|
||||
#
|
||||
# The size and address of every section must be aligned to at least 4K, except:
|
||||
# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.
|
||||
|
||||
@ -65,7 +65,7 @@ config CHROMEOS
|
||||
select VBOOT_LID_SWITCH
|
||||
|
||||
config CHROMEOS_WIFI_SAR
|
||||
bool "Enable SAR options for Chrome OS build"
|
||||
bool "Enable SAR options for ChromeOS build"
|
||||
depends on CHROMEOS
|
||||
select DSAR_ENABLE
|
||||
select SAR_ENABLE
|
||||
|
||||
@ -37,7 +37,7 @@ DefinitionBlock(
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -39,7 +39,7 @@ config CHROMEOS
|
||||
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
|
||||
|
||||
config CHROMEOS_WIFI_SAR
|
||||
bool "Enable SAR options for Chrome OS build"
|
||||
bool "Enable SAR options for ChromeOS build"
|
||||
depends on CHROMEOS
|
||||
select DSAR_ENABLE
|
||||
select GEO_SAR_ENABLE
|
||||
|
||||
@ -33,7 +33,7 @@ DefinitionBlock(
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -34,7 +34,7 @@ DefinitionBlock(
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -33,7 +33,7 @@ DefinitionBlock(
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -15,7 +15,7 @@ DefinitionBlock (
|
||||
#include <acpi/dsdt_top.asl>
|
||||
#include <soc.asl>
|
||||
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -182,7 +182,7 @@ chip soc/amd/cezanne
|
||||
chip drivers/gfx/generic
|
||||
register "device_count" = "1"
|
||||
register "device[0].name" = ""LCD""
|
||||
# Use Chrome OS privacy screen _HID
|
||||
# Use ChromeOS privacy screen _HID
|
||||
register "device[0].hid" = ""GOOG0010""
|
||||
# Internal panel on the first port of the graphics chip
|
||||
register "device[0].addr" = "0x80010400"
|
||||
|
||||
@ -166,7 +166,7 @@ config CHROMEOS
|
||||
select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU
|
||||
|
||||
config CHROMEOS_WIFI_SAR
|
||||
bool "Enable SAR options for Chrome OS build"
|
||||
bool "Enable SAR options for ChromeOS build"
|
||||
depends on CHROMEOS
|
||||
select DSAR_ENABLE
|
||||
select GEO_SAR_ENABLE
|
||||
|
||||
@ -35,7 +35,7 @@ DefinitionBlock(
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -52,7 +52,7 @@ DefinitionBlock (
|
||||
/* Thermal handler */
|
||||
#include <variant/acpi/thermal.asl>
|
||||
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# Firmware Layout Description for Chrome OS.
|
||||
# Firmware Layout Description for ChromeOS.
|
||||
#
|
||||
# The size and address of every section must be aligned to at least 4K, except:
|
||||
# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.
|
||||
|
||||
@ -32,7 +32,7 @@ DefinitionBlock(
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -41,7 +41,7 @@ DefinitionBlock(
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -32,7 +32,7 @@ DefinitionBlock(
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -34,7 +34,7 @@ DefinitionBlock(
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
#if CONFIG(EC_GOOGLE_WILCO)
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -15,7 +15,7 @@ DefinitionBlock (
|
||||
#include <acpi/dsdt_top.asl>
|
||||
#include <soc.asl>
|
||||
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -140,7 +140,7 @@ config VBOOT_GSCVD
|
||||
default n
|
||||
|
||||
config CHROMEOS_WIFI_SAR
|
||||
bool "Enable SAR options for Chrome OS build"
|
||||
bool "Enable SAR options for ChromeOS build"
|
||||
depends on CHROMEOS
|
||||
select DSAR_ENABLE
|
||||
select GEO_SAR_ENABLE
|
||||
|
||||
@ -36,7 +36,7 @@ DefinitionBlock(
|
||||
#include "mainboard.asl"
|
||||
}
|
||||
|
||||
// Chrome OS Embedded Controller
|
||||
// ChromeOS Embedded Controller
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
// ACPI code for EC SuperIO functions
|
||||
|
||||
@ -44,7 +44,7 @@ DefinitionBlock (
|
||||
/* Thermal handler */
|
||||
#include <variant/acpi/thermal.asl>
|
||||
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -28,7 +28,7 @@ DefinitionBlock(
|
||||
}
|
||||
|
||||
#if CONFIG(EC_GOOGLE_CHROMEEC)
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -31,7 +31,7 @@ DefinitionBlock(
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -31,7 +31,7 @@ DefinitionBlock(
|
||||
}
|
||||
|
||||
#if CONFIG(EC_GOOGLE_CHROMEEC)
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -31,7 +31,7 @@ DefinitionBlock(
|
||||
}
|
||||
|
||||
#if CONFIG(EC_GOOGLE_CHROMEEC)
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -30,7 +30,7 @@ DefinitionBlock(
|
||||
}
|
||||
}
|
||||
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
// ACPI code for EC SuperIO functions
|
||||
|
||||
@ -33,7 +33,7 @@ DefinitionBlock(
|
||||
}
|
||||
|
||||
#if CONFIG(EC_GOOGLE_CHROMEEC)
|
||||
/* Chrome OS Embedded Controller */
|
||||
/* ChromeOS Embedded Controller */
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
|
||||
@ -103,7 +103,7 @@ config VBOOT_DISABLE_DEV_ON_RECOVERY
|
||||
bool
|
||||
default n
|
||||
help
|
||||
When this option is enabled, the Chrome OS device leaves the
|
||||
When this option is enabled, the ChromeOS device leaves the
|
||||
developer mode as soon as recovery request is detected. This is
|
||||
handy on embedded devices with limited input capabilities.
|
||||
|
||||
@ -321,10 +321,10 @@ config GBB_HWID
|
||||
string "Hardware ID"
|
||||
default ""
|
||||
help
|
||||
A hardware identifier for device. On Chrome OS this is used for auto
|
||||
A hardware identifier for device. On ChromeOS this is used for auto
|
||||
update and recovery, and will be generated when manufacturing by the
|
||||
factory software, in a strictly defined format.
|
||||
Leave empty to get a test-only Chrome OS HWID v2 string generated.
|
||||
Leave empty to get a test-only ChromeOS HWID v2 string generated.
|
||||
|
||||
config GBB_BMPFV_FILE
|
||||
string "Path to bmpfv image"
|
||||
@ -339,7 +339,7 @@ config GBB_FLAG_LOAD_OPTION_ROMS
|
||||
default n
|
||||
|
||||
config GBB_FLAG_ENABLE_ALTERNATE_OS
|
||||
bool "Allow booting a non-Chrome OS kernel if dev switch is on"
|
||||
bool "Allow booting a non-ChromeOS kernel if dev switch is on"
|
||||
default n
|
||||
|
||||
config GBB_FLAG_FORCE_DEV_SWITCH_ON
|
||||
|
||||
@ -434,7 +434,7 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK
|
||||
select ARCH_VERSTAGE_ARMV7
|
||||
help
|
||||
Runs verstage on the PSP. Only available on
|
||||
certain Chrome OS branded parts from AMD.
|
||||
certain ChromeOS branded parts from AMD.
|
||||
|
||||
config VBOOT_HASH_BLOCK_SIZE
|
||||
hex
|
||||
|
||||
@ -466,7 +466,7 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK
|
||||
select ARCH_VERSTAGE_ARMV7
|
||||
help
|
||||
Runs verstage on the PSP. Only available on
|
||||
certain Chrome OS branded parts from AMD.
|
||||
certain ChromeOS branded parts from AMD.
|
||||
|
||||
config VBOOT_HASH_BLOCK_SIZE
|
||||
hex
|
||||
|
||||
@ -454,7 +454,7 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK
|
||||
select ARCH_VERSTAGE_ARMV7
|
||||
help
|
||||
Runs verstage on the PSP. Only available on
|
||||
certain Chrome OS branded parts from AMD.
|
||||
certain ChromeOS branded parts from AMD.
|
||||
|
||||
config VBOOT_HASH_BLOCK_SIZE
|
||||
hex
|
||||
|
||||
@ -490,7 +490,7 @@ uint8_t cse_wait_com_soft_temp_disable(void);
|
||||
|
||||
/*
|
||||
* The CSE Lite SKU supports notion of RO and RW boot partitions. The function will set
|
||||
* CSE's boot partition as per Chrome OS boot modes. In normal mode, the function allows CSE to
|
||||
* CSE's boot partition as per ChromeOS boot modes. In normal mode, the function allows CSE to
|
||||
* boot from RW and triggers recovery mode if CSE fails to jump to RW.
|
||||
* In software triggered recovery mode, the function allows CSE to boot from whatever is
|
||||
* currently selected partition.
|
||||
|
||||
@ -46,7 +46,7 @@ static void set_cs(const struct spi_bitbang_ops *ops, int value)
|
||||
gpio_set(slave->cs, value);
|
||||
}
|
||||
|
||||
/* Can't use GPIO() here because of bug in GCC version used by Chromium OS. */
|
||||
/* Can't use GPIO() here because of bug in GCC version used by ChromiumOS. */
|
||||
static const struct rockchip_bitbang_slave slaves[] = {
|
||||
[0] = {
|
||||
.ops = { get_miso, set_mosi, set_clk, set_cs },
|
||||
|
||||
@ -23,7 +23,7 @@ config CHROMEOS
|
||||
if CHROMEOS
|
||||
|
||||
config CHROMEOS_RAMOOPS
|
||||
bool "Reserve space for Chrome OS ramoops"
|
||||
bool "Reserve space for ChromeOS ramoops"
|
||||
default y
|
||||
|
||||
config CHROMEOS_RAMOOPS_RAM_SIZE
|
||||
|
||||
@ -11,7 +11,7 @@
|
||||
* The Linux kernel implementation can be found at
|
||||
* drivers/net/usb/r8152.c:vendor_mac_passthru_addr_read()
|
||||
*
|
||||
* For Chrome OS, the policy which controls where the dock MAC address
|
||||
* For ChromeOS, the policy which controls where the dock MAC address
|
||||
* comes from is written into RW_VPD property "dock_passthrough":
|
||||
*
|
||||
* "dock_mac" or empty: Use MAC address from RO_VPD value "dock_mac"
|
||||
|
||||
@ -38,7 +38,7 @@ void chromeos_set_ramoops(void *ram_oops, size_t size);
|
||||
enum cb_err get_dsm_calibration_from_key(const char *key, uint64_t *value);
|
||||
|
||||
/*
|
||||
* Declaration for mainboards to use to generate ACPI-specific Chrome OS needs.
|
||||
* Declaration for mainboards to use to generate ACPI-specific ChromeOS needs.
|
||||
*/
|
||||
void chromeos_acpi_gpio_generate(void);
|
||||
|
||||
|
||||
@ -36,9 +36,9 @@ file `Python`
|
||||
* _rmodtool_ - Creates rmodules `C`
|
||||
* _ifwitool_ - For manipulating IFWI `C`
|
||||
* __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C`
|
||||
* __chromeos__ - These scripts can be used to access Chrome OS
|
||||
* __chromeos__ - These scripts can be used to access ChromeOS
|
||||
resources, for example to extract System Agent reference code and other
|
||||
blobs (e.g. mrc.bin, refcode, VGA option roms) from a Chrome OS
|
||||
blobs (e.g. mrc.bin, refcode, VGA option roms) from a ChromeOS
|
||||
recovery image. `C`
|
||||
* __crossgcc__ - A cross toolchain builder for -elf toolchains (ie. no
|
||||
libc support) `Bash`
|
||||
|
||||
@ -426,7 +426,7 @@ function build_config
|
||||
export HOSTCC='gcc'
|
||||
|
||||
if [ "$chromeos" = true ] && [ "$(grep -c "^[[:space:]]*select[[:space:]]*MAINBOARD_HAS_CHROMEOS\>" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig")" -eq 0 ]; then
|
||||
echo "${BUILD_NAME} doesn't support Chrome OS, skipping."
|
||||
echo "${BUILD_NAME} doesn't support ChromeOS, skipping."
|
||||
return
|
||||
fi
|
||||
|
||||
@ -450,7 +450,7 @@ function build_config
|
||||
# Skip this rule for configs created from templates that already
|
||||
# come with CHROMEOS enabled.
|
||||
grep -q "^CONFIG_CHROMEOS=y" ${config_file:-/dev/null} || \
|
||||
check_config "$build_dir" "Chrome OS" "CONFIG_CHROMEOS=y" negate
|
||||
check_config "$build_dir" "ChromeOS" "CONFIG_CHROMEOS=y" negate
|
||||
local FORCE_ENABLED_CROS=$?
|
||||
else
|
||||
local FORCE_ENABLED_CROS=0
|
||||
@ -611,7 +611,7 @@ Options:\n"
|
||||
[-u|--update] Update existing image
|
||||
[-v|--verbose] Print more messages
|
||||
[-x|--chromeos] Build with CHROMEOS enabled
|
||||
Skip boards without Chrome OS support
|
||||
Skip boards without ChromeOS support
|
||||
[-X|--xmlfile <name>] Set JUnit XML log file filename
|
||||
(defaults to $XMLFILE)
|
||||
[-y|--ccache] Use ccache
|
||||
@ -765,7 +765,7 @@ while true ; do
|
||||
-x|--chromeos) shift
|
||||
chromeos=true
|
||||
testclass=chromeos
|
||||
customizing="${customizing}, chrome os"
|
||||
customizing="${customizing}, chromeos"
|
||||
configoptions="${configoptions}CONFIG_CHROMEOS=y\nCONFIG_VBOOT_MEASURED_BOOT=y\n"
|
||||
;;
|
||||
-X|--xmlfile) shift; XMLFILE=$1; REAL_XMLFILE=$1; shift;;
|
||||
|
||||
@ -141,8 +141,8 @@ static void eventlog_print_type(const struct event_header *event)
|
||||
{ELOG_TYPE_S0IX_ENTER, "S0ix Enter"},
|
||||
{ELOG_TYPE_S0IX_EXIT, "S0ix Exit"},
|
||||
{ELOG_TYPE_WAKE_SOURCE, "Wake Source"},
|
||||
{ELOG_TYPE_CROS_DEVELOPER_MODE, "Chrome OS Developer Mode"},
|
||||
{ELOG_TYPE_CROS_RECOVERY_MODE, "Chrome OS Recovery Mode"},
|
||||
{ELOG_TYPE_CROS_DEVELOPER_MODE, "ChromeOS Developer Mode"},
|
||||
{ELOG_TYPE_CROS_RECOVERY_MODE, "ChromeOS Recovery Mode"},
|
||||
{ELOG_TYPE_MANAGEMENT_ENGINE, "Management Engine"},
|
||||
{ELOG_TYPE_MANAGEMENT_ENGINE_EXT, "Management Engine Extra"},
|
||||
{ELOG_TYPE_LAST_POST_CODE, "Last post code in previous boot"},
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* Copyright 2020 The Chromium OS Authors. All rights reserved.
|
||||
/* Copyright 2020 The ChromiumOS Authors. All rights reserved.
|
||||
* Use of this source code is governed by a BSD-style license that can be
|
||||
* found in the LICENSE file.
|
||||
*/
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* Copyright 2020 The Chromium OS Authors. All rights reserved.
|
||||
/* Copyright 2020 The ChromiumOS Authors. All rights reserved.
|
||||
* Use of this source code is governed by a BSD-style license that can be
|
||||
* found in the LICENSE file.
|
||||
*
|
||||
|
||||
@ -1,16 +1,16 @@
|
||||
# Chrome OS Scripts
|
||||
# ChromeOS Scripts
|
||||
|
||||
These scripts can be used to access or generate Chrome OS resources, for example
|
||||
These scripts can be used to access or generate ChromeOS resources, for example
|
||||
to extract System Agent reference code and other blobs (e.g. `mrc.bin`, refcode,
|
||||
VGA option roms) from a Chrome OS recovery image.
|
||||
VGA option roms) from a ChromeOS recovery image.
|
||||
|
||||
## crosfirmware.sh
|
||||
|
||||
`crosfirmware.sh` downloads a Chrome OS recovery image from the recovery
|
||||
`crosfirmware.sh` downloads a ChromeOS recovery image from the recovery
|
||||
image server, unpacks it, extracts the firmware update shell archive,
|
||||
extracts the firmware images from the shell archive.
|
||||
|
||||
To download all Chrome OS firmware images, run
|
||||
To download all ChromeOS firmware images, run
|
||||
|
||||
$ ./crosfirmware.sh
|
||||
|
||||
@ -21,14 +21,14 @@ To download, e.g. the Panther firmware image, run
|
||||
|
||||
## extract_blobs.sh
|
||||
|
||||
`extract_blobs.sh` extracts the blobs from a Chrome OS firmware image.
|
||||
`extract_blobs.sh` extracts the blobs from a ChromeOS firmware image.
|
||||
|
||||
Right now it will produce the ME firmware blob, IFD, VGA option rom,
|
||||
and `mrc.bin`.
|
||||
|
||||
## gen_test_hwid.sh
|
||||
|
||||
`gen_test_hwid.sh` generates a test-only identifier in Chrome OS HWID v2
|
||||
`gen_test_hwid.sh` generates a test-only identifier in ChromeOS HWID v2
|
||||
compatible format.
|
||||
|
||||
Usage:
|
||||
|
||||
@ -1,3 +1,3 @@
|
||||
These scripts can be used to access Chrome OS resources, for example to extract
|
||||
These scripts can be used to access ChromeOS resources, for example to extract
|
||||
System Agent reference code and other blobs (e.g. mrc.bin, refcode, VGA option
|
||||
roms) from a Chrome OS recovery image. `C`
|
||||
roms) from a ChromeOS recovery image. `C`
|
||||
|
||||
@ -8,7 +8,7 @@ main() {
|
||||
exit 1
|
||||
fi
|
||||
|
||||
# Generate a test-only Chrome OS HWID v2 string
|
||||
# Generate a test-only ChromeOS HWID v2 string
|
||||
local board="$1"
|
||||
local prefix="$(echo "${board}" | tr a-z A-Z) TEST"
|
||||
# gzip has second-to-last 4 bytes in CRC32.
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user