c4e90454f4
Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
120 lines
3.3 KiB
C
120 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __CHROMEOS_H__
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#define __CHROMEOS_H__
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#include <stddef.h>
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#include <stdint.h>
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#include <types.h>
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#if CONFIG(CHROMEOS)
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/* functions implemented in watchdog.c */
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void mark_watchdog_tombstone(void);
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void reboot_from_watchdog(void);
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bool reset_watchdog_tombstone(void);
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#else
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static inline void mark_watchdog_tombstone(void) { return; }
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static inline void reboot_from_watchdog(void) { return; }
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#endif /* CONFIG_CHROMEOS */
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/**
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* Perform any platform specific actions required prior to resetting the Cr50.
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* Defined as weak function in cr50_enable_update.c
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*/
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void mainboard_prepare_cr50_reset(void);
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void cbmem_add_vpd_calibration_data(void);
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void chromeos_set_me_hash(u32*, int);
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void chromeos_set_ramoops(void *ram_oops, size_t size);
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/**
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* get_dsm_calibration_from_key - Gets value related to DSM calibration from VPD
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* @key: The key in RO_VPD. The valid prefix is "dsm_calib_". The valid keys are
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* documented in https://chromeos.google.com/partner/dlm/docs/factory/vpd.html.
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* @value: Output value. The value read from VPD parsed into uint64_t integer.
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*
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* Returns CB_SUCCESS on success or CB_ERR on failure.
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*/
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enum cb_err get_dsm_calibration_from_key(const char *key, uint64_t *value);
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/*
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* Declaration for mainboards to use to generate ACPI-specific ChromeOS needs.
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*/
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void chromeos_acpi_gpio_generate(void);
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enum {
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CROS_GPIO_REC = 1, /* Recovery */
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CROS_GPIO_DEPRECATED_DEV = 2, /* Developer;
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* deprecated (chromium:942901) */
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CROS_GPIO_WP = 3, /* Write Protect */
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CROS_GPIO_PE = 4, /* Phase enforcement for final product */
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CROS_GPIO_ACTIVE_LOW = 0,
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CROS_GPIO_ACTIVE_HIGH = 1,
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CROS_GPIO_VIRTUAL = -1,
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};
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struct cros_gpio {
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int type;
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int polarity;
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int gpio_num;
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const char *device;
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};
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#define CROS_GPIO_INITIALIZER(typ, pol, num, dev) \
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{ \
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.type = (typ), \
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.polarity = (pol), \
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.gpio_num = (num), \
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.device = (dev), \
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}
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#define CROS_GPIO_REC_INITIALIZER(pol, num, dev) \
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CROS_GPIO_INITIALIZER(CROS_GPIO_REC, pol, num, dev)
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#define CROS_GPIO_REC_AL(num, dev) \
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CROS_GPIO_REC_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev)
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#define CROS_GPIO_REC_AH(num, dev) \
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CROS_GPIO_REC_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev)
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#define CROS_GPIO_WP_INITIALIZER(pol, num, dev) \
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CROS_GPIO_INITIALIZER(CROS_GPIO_WP, pol, num, dev)
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#define CROS_GPIO_WP_AL(num, dev) \
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CROS_GPIO_WP_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev)
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#define CROS_GPIO_WP_AH(num, dev) \
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CROS_GPIO_WP_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev)
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#define CROS_GPIO_PE_INITIALIZER(pol, num, dev) \
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CROS_GPIO_INITIALIZER(CROS_GPIO_PE, pol, num, dev)
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#define CROS_GPIO_PE_AL(num, dev) \
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CROS_GPIO_PE_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev)
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#define CROS_GPIO_PE_AH(num, dev) \
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CROS_GPIO_PE_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev)
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struct cros_gpio_pack {
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int count;
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const struct cros_gpio *gpios;
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};
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extern const struct cros_gpio_pack variant_cros_gpio;
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#define DECLARE_NO_CROS_GPIOS() \
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const struct cros_gpio_pack variant_cros_gpio = \
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{ .count = 0, .gpios = NULL }
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#define DECLARE_CROS_GPIOS(x) \
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const struct cros_gpio_pack variant_cros_gpio = \
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{ .count = ARRAY_SIZE(x), .gpios = x }
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#define DECLARE_WEAK_CROS_GPIOS(x) \
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const struct cros_gpio_pack __weak variant_cros_gpio = \
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{ .count = ARRAY_SIZE(x), .gpios = x }
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#endif /* __CHROMEOS_H__ */
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