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1915ec1fe74a0f65d0e75464e176e5692bf27190
system76-coreboot/src/soc/intel
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Subrata Banik 1915ec1fe7 soc/intel/alderlake: Drop local ufs.asl 
This patch drops `ufs.asl` from the local SoC directory.

BUG=none
TEST=Able to build and boot Google/Kano.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I84e0b51e74e2d6a7120f1d990152bc27e37a501f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68302
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
2022-10-20 14:40:30 +00:00
..
alderlake
soc/intel/alderlake: Drop local ufs.asl
2022-10-20 14:40:30 +00:00
apollolake
soc/intel/apollolake: Lock down Global SMI
2022-10-15 22:33:54 +00:00
baytrail
treewide: Use 'fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk'
2022-10-15 16:53:55 +00:00
braswell
treewide: Use 'fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk'
2022-10-15 16:53:55 +00:00
broadwell
treewide: Use 'fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk'
2022-10-15 16:53:55 +00:00
cannonlake
treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk'
2022-10-12 14:18:35 +00:00
common
soc/intel/cmn/block/acpi: Create common ASL entry for UFS
2022-10-20 14:40:00 +00:00
denverton_ns
payloads,src: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity
2022-10-13 19:14:57 +00:00
elkhartlake
soc/intel: Kconfig: Correct UART source clock value in comment
2022-10-12 23:51:09 +00:00
icelake
treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk'
2022-10-12 14:18:35 +00:00
jasperlake
treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk'
2022-10-12 14:18:35 +00:00
meteorlake
soc/intel: Kconfig: Correct UART source clock value in comment
2022-10-12 23:51:09 +00:00
quark
treewide: Use 'fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk'
2022-10-15 16:53:45 +00:00
skylake
treewide: Use 'fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk'
2022-10-15 16:53:55 +00:00
tigerlake
soc/intel: Kconfig: Correct UART source clock value in comment
2022-10-12 23:51:09 +00:00
xeon_sp
payloads,src: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity
2022-10-13 19:14:57 +00:00
Makefile.inc
soc/intel/common/cse: Add support for stitching CSE components
2021-10-19 16:09:08 +00:00