19799b4cd9
The ACPI name of any device needs to match the name used for generating
the S0i3 LPI constraint list, which comes from soc_acpi_name() for each
SoC. The names used for the eMMC controller do not match, which will
lead to broken ACPI tables since the LPI constriant will reference
an ACPI device which does not exist. Some OSes tolerate this better
than others, but it should still be corrected.
TEST=build/boot google/{hatch,volteer, brya}, dump ACPI and verify
no invalid device names referenced.
Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78825
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
194 lines
4.0 KiB
Plaintext
194 lines
4.0 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/pcr_ids.h>
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Scope (\_SB.PCI0) {
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/*
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* Clear register 0x1C20/0x4820
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* Arg0 - PCR Port ID
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*/
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Method(SCSC, 1, Serialized)
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{
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PCRA (Arg0, 0x1C20, 0x0)
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PCRA (Arg0, 0x4820, 0x0)
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}
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/* EMMC */
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Device(EMMC) {
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Name(_ADR, 0x001A0000)
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Name (_DDN, "eMMC Controller")
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Name (TEMP, 0)
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OperationRegion(SCSR, PCI_Config, 0x00, 0x100)
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Field(SCSR, WordAcc, NoLock, Preserve) {
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Offset (0x84), /* PMECTRLSTATUS */
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PMCR, 16,
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Offset (0xA2), /* PG_CONFIG */
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, 2,
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PGEN, 1, /* PG_ENABLE */
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}
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Method(_INI) {
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/* Clear register 0x1C20/0x4820 */
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SCSC (PID_EMMC)
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}
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Method(_PS0, 0, Serialized) {
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Stall (50) // Sleep 50 us
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PGEN = 0 // Disable PG
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/* Clear register 0x1C20/0x4820 */
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SCSC (PID_EMMC)
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/* Set Power State to D0 */
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PMCR = PMCR & 0xFFFC
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TEMP = PMCR
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}
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Method(_PS3, 0, Serialized) {
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PGEN = 1 // Enable PG
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/* Set Power State to D3 */
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PMCR = PMCR | 0x0003
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TEMP = PMCR
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}
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Device (CARD)
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{
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Name (_ADR, 0x00000008)
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Method (_RMV, 0, NotSerialized)
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{
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Return (0)
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}
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}
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}
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/* SD CARD */
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Device (SDXC)
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{
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Name (_ADR, 0x001A0001)
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Name (_DDN, "SD Controller")
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Name (TEMP, 0)
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Name (DSUU, ToUUID("f6c13ea5-65cd-461f-ab7a-29f7e8d5bd61"))
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OperationRegion (SDPC, PCI_Config, 0x00, 0x100)
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Field (SDPC, WordAcc, NoLock, Preserve)
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{
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Offset (0x84), /* PMECTRLSTATUS */
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PMCR, 16,
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Offset (0xA2), /* PG_CONFIG */
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, 2,
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PGEN, 1, /* PG_ENABLE */
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}
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/*
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* _DSM x86 Device Specific Method
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* Arg0: UUID Unique function identifier
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* Arg1: Integer Revision Level
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* Arg2: Integer Function Index (0 = Return Supported Functions)
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* Arg3: Package Parameters
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*/
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Method (_DSM, 4)
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{
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If (Arg0 == DSUU) {
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/* Check the revision */
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If (Arg1 >= 0) {
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/*
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* Function Index 0 the return value is a buffer containing
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* one bit for each function index, starting with zero.
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* Bit 0 - Indicates whether there is support for any
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* functions other than function 0.
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* Bit 1 - Indicates support to clear power control register
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* Bit 2 - Indicates support to set power control register
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* Bit 3 - Indicates support to set 1.8V signalling
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* Bit 4 - Indicates support to set 3.3V signalling
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* Bit 5 - Indicates support for HS200 mode
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* Bit 6 - Indicates support for HS400 mode
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* Bit 9 - Indicates eMMC I/O Driver Strength
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*/
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/*
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* For SD we have to support functions to
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* set 1.8V signalling and 3.3V signalling [BIT4, BIT3]
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*/
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If (Arg2 == 0) {
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Return (Buffer () { 0x19 })
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}
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/*
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* Function Index 3: Set 1.8v signalling.
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* We put a sleep of 100ms in this method to
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* work around a known issue with detecting
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* UHS SD card on PCH. This is to compensate
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* for the SD VR slowness.
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*/
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If (Arg2 == 3) {
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Sleep (100)
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Return(Buffer () { 0x00 })
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}
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/*
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* Function Index 4: Set 3.3v signalling.
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* We put a sleep of 100ms in this method to
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* work around a known issue with detecting
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* UHS SD card on PCH. This is to compensate
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* for the SD VR slowness.
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*/
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If (Arg2 == 4) {
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Sleep (100)
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Return(Buffer () { 0x00 })
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}
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}
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}
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Return(Buffer() { 0x0 })
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}
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Method(_INI)
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{
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/* Clear register 0x1C20/0x4820 */
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SCSC (PID_SDX)
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}
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Method (_PS0, 0, Serialized)
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{
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PGEN = 0 /* Disable PG */
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/* Clear register 0x1C20/0x4820 */
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SCSC (PID_SDX)
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/* Set Power State to D0 */
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PMCR = PMCR & 0xFFFC
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TEMP = PMCR
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/* Change pad mode to Native */
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GPMO(SD_PWR_EN_PIN, 0x1)
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}
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Method (_PS3, 0, Serialized)
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{
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PGEN = 1 /* Enable PG */
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/* Set Power State to D3 */
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PMCR = PMCR | 0x0003
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TEMP = PMCR
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/* Change pad mode to GPIO control */
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GPMO(SD_PWR_EN_PIN, 0x0)
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/* Enable Tx Buffer */
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GTXE(SD_PWR_EN_PIN, 0x1)
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/* Drive TX to zero */
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CTXS(SD_PWR_EN_PIN)
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}
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Device (CARD)
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{
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Name (_ADR, 0x00000008)
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Method (_RMV, 0, NotSerialized)
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{
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Return (1)
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}
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}
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} /* Device (SDXC) */
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}
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