pchandri 1d77c721d3 intel/kunimitsu FAB3: Configure LPC to Quiet Mode. ...

This patch configures the LPC to quiet mode and sets
enables CLKRUN so that LPC can be power gated.

BUG=chrome-os-partner:44993
BRANCH=none
TEST=Builds and Boots on fab3 kunimitsu.

Change-Id: I46ff21f75b70f54da3f12dcc56d61f84b436cd7d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: edd37df385bc013b62f26435267291acc0a9b9a4
Original-Change-Id: Ide0f9e91127aebb8ac027ee0a598608b50aa4278
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/305396
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com>
Reviewed-on: http://review.coreboot.org/12153
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2015-10-27 15:18:09 +01:00

..

acpi

intel/skylake: IRQ programming through UPD

2015-10-27 15:16:02 +01:00

bootblock

cpu/mtrr.h: Fix macro names for MTRR registers

2015-10-15 03:52:49 +00:00

include/soc

intel/kunimitsu FAB3: Configure LPC to Quiet Mode.

2015-10-27 15:18:09 +01:00

romstage

intel/skylake: FSP 1.7.0 MemoryInit/SiliconInit params update

2015-10-27 15:15:39 +01:00

acpi.c

intel/skylake: Add support for Gfx PEIM (AKA GOP)

2015-10-27 15:15:22 +01:00

chip.c

intel/skylake: IRQ programming through UPD

2015-10-27 15:16:02 +01:00

chip.h

intel/skylake: IRQ programming through UPD

2015-10-27 15:16:02 +01:00

cpu_info.c

soc/intel: Add Skylake SOC support

2015-07-16 17:24:48 +02:00

cpu.c

cpu/mtrr.h: Fix macro names for MTRR registers

2015-10-15 03:52:49 +00:00

elog.c

skylake: align power management names with hardware

2015-07-29 19:31:07 +02:00

finalize.c

soc/intel: Add Skylake SOC support

2015-07-16 17:24:48 +02:00

flash_controller.c

skylake: refactor flash_controller code

2015-09-08 11:30:11 +00:00

gpio.c

Skylake: Print GPIO MMIO base and pad config using gpio_debug token

2015-09-10 09:43:37 +00:00

igd.c

intel/skylake: Add support for Gfx PEIM (AKA GOP)

2015-10-27 15:15:22 +01:00

Kconfig

intel/kunimitsu FAB3: Configure LPC to Quiet Mode.

2015-10-27 15:18:09 +01:00

lpc.c

intel/kunimitsu FAB3: Configure LPC to Quiet Mode.

2015-10-27 15:18:09 +01:00

Makefile.inc

skylake: add support for verstage

2015-10-11 23:59:14 +00:00

memmap.c

Skylake: update cbmem_top

2015-08-19 14:04:31 +00:00

monotonic_timer.c

skylake: allow timer_monotonic_get() in all stages

2015-09-08 11:22:24 +00:00

pch.c

skylake: SPI code cleanup

2015-10-11 23:57:53 +00:00

pcie.c

soc/intel: Add Skylake SOC support

2015-07-16 17:24:48 +02:00

pcr.c

skylake: provide pcr helper to get a port's register space

2015-07-29 19:30:49 +02:00

pei_data.c

intel/skylake: Fix RMT disable of saved training data

2015-08-29 07:18:49 +00:00

pmc.c

Skylake:Set DISB inside romstage after mrc init

2015-09-08 11:35:37 +00:00

pmutil.c

skylake: fix SMI GPI status handling

2015-08-14 15:21:16 +02:00

ramstage.c

fsp1_1: provide binding to UEFI version

2015-09-10 17:52:28 +00:00

smbus_common.c

soc/intel: Add Skylake SOC support

2015-07-16 17:24:48 +02:00

smbus.c

soc/intel: Add Skylake SOC support

2015-07-16 17:24:48 +02:00

smi.c

soc/intel: Add Skylake SOC support

2015-07-16 17:24:48 +02:00

smihandler.c

skylake: fix SMI GPI status handling

2015-08-14 15:21:16 +02:00

smmrelocate.c

cpu/mtrr.h: Fix macro names for MTRR registers

2015-10-15 03:52:49 +00:00

systemagent.c

Skylake: update cbmem_top

2015-08-19 14:04:31 +00:00

tsc_freq.c

soc/intel: Add Skylake SOC support

2015-07-16 17:24:48 +02:00

uart_debug.c

skylake: fix serial port with new code base

2015-08-13 16:33:53 +02:00

uart.c

skylake: fix serial port with new code base

2015-08-13 16:33:53 +02:00

xhci.c

soc/intel: Add Skylake SOC support

2015-07-16 17:24:48 +02:00