73add175cd
With this implementation it's possible to detect the state of bootguard in intel based systems. Currently it's WIP and in a testphase. Handle it with care! Changes done: * Add support for reading msr * Read ME firmware version * Print bootguard state for ME > 9.1 * Make argument -s legacy * Add argument -b for bootguard (and ME) dumping * Add argument -m for ME dumping * Opt out early if CPU is non Intel Change-Id: Ifeec8e20fa8efc35d7db4c6a84be1f118dccfc4a Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/16328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
318 lines
13 KiB
C
318 lines
13 KiB
C
/*
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* intelmetool
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*
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* Copyright (C) 2008-2010 by coresystems GmbH
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* Copyright (C) 2009 Carl-Daniel Hailfinger
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* Copyright (C) 2015 Damien Zammit
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define ME_NOT_PRESENT 0
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#define ME_FOUND_NOTHING 1
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#define ME_FOUND_SOMETHING_NOT_SURE 2
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#define ME_CAN_DISABLE_IF_PRESENT 3
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#define ME_PRESENT_CAN_DISABLE 4
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#define ME_PRESENT_CANNOT_DISABLE 5
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#define INTELMETOOL_VERSION "1.1"
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#define GPLV2COPYRIGHT \
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"This program is free software: you can redistribute it and/or modify\n" \
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"it under the terms of the GNU General Public License as published by\n" \
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"the Free Software Foundation, version 2 of the License.\n\n" \
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"This program is distributed in the hope that it will be useful,\n" \
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"but WITHOUT ANY WARRANTY; without even the implied warranty of\n" \
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"MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n" \
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"GNU General Public License for more details.\n\n"
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#if defined(__GLIBC__)
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#include <sys/io.h>
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#endif
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#if (defined(__MACH__) && defined(__APPLE__))
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/* DirectHW is available here: https://www.coreboot.org/DirectHW */
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#define __DARWIN__
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#include <DirectHW/DirectHW.h>
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#endif
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#ifdef __NetBSD__
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#include <pciutils/pci.h>
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#else
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#include <pci/pci.h>
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#endif
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#define CNRM "\x1B[0m"
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#define CRED "\x1B[31m"
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#define CGRN "\x1B[32m"
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#define CYEL "\x1B[33m"
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#define CBLU "\x1B[34m"
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#define CMAG "\x1B[35m"
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#define CCYN "\x1B[36m"
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#define CWHT "\x1B[37m"
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#define RESET "\033[0m"
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#define CPU_ID_SIZE 13
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#define FD2 0x3428
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#define ME_COMMAND_DELAY 10000
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#define ME_MESSAGE_LEN 256
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extern int debug;
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static inline void print_cap(const char *name, int state)
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{
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printf("ME Capability: %-30s : %s\n",
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name, state ? CRED "ON" RESET : CGRN "OFF" RESET);
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}
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#define PCI_VENDOR_ID_INTEL 0x8086
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// Definitely has ME and can be disabled
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#define PCI_DEVICE_ID_INTEL_ICH8ME 0x2811
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#define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917
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#define PCI_DEVICE_ID_INTEL_ICH9M 0x2919
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#define PCI_DEV_HAS_ME_DISABLE(x) ( \
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((x) == PCI_DEVICE_ID_INTEL_ICH8ME) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH9ME) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH9M ))
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// Definitely has ME and is very difficult to remove
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#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16
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#define PCI_DEVICE_ID_INTEL_3400_DESKTOP 0x3b00
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#define PCI_DEVICE_ID_INTEL_3400_MOBILE 0x3b01
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#define PCI_DEVICE_ID_INTEL_P55 0x3b02
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#define PCI_DEVICE_ID_INTEL_PM55 0x3b03
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#define PCI_DEVICE_ID_INTEL_H55 0x3b06
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#define PCI_DEVICE_ID_INTEL_QM57 0x3b07
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#define PCI_DEVICE_ID_INTEL_H57 0x3b08
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#define PCI_DEVICE_ID_INTEL_HM55 0x3b09
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#define PCI_DEVICE_ID_INTEL_Q57 0x3b0a
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#define PCI_DEVICE_ID_INTEL_HM57 0x3b0b
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#define PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF 0x3b0d
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#define PCI_DEVICE_ID_INTEL_B55_A 0x3b0e
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#define PCI_DEVICE_ID_INTEL_QS57 0x3b0f
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#define PCI_DEVICE_ID_INTEL_3400 0x3b12
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#define PCI_DEVICE_ID_INTEL_3420 0x3b14
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#define PCI_DEVICE_ID_INTEL_3450 0x3b16
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#define PCI_DEVICE_ID_INTEL_B55_B 0x3b1e
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#define PCI_DEVICE_ID_INTEL_Z68 0x1c44
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#define PCI_DEVICE_ID_INTEL_P67 0x1c46
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#define PCI_DEVICE_ID_INTEL_UM67 0x1c47
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#define PCI_DEVICE_ID_INTEL_HM65 0x1c49
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#define PCI_DEVICE_ID_INTEL_H67 0x1c4a
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#define PCI_DEVICE_ID_INTEL_HM67 0x1c4b
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#define PCI_DEVICE_ID_INTEL_Q65 0x1c4c
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#define PCI_DEVICE_ID_INTEL_QS67 0x1c4d
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#define PCI_DEVICE_ID_INTEL_Q67 0x1c4e
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#define PCI_DEVICE_ID_INTEL_QM67 0x1c4f
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#define PCI_DEVICE_ID_INTEL_B65 0x1c50
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#define PCI_DEVICE_ID_INTEL_C202 0x1c52
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#define PCI_DEVICE_ID_INTEL_C204 0x1c54
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#define PCI_DEVICE_ID_INTEL_C206 0x1c56
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#define PCI_DEVICE_ID_INTEL_H61 0x1c5c
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#define PCI_DEVICE_ID_INTEL_Z77 0x1e44
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#define PCI_DEVICE_ID_INTEL_Z75 0x1e46
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#define PCI_DEVICE_ID_INTEL_Q77 0x1e47
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#define PCI_DEVICE_ID_INTEL_Q75 0x1e48
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#define PCI_DEVICE_ID_INTEL_B75 0x1e49
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#define PCI_DEVICE_ID_INTEL_H77 0x1e4a
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#define PCI_DEVICE_ID_INTEL_C216 0x1e53
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#define PCI_DEVICE_ID_INTEL_QM77 0x1e55
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#define PCI_DEVICE_ID_INTEL_QS77 0x1e56
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#define PCI_DEVICE_ID_INTEL_HM77 0x1e57
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#define PCI_DEVICE_ID_INTEL_UM77 0x1e58
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#define PCI_DEVICE_ID_INTEL_HM76 0x1e59
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#define PCI_DEVICE_ID_INTEL_HM75 0x1e5d
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#define PCI_DEVICE_ID_INTEL_HM70 0x1e5e
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#define PCI_DEVICE_ID_INTEL_NM70 0x1e5f
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#define PCI_DEVICE_ID_INTEL_QM87 0x8c4f
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#define PCI_DEVICE_ID_INTEL_DH89XXCC 0x2310
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45
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#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5
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#define PCI_DEVICE_ID_INTEL_X99 0x8d47
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#define PCI_DEV_HAS_ME_DIFFICULT(x) ( \
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((x) == PCI_DEVICE_ID_INTEL_ICH10R) || \
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((x) == PCI_DEVICE_ID_INTEL_3400_DESKTOP) || \
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((x) == PCI_DEVICE_ID_INTEL_3400_MOBILE) || \
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((x) == PCI_DEVICE_ID_INTEL_P55 ) || \
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((x) == PCI_DEVICE_ID_INTEL_PM55 ) || \
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((x) == PCI_DEVICE_ID_INTEL_H55 ) || \
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((x) == PCI_DEVICE_ID_INTEL_QM57 ) || \
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((x) == PCI_DEVICE_ID_INTEL_H57 ) || \
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((x) == PCI_DEVICE_ID_INTEL_HM55 ) || \
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((x) == PCI_DEVICE_ID_INTEL_Q57 ) || \
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((x) == PCI_DEVICE_ID_INTEL_HM57 ) || \
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((x) == PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF) || \
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((x) == PCI_DEVICE_ID_INTEL_B55_A ) || \
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((x) == PCI_DEVICE_ID_INTEL_QS57 ) || \
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((x) == PCI_DEVICE_ID_INTEL_3400 ) || \
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((x) == PCI_DEVICE_ID_INTEL_3420 ) || \
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((x) == PCI_DEVICE_ID_INTEL_3450 ) || \
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((x) == PCI_DEVICE_ID_INTEL_B55_B ) || \
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((x) == PCI_DEVICE_ID_INTEL_Z68 ) || \
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((x) == PCI_DEVICE_ID_INTEL_P67 ) || \
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((x) == PCI_DEVICE_ID_INTEL_UM67 ) || \
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((x) == PCI_DEVICE_ID_INTEL_HM65 ) || \
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((x) == PCI_DEVICE_ID_INTEL_H67 ) || \
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((x) == PCI_DEVICE_ID_INTEL_HM67 ) || \
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((x) == PCI_DEVICE_ID_INTEL_Q65 ) || \
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((x) == PCI_DEVICE_ID_INTEL_QS67 ) || \
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((x) == PCI_DEVICE_ID_INTEL_Q67 ) || \
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((x) == PCI_DEVICE_ID_INTEL_QM67 ) || \
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((x) == PCI_DEVICE_ID_INTEL_B65 ) || \
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((x) == PCI_DEVICE_ID_INTEL_C202 ) || \
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((x) == PCI_DEVICE_ID_INTEL_C204 ) || \
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((x) == PCI_DEVICE_ID_INTEL_C206 ) || \
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((x) == PCI_DEVICE_ID_INTEL_H61 ) || \
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((x) == PCI_DEVICE_ID_INTEL_Z77 ) || \
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((x) == PCI_DEVICE_ID_INTEL_Z75 ) || \
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((x) == PCI_DEVICE_ID_INTEL_Q77 ) || \
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((x) == PCI_DEVICE_ID_INTEL_Q75 ) || \
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((x) == PCI_DEVICE_ID_INTEL_B75 ) || \
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((x) == PCI_DEVICE_ID_INTEL_H77 ) || \
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((x) == PCI_DEVICE_ID_INTEL_C216 ) || \
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((x) == PCI_DEVICE_ID_INTEL_QM77 ) || \
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((x) == PCI_DEVICE_ID_INTEL_QS77 ) || \
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((x) == PCI_DEVICE_ID_INTEL_HM77 ) || \
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((x) == PCI_DEVICE_ID_INTEL_UM77 ) || \
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((x) == PCI_DEVICE_ID_INTEL_HM76 ) || \
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((x) == PCI_DEVICE_ID_INTEL_HM75 ) || \
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((x) == PCI_DEVICE_ID_INTEL_HM70 ) || \
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((x) == PCI_DEVICE_ID_INTEL_NM70 ) || \
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((x) == PCI_DEVICE_ID_INTEL_QM87 ) || \
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((x) == PCI_DEVICE_ID_INTEL_DH89XXCC ) || \
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((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL ) || \
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((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM ) || \
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((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE ) || \
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((x) == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP ) || \
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((x) == PCI_DEVICE_ID_INTEL_X99 ))
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// Not sure if ME present, but should be able to disable it easily
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#define PCI_DEVICE_ID_INTEL_ICH8 0x2810
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#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815
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#define PCI_DEVICE_ID_INTEL_ICH9DH 0x2912
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#define PCI_DEVICE_ID_INTEL_ICH9DO 0x2914
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#define PCI_DEVICE_ID_INTEL_ICH9R 0x2916
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#define PCI_DEVICE_ID_INTEL_ICH9 0x2918
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#define PCI_DEV_CAN_DISABLE_ME_IF_PRESENT(x) ( \
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((x) == PCI_DEVICE_ID_INTEL_ICH8 ) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH8M ) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH9DH ) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH9DO ) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH9R ) || \
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((x) == PCI_DEVICE_ID_INTEL_ICH9 ))
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// Not sure at all
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#define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119
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#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100
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#define PCI_DEV_ME_NOT_SURE(x) ( \
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((x) == PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC) || \
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((x) == PCI_DEVICE_ID_INTEL_SCH_POULSBO))
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#define PCI_DEVICE_ID_INTEL_COUGARPOINT_1 0x1C3A /* Cougar Point */
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#define PCI_DEVICE_ID_INTEL_PATSBURG_1 0x1D3A /* C600/X79 Patsburg */
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#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_1 0x1CBA /* Panther Point */
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#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_2 0x1DBA /* Panther Point */
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#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_3 0x1E3A /* Panther Point */
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#define PCI_DEVICE_ID_INTEL_CAVECREEK 0x2364 /* Cave Creek */
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#define PCI_DEVICE_ID_INTEL_BEARLAKE_1 0x28B4 /* Bearlake */
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#define PCI_DEVICE_ID_INTEL_BEARLAKE_2 0x28C4 /* Bearlake */
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#define PCI_DEVICE_ID_INTEL_BEARLAKE_3 0x28D4 /* Bearlake */
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#define PCI_DEVICE_ID_INTEL_BEARLAKE_4 0x28E4 /* Bearlake */
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#define PCI_DEVICE_ID_INTEL_BEARLAKE_5 0x28F4 /* Bearlake */
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#define PCI_DEVICE_ID_INTEL_82946GZ 0x2974 /* 82946GZ/GL */
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#define PCI_DEVICE_ID_INTEL_82G35 0x2984 /* 82G35 Express */
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#define PCI_DEVICE_ID_INTEL_82Q963 0x2994 /* 82Q963/Q965 */
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#define PCI_DEVICE_ID_INTEL_82P965 0x29A4 /* 82P965/G965 */
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#define PCI_DEVICE_ID_INTEL_82Q35 0x29B4 /* 82Q35 Express */
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#define PCI_DEVICE_ID_INTEL_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */
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#define PCI_DEVICE_ID_INTEL_82Q33 0x29D4 /* 82Q33 Express */
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#define PCI_DEVICE_ID_INTEL_82X38 0x29E4 /* 82X38/X48 Express */
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#define PCI_DEVICE_ID_INTEL_3200 0x29F4 /* 3200/3210 Server */
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#define PCI_DEVICE_ID_INTEL_PM965 0x2A04 /* Mobile PM965/GM965 */
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#define PCI_DEVICE_ID_INTEL_GME965 0x2A14 /* Mobile GME965/GLE960 */
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#define PCI_DEVICE_ID_INTEL_CANTIGA_1 0x2A44 /* Cantiga */
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#define PCI_DEVICE_ID_INTEL_CANTIGA_2 0x2a50 /* Cantiga */
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#define PCI_DEVICE_ID_INTEL_CANTIGA_3 0x2A54 /* Cantiga */
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#define PCI_DEVICE_ID_INTEL_CANTIGA_4 0x2A64 /* Cantiga */
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#define PCI_DEVICE_ID_INTEL_CANTIGA_5 0x2A74 /* Cantiga */
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#define PCI_DEVICE_ID_INTEL_EAGLELAKE_1 0x2E04 /* Eaglelake */
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#define PCI_DEVICE_ID_INTEL_EAGLELAKE_2 0x2E14 /* Eaglelake */
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#define PCI_DEVICE_ID_INTEL_EAGLELAKE_3 0x2E24 /* Eaglelake */
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#define PCI_DEVICE_ID_INTEL_EAGLELAKE_4 0x2E34 /* Eaglelake */
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#define PCI_DEVICE_ID_INTEL_CALPELLA_1 0x3B64 /* Calpella */
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#define PCI_DEVICE_ID_INTEL_CALPELLA_2 0x3B65 /* Calpella */
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_1 0x8C3A /* Lynx Point H */
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_2 0x8CBA /* Lynx Point H Refresh */
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_3 0x8D3A /* Lynx Point - Wellsburg */
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_4 0x9C3A /* Lynx Point LP */
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#define PCI_DEVICE_ID_INTEL_WILDCAT_1 0x9CBA /* Wildcat Point LP */
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#define PCI_DEVICE_ID_INTEL_WILDCAT_2 0x9CBB /* Wildcat Point LP 2 */
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H1 0xa13a /* SUNRISE Point-H 1 */
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#define PCI_DEVICE_ID_INTEL_SUNRISE_H2 0xa13b /* SUNRISE Point-H 2 */
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#define PCI_DEVICE_ID_INTEL_SUNRISE_LP 0x9d3a /* SUNRISE Point-LP */
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#define PCI_DEV_HAS_SUPPORTED_ME(x) ( \
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((x) == PCI_DEVICE_ID_INTEL_COUGARPOINT_1) || \
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((x) == PCI_DEVICE_ID_INTEL_PATSBURG_1) || \
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((x) == PCI_DEVICE_ID_INTEL_PANTHERPOINT_1) || \
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((x) == PCI_DEVICE_ID_INTEL_PANTHERPOINT_2) || \
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((x) == PCI_DEVICE_ID_INTEL_PANTHERPOINT_3) || \
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((x) == PCI_DEVICE_ID_INTEL_CAVECREEK) || \
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((x) == PCI_DEVICE_ID_INTEL_BEARLAKE_1) || \
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((x) == PCI_DEVICE_ID_INTEL_BEARLAKE_2) || \
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((x) == PCI_DEVICE_ID_INTEL_BEARLAKE_3) || \
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((x) == PCI_DEVICE_ID_INTEL_BEARLAKE_4) || \
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((x) == PCI_DEVICE_ID_INTEL_BEARLAKE_5) || \
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((x) == PCI_DEVICE_ID_INTEL_82946GZ) || \
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((x) == PCI_DEVICE_ID_INTEL_82G35) || \
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((x) == PCI_DEVICE_ID_INTEL_82Q963) || \
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((x) == PCI_DEVICE_ID_INTEL_82P965) || \
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((x) == PCI_DEVICE_ID_INTEL_82Q35) || \
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((x) == PCI_DEVICE_ID_INTEL_82G33) || \
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((x) == PCI_DEVICE_ID_INTEL_82Q33) || \
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((x) == PCI_DEVICE_ID_INTEL_82X38) || \
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((x) == PCI_DEVICE_ID_INTEL_3200) || \
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((x) == PCI_DEVICE_ID_INTEL_PM965) || \
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((x) == PCI_DEVICE_ID_INTEL_GME965) || \
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((x) == PCI_DEVICE_ID_INTEL_CANTIGA_1) || \
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((x) == PCI_DEVICE_ID_INTEL_CANTIGA_2) || \
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((x) == PCI_DEVICE_ID_INTEL_CANTIGA_3) || \
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((x) == PCI_DEVICE_ID_INTEL_CANTIGA_4) || \
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((x) == PCI_DEVICE_ID_INTEL_CANTIGA_5) || \
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((x) == PCI_DEVICE_ID_INTEL_EAGLELAKE_1) || \
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((x) == PCI_DEVICE_ID_INTEL_EAGLELAKE_2) || \
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((x) == PCI_DEVICE_ID_INTEL_EAGLELAKE_3) || \
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((x) == PCI_DEVICE_ID_INTEL_EAGLELAKE_4) || \
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((x) == PCI_DEVICE_ID_INTEL_CALPELLA_1) || \
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((x) == PCI_DEVICE_ID_INTEL_CALPELLA_2) || \
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((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_1) || \
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((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_2) || \
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((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_3) || \
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((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_4) || \
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((x) == PCI_DEVICE_ID_INTEL_WILDCAT_1) || \
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((x) == PCI_DEVICE_ID_INTEL_WILDCAT_2) || \
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((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H1) || \
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((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H2) || \
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((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP))
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#define BOOTGUARD_DISABLED 0x400000000
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#define BOOTGUARD_ENABLED_VERIFIED_MODE 0x100000000
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#define BOOTGUARD_ENABLED_MEASUREMENT_MODE 0x200000000
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#define BOOTGUARD_ENABLED_COMBI_MODE 0x300000000
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#define BOOTGUARD_CAPABILITY(x) ( \
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((x) == BOOTGUARD_DISABLED) || \
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((x) == BOOTGUARD_ENABLED_VERIFIED_MODE) || \
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((x) == BOOTGUARD_ENABLED_MEASUREMENT_MODE) || \
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((x) == BOOTGUARD_ENABLED_COMBI_MODE))
|