11e90e06d3
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3033 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
499 lines
12 KiB
C
499 lines
12 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
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* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2007 Luc Verhaegen <libv@skynet.be>
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* Copyright (C) 2007 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* Contains the board specific flash enables.
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*/
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#include <stdio.h>
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#include <pci/pci.h>
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#include <stdint.h>
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#include <string.h>
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#include "flash.h"
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/*
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* Helper functions for many Winbond Super I/Os of the W836xx range.
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*/
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/* Enter extended functions */
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static void w836xx_ext_enter(uint16_t port)
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{
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outb(0x87, port);
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outb(0x87, port);
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}
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/* Leave extended functions */
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static void w836xx_ext_leave(uint16_t port)
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{
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outb(0xAA, port);
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}
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/* General functions for reading/writing Winbond Super I/Os. */
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static unsigned char wbsio_read(uint16_t index, uint8_t reg)
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{
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outb(reg, index);
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return inb(index + 1);
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}
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static void wbsio_write(uint16_t index, uint8_t reg, uint8_t data)
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{
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outb(reg, index);
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outb(data, index + 1);
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}
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static void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask)
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{
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uint8_t tmp;
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outb(reg, index);
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tmp = inb(index + 1) & ~mask;
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outb(tmp | (data & mask), index + 1);
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}
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/**
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* Winbond W83627HF: Raise GPIO24.
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*
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* Suited for:
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* - Agami Aruma
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* - IWILL DK8-HTX
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*/
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static int w83627hf_gpio24_raise(uint16_t index, const char *name)
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{
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w836xx_ext_enter(index);
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/* Is this the W83627HF? */
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if (wbsio_read(index, 0x20) != 0x52) { /* Super I/O device ID reg. */
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fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
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name, wbsio_read(index, 0x20));
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w836xx_ext_leave(index);
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return -1;
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}
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/* PIN89S: WDTO/GP24 multiplex -> GPIO24 */
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wbsio_mask(index, 0x2B, 0x10, 0x10);
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/* Select logical device 8: GPIO port 2 */
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wbsio_write(index, 0x07, 0x08);
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wbsio_mask(index, 0x30, 0x01, 0x01); /* Activate logical device. */
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wbsio_mask(index, 0xF0, 0x00, 0x10); /* GPIO24 -> output */
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wbsio_mask(index, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */
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wbsio_mask(index, 0xF1, 0x10, 0x10); /* Raise GPIO24 */
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w836xx_ext_leave(index);
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return 0;
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}
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static int w83627hf_gpio24_raise_2e(const char *name)
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{
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/* TODO: Typo? Shouldn't this be 0x2e? */
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return w83627hf_gpio24_raise(0x2d, name);
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}
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/**
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* Winbond W83627THF: GPIO 4, bit 4
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*
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* Suited for:
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* - MSI K8N-NEO3
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*/
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static int w83627thf_gpio4_4_raise(uint16_t index, const char *name)
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{
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w836xx_ext_enter(index);
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/* Is this the W83627THF? */
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if (wbsio_read(index, 0x20) != 0x82) { /* Super I/O device ID reg. */
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fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n",
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name, wbsio_read(index, 0x20));
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w836xx_ext_leave(index);
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return -1;
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}
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/* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */
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wbsio_write(index, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */
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wbsio_mask(index, 0x30, 0x02, 0x02); /* Activate logical device. */
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wbsio_mask(index, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */
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wbsio_mask(index, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */
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wbsio_mask(index, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */
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w836xx_ext_leave(index);
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return 0;
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}
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static int w83627thf_gpio4_4_raise_4e(const char *name)
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{
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return w83627thf_gpio4_4_raise(0x4e, name);
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}
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/**
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* Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
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*
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* We don't need to do this when using LinuxBIOS, GPIO15 is never lowered there.
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*/
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static int board_via_epia_m(const char *name)
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{
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struct pci_dev *dev;
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uint16_t base;
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uint8_t val;
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dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
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if (!dev) {
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fprintf(stderr, "\nERROR: VT8235 ISA bridge not found.\n");
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return -1;
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}
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/* GPIO12-15 -> output */
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val = pci_read_byte(dev, 0xE4);
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val |= 0x10;
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pci_write_byte(dev, 0xE4, val);
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/* Get Power Management IO address. */
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base = pci_read_word(dev, 0x88) & 0xFF80;
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/* Enable GPIO15 which is connected to write protect. */
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val = inb(base + 0x4D);
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val |= 0x80;
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outb(val, base + 0x4D);
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return 0;
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}
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/**
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* Suited for:
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* - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
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* - Tyan Tomcat K7M: AMD Geode NX + VIA KM400 + VT8237.
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*/
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static int board_asus_a7v8x_mx(const char *name)
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{
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struct pci_dev *dev;
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uint8_t val;
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dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
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if (!dev)
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dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */
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if (!dev) {
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fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n");
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return -1;
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}
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/* This bit is marked reserved actually. */
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val = pci_read_byte(dev, 0x59);
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val &= 0x7F;
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pci_write_byte(dev, 0x59, val);
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/* Raise ROM MEMW# line on Winbond W83697 Super I/O. */
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w836xx_ext_enter(0x2E);
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if (!(wbsio_read(0x2E, 0x24) & 0x02)) /* Flash ROM enabled? */
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wbsio_mask(0x2E, 0x24, 0x08, 0x08); /* Enable MEMW#. */
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w836xx_ext_leave(0x2E);
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return 0;
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}
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/**
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* Suited for ASUS P5A.
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*
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* This is rather nasty code, but there's no way to do this cleanly.
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* We're basically talking to some unknown device on SMBus, my guess
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* is that it is the Winbond W83781D that lives near the DIP BIOS.
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*/
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static int board_asus_p5a(const char *name)
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{
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uint8_t tmp;
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int i;
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#define ASUSP5A_LOOP 5000
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outb(0x00, 0xE807);
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outb(0xEF, 0xE803);
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outb(0xFF, 0xE800);
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for (i = 0; i < ASUSP5A_LOOP; i++) {
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outb(0xE1, 0xFF);
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if (inb(0xE800) & 0x04)
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break;
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}
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if (i == ASUSP5A_LOOP) {
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printf("%s: Unable to contact device.\n", name);
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return -1;
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}
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outb(0x20, 0xE801);
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outb(0x20, 0xE1);
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outb(0xFF, 0xE802);
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for (i = 0; i < ASUSP5A_LOOP; i++) {
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tmp = inb(0xE800);
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if (tmp & 0x70)
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break;
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}
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if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
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printf("%s: failed to read device.\n", name);
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return -1;
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}
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tmp = inb(0xE804);
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tmp &= ~0x02;
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outb(0x00, 0xE807);
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outb(0xEE, 0xE803);
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outb(tmp, 0xE804);
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outb(0xFF, 0xE800);
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outb(0xE1, 0xFF);
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outb(0x20, 0xE801);
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outb(0x20, 0xE1);
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outb(0xFF, 0xE802);
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for (i = 0; i < ASUSP5A_LOOP; i++) {
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tmp = inb(0xE800);
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if (tmp & 0x70)
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break;
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}
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if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
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printf("%s: failed to write to device.\n", name);
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return -1;
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}
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return 0;
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}
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static int board_ibm_x3455(const char *name)
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{
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uint8_t byte;
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/* Set GPIO lines in the Broadcom HT-1000 southbridge. */
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outb(0x45, 0xcd6);
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byte = inb(0xcd7);
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outb(byte | 0x20, 0xcd7);
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return 0;
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}
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/**
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* Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards.
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*/
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static int board_epox_ep_bx3(const char *name)
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{
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uint8_t tmp;
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/* Raise GPIO22. */
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tmp = inb(0x4036);
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outb(tmp, 0xEB);
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tmp |= 0x40;
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outb(tmp, 0x4036);
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outb(tmp, 0xEB);
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return 0;
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}
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/**
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* Suited for Acorp 6A815EPD.
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*/
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static int board_acorp_6a815epd(const char *name)
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{
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struct pci_dev *dev;
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uint16_t port;
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uint8_t val;
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dev = pci_dev_find(0x8086, 0x2440); /* Intel ICH2 LPC */
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if (!dev) {
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fprintf(stderr, "\nERROR: ICH2 LPC bridge not found.\n");
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return -1;
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}
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/* Use GPIOBASE register to find where the GPIO is mapped. */
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port = (pci_read_word(dev, 0x58) & 0xFFC0) + 0xE;
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val = inb(port);
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val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */
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val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */
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outb(val, port);
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return 0;
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}
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/**
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* We use 2 sets of IDs here, you're free to choose which is which. This
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* is to provide a very high degree of certainty when matching a board on
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* the basis of subsystem/card IDs. As not every vendor handles
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* subsystem/card IDs in a sane manner.
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*
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* Keep the second set NULLed if it should be ignored.
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*/
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struct board_pciid_enable {
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/* Any device, but make it sensible, like the ISA bridge. */
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uint16_t first_vendor;
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uint16_t first_device;
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uint16_t first_card_vendor;
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uint16_t first_card_device;
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/* Any device, but make it sensible, like
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* the host bridge. May be NULL.
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*/
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uint16_t second_vendor;
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uint16_t second_device;
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uint16_t second_card_vendor;
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uint16_t second_card_device;
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/* The vendor / part name from the LinuxBIOS table. */
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const char *lb_vendor;
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const char *lb_part;
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const char *name;
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int (*enable) (const char *name);
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};
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struct board_pciid_enable board_pciid_enables[] = {
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{0x10de, 0x0360, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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"gigabyte", "m57sli", "GIGABYTE GA-M57SLI-S4", it87xx_probe_spi_flash},
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{0x10de, 0x03e0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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"gigabyte", "m61p", "GIGABYTE GA-M61P-S3", it87xx_probe_spi_flash},
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{0x1039, 0x0761, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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"gigabyte", "2761gxdk", "GIGABYTE GA-2761GXDK", it87xx_probe_spi_flash},
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{0x1022, 0x7468, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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"iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise_2e},
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{0x10de, 0x005e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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"msi", "k8n-neo3", "MSI K8N Neo3", w83627thf_gpio4_4_raise_4e},
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{0x1022, 0x746B, 0x1022, 0x36C0, 0x0000, 0x0000, 0x0000, 0x0000,
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"AGAMI", "ARUMA", "agami Aruma", w83627hf_gpio24_raise_2e},
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{0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01,
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NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m},
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{0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118,
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NULL, NULL, "ASUS A7V8-MX SE", board_asus_a7v8x_mx},
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{0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498,
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NULL, NULL, "Tyan Tomcat K7M", board_asus_a7v8x_mx},
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{0x10B9, 0x1541, 0x0000, 0x0000, 0x10B9, 0x1533, 0x0000, 0x0000,
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"asus", "p5a", "ASUS P5A", board_asus_p5a},
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{0x1166, 0x0205, 0x1014, 0x0347, 0x0000, 0x0000, 0x0000, 0x0000,
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"ibm", "x3455", "IBM x3455", board_ibm_x3455},
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{0x8086, 0x7110, 0x0000, 0x0000, 0x8086, 0x7190, 0x0000, 0x0000,
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"epox", "ep-bx3", "EPoX EP-BX3", board_epox_ep_bx3},
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{0x8086, 0x1130, 0x0000, 0x0000, 0x105a, 0x0d30, 0x105a, 0x4d33,
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"acorp", "6a815epd", "Acorp 6A815EPD", board_acorp_6a815epd},
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{0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */
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};
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/**
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* Match boards on LinuxBIOS table gathered vendor and part name.
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* Require main PCI IDs to match too as extra safety.
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*/
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static struct board_pciid_enable *board_match_linuxbios_name(const char *vendor, const char *part)
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{
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struct board_pciid_enable *board = board_pciid_enables;
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for (; board->name; board++) {
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if (!board->lb_vendor || strcmp(board->lb_vendor, vendor))
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continue;
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if (!board->lb_part || strcmp(board->lb_part, part))
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continue;
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if (!pci_dev_find(board->first_vendor, board->first_device))
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continue;
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if (board->second_vendor &&
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!pci_dev_find(board->second_vendor, board->second_device))
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continue;
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return board;
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}
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printf("NOT FOUND %s:%s\n", vendor, part);
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return NULL;
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}
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/**
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* Match boards on PCI IDs and subsystem IDs.
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* Second set of IDs can be main only or missing completely.
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*/
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static struct board_pciid_enable *board_match_pci_card_ids(void)
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{
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struct board_pciid_enable *board = board_pciid_enables;
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for (; board->name; board++) {
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if (!board->first_card_vendor || !board->first_card_device)
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continue;
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if (!pci_card_find(board->first_vendor, board->first_device,
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board->first_card_vendor,
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board->first_card_device))
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continue;
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if (board->second_vendor) {
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if (board->second_card_vendor) {
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if (!pci_card_find(board->second_vendor,
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board->second_device,
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board->second_card_vendor,
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board->second_card_device))
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continue;
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} else {
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if (!pci_dev_find(board->second_vendor,
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board->second_device))
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continue;
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}
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}
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return board;
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}
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return NULL;
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}
|
|
|
|
int board_flash_enable(const char *vendor, const char *part)
|
|
{
|
|
struct board_pciid_enable *board = NULL;
|
|
int ret = 0;
|
|
|
|
if (vendor && part)
|
|
board = board_match_linuxbios_name(vendor, part);
|
|
|
|
if (!board)
|
|
board = board_match_pci_card_ids();
|
|
|
|
if (board) {
|
|
printf("Found board \"%s\": enabling flash write... ",
|
|
board->name);
|
|
|
|
ret = board->enable(board->name);
|
|
if (ret)
|
|
printf("FAILED!\n");
|
|
else
|
|
printf("OK.\n");
|
|
}
|
|
|
|
return ret;
|
|
}
|