c272a87f5c
Behavior matches with other dumps of inteltool. Change-Id: Id9755d251fc42185c9e8d574deb55c76e129b718 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
110 lines
2.9 KiB
C
110 lines
2.9 KiB
C
/*
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* ahci.c: dump AHCI registers
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*
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* Copyright (C) 2016 Iru Cai
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* Copyright (C) 2017 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the
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* License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <inttypes.h>
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#include "inteltool.h"
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static const char *ghc_regs[] = {
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"CAP", "GHC", "IS", "PI",
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"VS", "CCC_CTL", "CCC_PORTS", "EM_LOC",
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"EM_CTL", "CAP2", "BOHC"
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};
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static const char *port_ctl_regs[] = {
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"PxCLB", "PxCLBU", "PxFB", "PxFBU",
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"PxIS", "PxIE", "PxCMD", "Reserved",
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"PxTFD", "PxSIG", "PxSSTS", "PxSCTL",
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"PxSERR", "PxSACT", "PxCI", "PxSNTF",
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"PxFBS", "PxDEVSLP", "Reserved"
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};
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#define NUM_GHC (sizeof(ghc_regs)/sizeof(ghc_regs[0]))
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#define NUM_PORTCTL (sizeof(port_ctl_regs)/sizeof(port_ctl_regs[0]))
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#define MMIO(offset) (*(uint32_t *)(mmio + offset))
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#define MMIO_PORT(offset) (*(uint32_t *)(mmio_port + offset))
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static void print_port(const uint8_t *const mmio, size_t port)
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{
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size_t i;
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printf("\nPort %zu Control Registers:\n", port);
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const uint8_t *const mmio_port = mmio + 0x100 + port * 0x80;
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for (i = 0; i < 0x80; i += 4) {
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if (i / 4 < NUM_PORTCTL) {
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printf("0x%03zx: 0x%08x (%s)\n",
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(size_t)(mmio_port - mmio) + i,
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MMIO_PORT(i), port_ctl_regs[i / 4]);
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} else if (MMIO_PORT(i)) {
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printf("0x%03zx: 0x%08x (Reserved)\n",
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(size_t)(mmio_port - mmio) + i, MMIO_PORT(i));
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}
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}
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}
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int print_ahci(struct pci_dev *ahci)
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{
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size_t mmio_size, i;
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if (!ahci) {
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puts("No SATA device found");
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return 0;
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}
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printf("\n============= AHCI Registers ==============\n\n");
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if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA)
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mmio_size = 0x800;
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else
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mmio_size = 0x400;
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const pciaddr_t mmio_phys = ahci->base_addr[5] & ~0x7ULL;
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printf("ABAR = 0x%08llx (MEM)\n\n", (unsigned long long)mmio_phys);
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const uint8_t *const mmio = map_physical(mmio_phys, mmio_size);
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if (mmio == NULL) {
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perror("Error mapping MMIO");
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exit(1);
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}
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puts("Generic Host Control Registers:");
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for (i = 0; i < 0x100; i += 4) {
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if (i / 4 < NUM_GHC) {
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printf("0x%03zx: 0x%08x (%s)\n",
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i, MMIO(i), ghc_regs[i / 4]);
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} else if (MMIO(i)) {
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printf("0x%03zx: 0x%08x (Reserved)\n", i, MMIO(i));
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}
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}
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const size_t max_ports = (mmio_size - 0x100) / 0x80;
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for (i = 0; i < max_ports; i++) {
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if (MMIO(0x0c) & 1 << i)
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print_port(mmio, i);
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}
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if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA) {
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puts("\nOther registers:");
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for (i = 0x500; i < mmio_size; i += 4) {
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if (MMIO(i))
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printf("0x%03zx: 0x%08x\n", i, MMIO(i));
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}
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}
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unmap_physical((void *)mmio, mmio_size);
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return 0;
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}
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