35599f9a66
Recommonmark has been deprecated since 2021 [1] and the last release was
over 3 years ago [2]. As per their announcement, Markedly Structured
Text (MyST) Parser [3] is the recommended replacement.
For the most part, the existing documentation is compatible with MyST,
as both parsers are built around the CommonMark flavor of Markdown. The
main difference that affects coreboot is how the Sphinx toctree is
generated. Recommonmark has a feature called auto_toc_tree, which
converts single level lists of references into a toctree:
* [Part 1: Starting from scratch](part1.md)
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)
MyST Parser does not provide a replacement for this feature, meaning the
toctree must be defined manually. This is done using MyST's syntax for
Sphinx directives:
```{toctree}
:maxdepth: 1
Part 1: Starting from scratch <part1.md>
Part 2: Submitting a patch to coreboot.org <part2.md>
Part 3: Writing unit tests <part3.md>
Managing local additions <managing_local_additions.md>
Flashing firmware <flashing_firmware/index.md>
```
Internally, auto_toc_tree essentially converts lists of references into
the Sphinx toctree structure that the MyST syntax above more directly
represents.
The toctrees were converted to the MyST syntax using the following
command and Python script:
`find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py`
```
import re
import sys
in_list = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()
with open(sys.argv[1], "w") as f:
for line in lines:
match = re.match(r"^[-*+] \[(.*)\]\((.*)\)$", line)
if match is not None:
if not in_list:
in_list = True
f.write("```{toctree}\n")
f.write(":maxdepth: 1\n\n")
f.write(match.group(1) + " <" + match.group(2) + ">\n")
else:
if in_list:
f.write("```\n")
f.write(line)
in_list = False
if in_list:
f.write("```\n")
```
While this does add a little more work for creating the toctree, this
does give more control over exactly what goes into the toctree. For
instance, lists of links to external resources currently end up in the
toctree, but we may want to limit it to pages within coreboot.
This change does break rendering and navigation of the documentation in
applications that can render Markdown, such as Okular, Gitiles, or the
GitHub mirror. Assuming the docs are mainly intended to be viewed after
being rendered to doc.coreboot.org, this is probably not an issue in
practice.
Another difference is that MyST natively supports Markdown tables,
whereas with Recommonmark, tables had to be written in embedded rST [4].
However, MyST also supports embedded rST, so the existing tables can be
easily converted as the syntax is nearly identical.
These were converted using
`find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"`
Makefile.sphinx and conf.py were regenerated from scratch by running
`sphinx-quickstart` using the updated version of Sphinx, which removes a
lot of old commented out boilerplate. Any relevant changes coreboot had
made on top of the previous autogenerated versions of these files were
ported over to the newly generated file.
From some initial testing the generated webpages appear and function
identically to the existing documentation built with Recommonmark.
TEST: `make -C util/docker docker-build-docs` builds the documentation
successfully and the generated output renders properly when viewed in
a web browser.
[1] https://github.com/readthedocs/recommonmark/issues/221
[2] https://pypi.org/project/recommonmark/
[3] https://myst-parser.readthedocs.io/en/latest/
[4] https://doc.coreboot.org/getting_started/writing_documentation.html
Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
5.2 KiB
ASUS P8Z77-M
This page describes how to run coreboot on the ASUS P8Z77-M.
Flashing coreboot
+---------------------+----------------+
| Type | Value |
+=====================+================+
| Model | W25Q64FVA1Q |
+---------------------+----------------+
| Size | 8 MiB |
+---------------------+----------------+
| Package | DIP-8 |
+---------------------+----------------+
| Socketed | yes |
+---------------------+----------------+
| Write protection | yes |
+---------------------+----------------+
| Dual BIOS feature | no |
+---------------------+----------------+
| Internal flashing | yes |
+---------------------+----------------+
The flash chip is located between the blue SATA ports.
The main SPI flash cannot be written internally because Asus disables BIOSWE and
enables BLE/SMM_BWP flags in BIOS_CNTL for their latest bioses.
To install coreboot for the first time, the flash chip must be removed and
flashed with an external programmer; flashing in-circuit doesn't work.
The flash chip is socketed, so it's easy to remove and reflash.
Working
-
All USB2 ports (mouse, keyboard and thumb drive)
-
USB3 ports on rear (Boots SystemRescue 6.0.3 off a Kingston DataTraveler G4 8GB)
-
Gigabit Ethernet (RTL8111F)
-
SATA3, SATA2 (all ports, hot-swap not tested) (Blue SATA2) (Blue SATA2) (White SATA3) port 5 port 3 port 1 port 6 port 4 port 2
-
CPU Temp sensors and hardware monitor (some values don't make sense)
-
Native and MRC memory initialization (please see [Native raminit compatibility] and [MRC memory compatibility])
-
Integrated graphics with both libgfxinit and the Intel Video BIOS OpROM (VGA/DVI-D/HDMI tested and working)
-
16x PCIe GPU in PCIe-16x/4x slots (tested using nVidia Quadro 600 under SystemRescue 6.0.3 (Arch based))
-
Serial port
-
PCI slot Rockwell HSF 56k PCI modem, Sound Blaster Live! CT4780 (cards detected, not function tested) Promise SATA150 TX2plus (R/W OK to connected IDE hard drive, OpRom loaded, cannot boot from SeaBIOS)
-
S3 suspend from Linux
-
2-channel analog audio (WAV playback by mplayer via back panel line out port)
-
Windows 10 with libgfxinit high resolution framebuffer and VBT
Known issues
-
If you use MRC raminit, the NVRAM variable gfx_uma_size may be ignored as IGP's UMA could be reconfigured by the blob.
-
If SeaBIOS is used for payload with libgfxinit, it must be brought in via coreboot's config. Otherwise integrated graphics would fail with a black screen.
-
PCI POST card is not functional because the PCI bridge early init is not yet done.
-
The black PCIEX16_2 slot, although can physically fit an x16, only has physical contacts for an x8, and is electrically an x4 only.
Untested
- Wake-on-LAN
- USB3 on header
- TPM header
- EHCI debugging (Debug port is on the 5-pin side of USB2_910 header)
- HDMI and S/PDIF audio out
Not working
- PS/2 keyboard or mouse
- 4 and 6 channel analog audio out: Rear left and right audio is a muted copy of front left and right audio, and the other two channels are silent.
Native (and MRC) raminit compatibility
-
OCZ OCZ3G1600LVAM 2x2GB kit works at DDR3-1066 instead of DDR3-1600.
-
GSkill F3-1600C9D-16GRSL 2x8GB SODIMM kit on adapter boots, but is highly unstable with obvious pattern of bit errors during memtest86+ runs.
-
Samsung PC3-10600U 2x2GB kit works at full rated speed.
-
Kingston KTH9600B-4G 2x4GB kit works at full rated speed.
Extra onboard buttons
The board has two onboard buttons, and each has a related LED nearby. What controls the LEDs and what the buttons control are unknown, therefore they currently do nothing under coreboot.
-
BIOS_FLBK OEM firmware uses this button to facilitate a simple update mechanism via a USB drive plugged into the bottom USB port of the USB/LAN stack.
-
MemOK! OEM firmware uses this button for memory tuning related to overclocking.
Technology
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+
| Southbridge | bd82x6x |
+------------------+--------------------------------------------------+
| CPU | model_206ax |
+------------------+--------------------------------------------------+
| Super I/O | Nuvoton NCT6779D |
+------------------+--------------------------------------------------+
| EC | None |
+------------------+--------------------------------------------------+
| Coprocessor | Intel Management Engine |
+------------------+--------------------------------------------------+