9c98664480
Previously, X4X was incorrectly named because it provides support for SKUs within XX4X range. This is renamed. This patch provides support for all X4X SKUs according to datasheet Intel 4 Series Chipset Family Specification Update, namely: Q45, Q43, P45, P43, G45, G43, G41 and B43 (both versions). Tested on Gigabyte GA-G41M-ES2L Change-Id: I032265e80d9ca51e2fef29201280832ea3210a0b Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/11245 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
218 lines
8.6 KiB
C
218 lines
8.6 KiB
C
/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008-2010 by coresystems GmbH
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* Copyright (C) 2009 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <stdint.h>
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#if defined(__GLIBC__)
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#include <sys/io.h>
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#endif
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#if (defined(__MACH__) && defined(__APPLE__))
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/* DirectHW is available here: http://www.coreboot.org/DirectHW */
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#define __DARWIN__
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#include <DirectHW/DirectHW.h>
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#endif
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#include <pci/pci.h>
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/* This #include is needed for freebsd_{rd,wr}msr. */
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#if defined(__FreeBSD__)
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#include <machine/cpufunc.h>
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#endif
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#define INTELTOOL_VERSION "1.0"
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/* Tested chipsets: */
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_DEVICE_ID_INTEL_ICH 0x2410
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#define PCI_DEVICE_ID_INTEL_ICH0 0x2420
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#define PCI_DEVICE_ID_INTEL_ICH2 0x2440
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#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0
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#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc
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#define PCI_DEVICE_ID_INTEL_ICH5 0x24d0
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#define PCI_DEVICE_ID_INTEL_ICH6 0x2640
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#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0
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#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8
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#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9
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#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd
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#define PCI_DEVICE_ID_INTEL_NM10 0x27bc
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#define PCI_DEVICE_ID_INTEL_ICH8 0x2810
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#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815
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#define PCI_DEVICE_ID_INTEL_ICH8ME 0x2811
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#define PCI_DEVICE_ID_INTEL_ICH9DH 0x2912
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#define PCI_DEVICE_ID_INTEL_ICH9DO 0x2914
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#define PCI_DEVICE_ID_INTEL_ICH9R 0x2916
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#define PCI_DEVICE_ID_INTEL_ICH9 0x2918
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#define PCI_DEVICE_ID_INTEL_ICH9M 0x2919
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#define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917
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#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16
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#define PCI_DEVICE_ID_INTEL_3400_DESKTOP 0x3b00
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#define PCI_DEVICE_ID_INTEL_3400_MOBILE 0x3b01
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#define PCI_DEVICE_ID_INTEL_P55 0x3b02
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#define PCI_DEVICE_ID_INTEL_PM55 0x3b03
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#define PCI_DEVICE_ID_INTEL_H55 0x3b06
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#define PCI_DEVICE_ID_INTEL_QM57 0x3b07
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#define PCI_DEVICE_ID_INTEL_H57 0x3b08
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#define PCI_DEVICE_ID_INTEL_HM55 0x3b09
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#define PCI_DEVICE_ID_INTEL_Q57 0x3b0a
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#define PCI_DEVICE_ID_INTEL_HM57 0x3b0b
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#define PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF 0x3b0d
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#define PCI_DEVICE_ID_INTEL_B55_A 0x3b0e
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#define PCI_DEVICE_ID_INTEL_QS57 0x3b0f
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#define PCI_DEVICE_ID_INTEL_3400 0x3b12
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#define PCI_DEVICE_ID_INTEL_3420 0x3b14
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#define PCI_DEVICE_ID_INTEL_3450 0x3b16
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#define PCI_DEVICE_ID_INTEL_B55_B 0x3b1e
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#define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119
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#define PCI_DEVICE_ID_INTEL_Z68 0x1c44
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#define PCI_DEVICE_ID_INTEL_P67 0x1c46
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#define PCI_DEVICE_ID_INTEL_UM67 0x1c47
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#define PCI_DEVICE_ID_INTEL_HM65 0x1c49
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#define PCI_DEVICE_ID_INTEL_H67 0x1c4a
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#define PCI_DEVICE_ID_INTEL_HM67 0x1c4b
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#define PCI_DEVICE_ID_INTEL_Q65 0x1c4c
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#define PCI_DEVICE_ID_INTEL_QS67 0x1c4d
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#define PCI_DEVICE_ID_INTEL_Q67 0x1c4e
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#define PCI_DEVICE_ID_INTEL_QM67 0x1c4f
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#define PCI_DEVICE_ID_INTEL_B65 0x1c50
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#define PCI_DEVICE_ID_INTEL_C202 0x1c52
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#define PCI_DEVICE_ID_INTEL_C204 0x1c54
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#define PCI_DEVICE_ID_INTEL_C206 0x1c56
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#define PCI_DEVICE_ID_INTEL_H61 0x1c5c
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#define PCI_DEVICE_ID_INTEL_Z77 0x1e44
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#define PCI_DEVICE_ID_INTEL_Z75 0x1e46
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#define PCI_DEVICE_ID_INTEL_Q77 0x1e47
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#define PCI_DEVICE_ID_INTEL_Q75 0x1e48
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#define PCI_DEVICE_ID_INTEL_B75 0x1e49
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#define PCI_DEVICE_ID_INTEL_H77 0x1e4a
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#define PCI_DEVICE_ID_INTEL_C216 0x1e53
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#define PCI_DEVICE_ID_INTEL_QM77 0x1e55
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#define PCI_DEVICE_ID_INTEL_QS77 0x1e56
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#define PCI_DEVICE_ID_INTEL_HM77 0x1e57
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#define PCI_DEVICE_ID_INTEL_UM77 0x1e58
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#define PCI_DEVICE_ID_INTEL_HM76 0x1e59
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#define PCI_DEVICE_ID_INTEL_HM75 0x1e5d
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#define PCI_DEVICE_ID_INTEL_HM70 0x1e5e
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#define PCI_DEVICE_ID_INTEL_NM70 0x1e5f
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45
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#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5
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#define PCI_DEVICE_ID_INTEL_82810 0x7120
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#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
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#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124
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#define PCI_DEVICE_ID_INTEL_82830M 0x3575
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#define PCI_DEVICE_ID_INTEL_82845 0x1a30
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#define PCI_DEVICE_ID_INTEL_82865 0x2570
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#define PCI_DEVICE_ID_INTEL_82915 0x2580
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#define PCI_DEVICE_ID_INTEL_82945P 0x2770
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#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
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#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac
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#define PCI_DEVICE_ID_INTEL_82946 0x2970
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#define PCI_DEVICE_ID_INTEL_82965PM 0x2a00
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#define PCI_DEVICE_ID_INTEL_82Q965 0x2990
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#define PCI_DEVICE_ID_INTEL_82975X 0x277c
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#define PCI_DEVICE_ID_INTEL_82Q35 0x29b0
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#define PCI_DEVICE_ID_INTEL_82G33 0x29c0
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#define PCI_DEVICE_ID_INTEL_82Q33 0x29d0
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#define PCI_DEVICE_ID_INTEL_82X38 0x29e0
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#define PCI_DEVICE_ID_INTEL_32X0 0x29f0
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#define PCI_DEVICE_ID_INTEL_82XX4X 0x2a40
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#define PCI_DEVICE_ID_INTEL_82Q45 0x2e10
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#define PCI_DEVICE_ID_INTEL_82G45 0x2e20
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#define PCI_DEVICE_ID_INTEL_82G41 0x2e30
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#define PCI_DEVICE_ID_INTEL_82B43 0x2e40
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#define PCI_DEVICE_ID_INTEL_82B43_2 0x2e90
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#define PCI_DEVICE_ID_INTEL_82X58 0x3405
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#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100
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#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000
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#define PCI_DEVICE_ID_INTEL_I63XX 0x2670
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#define PCI_DEVICE_ID_INTEL_I5000X 0x25c0
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#define PCI_DEVICE_ID_INTEL_I5000Z 0x25d0
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#define PCI_DEVICE_ID_INTEL_I5000V 0x25d4
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#define PCI_DEVICE_ID_INTEL_I5000P 0x25d8
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/* untested, but almost identical to D-series */
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#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010
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#define PCI_DEVICE_ID_INTEL_82443LX 0x7180
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/* 82443BX has a different device ID if AGP is disabled (hardware-wise). */
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#define PCI_DEVICE_ID_INTEL_82443BX 0x7190
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#define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192
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/* 82371AB/EB/MB use the same device ID value. */
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#define PCI_DEVICE_ID_INTEL_82371XX 0x7110
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/* Bay Trail */
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#define PCI_DEVICE_ID_INTEL_BAYTRAIL 0x0f00 /* SOC Transaction Router */
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#define PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC 0x0f1c
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#define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31
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#define CPUID_BAYTRAIL 0x30670
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/* Intel starts counting these generations with the integration of the DRAM controller */
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#define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */
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#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */
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#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D 0x0100 /* Sandy Bridge (Desktop) */
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#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M 0x0104 /* Sandy Bridge (Mobile) */
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#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3 0x0108 /* Sandy Bridge (Xeon E3) */
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#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D 0x0150 /* Ivy Bridge (Desktop) */
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#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M 0x0154 /* Ivy Bridge (Mobile) */
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#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3 0x0158 /* Ivy Bridge (Xeon E3 v2) */
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#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c 0x015c /* Ivy Bridge (?) */
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#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D 0x0c00 /* Haswell (Desktop) */
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#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M 0x0c04 /* Haswell (Mobile) */
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#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */
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#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */
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#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */
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#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
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#if !defined(__DARWIN__) && !defined(__FreeBSD__)
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typedef struct { uint32_t hi, lo; } msr_t;
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#endif
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#if defined (__FreeBSD__)
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/* FreeBSD already has conflicting definitions for wrmsr/rdmsr. */
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#undef rdmsr
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#undef wrmsr
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#define rdmsr freebsd_rdmsr
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#define wrmsr freebsd_wrmsr
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typedef struct { uint32_t hi, lo; } msr_t;
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msr_t freebsd_rdmsr(int addr);
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int freebsd_wrmsr(int addr, msr_t msr);
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#endif
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typedef struct { uint16_t addr; int size; char *name; } io_register_t;
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void *map_physical(uint64_t phys_addr, size_t len);
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void unmap_physical(void *virt_addr, size_t len);
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unsigned int cpuid(unsigned int op);
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int print_intel_core_msrs(void);
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int print_mchbar(struct pci_dev *nb, struct pci_access *pacc);
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int print_pmbase(struct pci_dev *sb, struct pci_access *pacc);
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int print_rcba(struct pci_dev *sb);
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int print_gpios(struct pci_dev *sb, int show_all, int show_diffs);
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int print_epbar(struct pci_dev *nb);
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int print_dmibar(struct pci_dev *nb);
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int print_pciexbar(struct pci_dev *nb);
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int print_ambs(struct pci_dev *nb, struct pci_access *pacc);
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int print_spi(struct pci_dev *sb);
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int print_gfx(struct pci_dev *gfx);
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void ivybridge_dump_timings(void);
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