35599f9a66
Recommonmark has been deprecated since 2021 [1] and the last release was
over 3 years ago [2]. As per their announcement, Markedly Structured
Text (MyST) Parser [3] is the recommended replacement.
For the most part, the existing documentation is compatible with MyST,
as both parsers are built around the CommonMark flavor of Markdown. The
main difference that affects coreboot is how the Sphinx toctree is
generated. Recommonmark has a feature called auto_toc_tree, which
converts single level lists of references into a toctree:
* [Part 1: Starting from scratch](part1.md)
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)
MyST Parser does not provide a replacement for this feature, meaning the
toctree must be defined manually. This is done using MyST's syntax for
Sphinx directives:
```{toctree}
:maxdepth: 1
Part 1: Starting from scratch <part1.md>
Part 2: Submitting a patch to coreboot.org <part2.md>
Part 3: Writing unit tests <part3.md>
Managing local additions <managing_local_additions.md>
Flashing firmware <flashing_firmware/index.md>
```
Internally, auto_toc_tree essentially converts lists of references into
the Sphinx toctree structure that the MyST syntax above more directly
represents.
The toctrees were converted to the MyST syntax using the following
command and Python script:
`find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py`
```
import re
import sys
in_list = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()
with open(sys.argv[1], "w") as f:
for line in lines:
match = re.match(r"^[-*+] \[(.*)\]\((.*)\)$", line)
if match is not None:
if not in_list:
in_list = True
f.write("```{toctree}\n")
f.write(":maxdepth: 1\n\n")
f.write(match.group(1) + " <" + match.group(2) + ">\n")
else:
if in_list:
f.write("```\n")
f.write(line)
in_list = False
if in_list:
f.write("```\n")
```
While this does add a little more work for creating the toctree, this
does give more control over exactly what goes into the toctree. For
instance, lists of links to external resources currently end up in the
toctree, but we may want to limit it to pages within coreboot.
This change does break rendering and navigation of the documentation in
applications that can render Markdown, such as Okular, Gitiles, or the
GitHub mirror. Assuming the docs are mainly intended to be viewed after
being rendered to doc.coreboot.org, this is probably not an issue in
practice.
Another difference is that MyST natively supports Markdown tables,
whereas with Recommonmark, tables had to be written in embedded rST [4].
However, MyST also supports embedded rST, so the existing tables can be
easily converted as the syntax is nearly identical.
These were converted using
`find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"`
Makefile.sphinx and conf.py were regenerated from scratch by running
`sphinx-quickstart` using the updated version of Sphinx, which removes a
lot of old commented out boilerplate. Any relevant changes coreboot had
made on top of the previous autogenerated versions of these files were
ported over to the newly generated file.
From some initial testing the generated webpages appear and function
identically to the existing documentation built with Recommonmark.
TEST: `make -C util/docker docker-build-docs` builds the documentation
successfully and the generated output renders properly when viewed in
a web browser.
[1] https://github.com/readthedocs/recommonmark/issues/221
[2] https://pypi.org/project/recommonmark/
[3] https://myst-parser.readthedocs.io/en/latest/
[4] https://doc.coreboot.org/getting_started/writing_documentation.html
Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
4.3 KiB
4.3 KiB
Libretrend LT1000
This page describes how to run coreboot on the Libretrend LT1000 (aka Librebox).
Required proprietary blobs
To build a minimal working coreboot image some blobs are required (assuming only the BIOS region is being modified).
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+
| FSP-M, FSP-S | Intel Firmware Support Package | Required |
+-----------------+---------------------------------+---------------------+
| microcode | CPU microcode | Required |
+-----------------+---------------------------------+---------------------+
FSP-M and FSP-S are obtained after splitting the Kaby Lake FSP binary (done automatically by coreboot build system and included into the image) from the 3rdparty/fsp submodule.
Microcode updates are automatically included into the coreboot image by build system from the 3rdparty/intel-microcode submodule.
The mainboard code also contains a VBT file (version 1.00, BDB version 2.09) which is automatically included into the image by coreboot build system.
Flashing coreboot
Internal programming
The main SPI flash can be accessed using flashrom. It is strongly advised to flash only the BIOS region if not having an external programmer, see known issues.
External programming
The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip. This chip is located on the top middle side of the board near the CPU fan, between the DIMM slots and the M.2 disk. Use a clip (or solder the wires) to program the chip. Specifically, it's a Winbond W25Q64FV (3.3V) - datasheet.
Known issues
- Fastboot (MRC cache) is not working reliably (missing schematics for CPU to DIMM wiring).
- Flashing ME region with already cleaned ME firmware may lead to platform not booting, flashing full ME firmware is needed to recover.
- In order to have the USB device wake support from S3 state using the front USB 3.0 ports, one has to move the jumper on DUSB1_PWR_SET header (it will switch the power rails for the USB 3.0 ports).
- There are 6 unknown GPIO pins on the board.
Untested
Not all mainboard's peripherals and functions were tested because of lack of the cables or not being populated on the board case.
- LVDS header
- Onboard USB 2.0 and USB 3.0 headers
- Speakers and mic header
- SPDIF header
- Audio header
- PS/2 header
- LPT header
- CIR (infrared header)
- COM2 port RS485 mode (RS232/RS485 mode is controlled via jumper)
- SYS_FAN header
Working
- USB
- Ethernet
- Integrated graphics (with libgfxinit) on VGA and HDMI ports
- flashrom
- PCIe
- NVMe
- WiFi and Bluetooth
- SATA
- Serial ports 1-6
- SMBus
- HDA (verbs not implemented yet, but works under GNU/Linux (4.15 tested))
- Initialization with KBL FSP 2.0
- SeaBIOS payload (version rel-1.13.0)
- TPM2 (custom module connected to LPC DEBUG header)
- Automatic fan control
- Platform boots with cleaned ME (MFS partition must be left on SPI flash)
Technology
The platform contains an LR-i7S65T1 baseboard (LR-i7S65T2 with two NICs not sold yet). More details on baseboard site. Unfortunately the board manual is not publicly available.
+------------------+--------------------------------------------------+
| CPU | Intel Core i7-6500U |
+------------------+--------------------------------------------------+
| PCH | Skylake-U Premium |
+------------------+--------------------------------------------------+
| Super I/O | ITE IT8786E |
+------------------+--------------------------------------------------+
| Coprocessor | Intel Management Engine |
+------------------+--------------------------------------------------+