35599f9a66
Recommonmark has been deprecated since 2021 [1] and the last release was
over 3 years ago [2]. As per their announcement, Markedly Structured
Text (MyST) Parser [3] is the recommended replacement.
For the most part, the existing documentation is compatible with MyST,
as both parsers are built around the CommonMark flavor of Markdown. The
main difference that affects coreboot is how the Sphinx toctree is
generated. Recommonmark has a feature called auto_toc_tree, which
converts single level lists of references into a toctree:
* [Part 1: Starting from scratch](part1.md)
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)
MyST Parser does not provide a replacement for this feature, meaning the
toctree must be defined manually. This is done using MyST's syntax for
Sphinx directives:
```{toctree}
:maxdepth: 1
Part 1: Starting from scratch <part1.md>
Part 2: Submitting a patch to coreboot.org <part2.md>
Part 3: Writing unit tests <part3.md>
Managing local additions <managing_local_additions.md>
Flashing firmware <flashing_firmware/index.md>
```
Internally, auto_toc_tree essentially converts lists of references into
the Sphinx toctree structure that the MyST syntax above more directly
represents.
The toctrees were converted to the MyST syntax using the following
command and Python script:
`find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py`
```
import re
import sys
in_list = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()
with open(sys.argv[1], "w") as f:
for line in lines:
match = re.match(r"^[-*+] \[(.*)\]\((.*)\)$", line)
if match is not None:
if not in_list:
in_list = True
f.write("```{toctree}\n")
f.write(":maxdepth: 1\n\n")
f.write(match.group(1) + " <" + match.group(2) + ">\n")
else:
if in_list:
f.write("```\n")
f.write(line)
in_list = False
if in_list:
f.write("```\n")
```
While this does add a little more work for creating the toctree, this
does give more control over exactly what goes into the toctree. For
instance, lists of links to external resources currently end up in the
toctree, but we may want to limit it to pages within coreboot.
This change does break rendering and navigation of the documentation in
applications that can render Markdown, such as Okular, Gitiles, or the
GitHub mirror. Assuming the docs are mainly intended to be viewed after
being rendered to doc.coreboot.org, this is probably not an issue in
practice.
Another difference is that MyST natively supports Markdown tables,
whereas with Recommonmark, tables had to be written in embedded rST [4].
However, MyST also supports embedded rST, so the existing tables can be
easily converted as the syntax is nearly identical.
These were converted using
`find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"`
Makefile.sphinx and conf.py were regenerated from scratch by running
`sphinx-quickstart` using the updated version of Sphinx, which removes a
lot of old commented out boilerplate. Any relevant changes coreboot had
made on top of the previous autogenerated versions of these files were
ported over to the newly generated file.
From some initial testing the generated webpages appear and function
identically to the existing documentation built with Recommonmark.
TEST: `make -C util/docker docker-build-docs` builds the documentation
successfully and the generated output renders properly when viewed in
a web browser.
[1] https://github.com/readthedocs/recommonmark/issues/221
[2] https://pypi.org/project/recommonmark/
[3] https://myst-parser.readthedocs.io/en/latest/
[4] https://doc.coreboot.org/getting_started/writing_documentation.html
Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2.8 KiB
2.8 KiB
Display Panel Specifics
Timing Parameters
From the binary file edid in the sys filesystem on Linux, the panel can be
identified. The exact path may differ slightly. Here is an example:
$ strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid
@0 5
LG Display
LP140WF3-SPD1
To figure out the timing parameters, refer to the Intel Programmer's Reference
Manuals
and try to find the datasheet of the panel using the information from edid.
In the example above, you would search for LP140WF3-SPD1. Find a table listing
the power sequence timing parameters, which are usually named T[N] and also
referenced in Intel's respective registers listing. You need the values for
PP_ON_DELAYS, PP_OFF_DELAYS and PP_DIVISOR for your devicetree.cb:
+-----------------------------+---------------------------------------+-----+
| Intel docs | devicetree.cb | eDP |
+-----------------------------+---------------------------------------+-----+
| Power up delay | `gpu_panel_power_up_delay` | T3 |
+-----------------------------+---------------------------------------+-----+
| Power on to backlight on | `gpu_panel_power_backlight_on_delay` | T7 |
+-----------------------------+---------------------------------------+-----+
| Power Down delay | `gpu_panel_power_down_delay` | T10 |
+-----------------------------+---------------------------------------+-----+
| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9 |
+-----------------------------+---------------------------------------+-----+
| Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 |
+-----------------------------+---------------------------------------+-----+
Intel GPU Tools and VBT
The Intel GPU tools are in a package called either intel-gpu-tools or
igt-gpu-tools in most distributions of Linux-based operating systems.
In the coreboot util/ directory, you can find intelvbttool.
From a running system, you can dump the register values directly:
$ intel_reg dump --all | grep PCH_PP
PCH_PP_STATUS (0x000c7200): 0x80000008
PCH_PP_CONTROL (0x000c7204): 0x00000007
PCH_PP_ON_DELAYS (0x000c7208): 0x07d00001
PCH_PP_OFF_DELAYS (0x000c720c): 0x01f40001
PCH_PP_DIVISOR (0x000c7210): 0x0004af06
You can obtain the timing values from a VBT (Video BIOS Table), which you can dump from a vendor UEFI image:
$ intel_vbt_decode data.vbt | grep T3
Power Sequence: T3 2000 T7 10 T9 2000 T10 500 T12 5000
T3 optimization: no