35599f9a66
Recommonmark has been deprecated since 2021 [1] and the last release was
over 3 years ago [2]. As per their announcement, Markedly Structured
Text (MyST) Parser [3] is the recommended replacement.
For the most part, the existing documentation is compatible with MyST,
as both parsers are built around the CommonMark flavor of Markdown. The
main difference that affects coreboot is how the Sphinx toctree is
generated. Recommonmark has a feature called auto_toc_tree, which
converts single level lists of references into a toctree:
* [Part 1: Starting from scratch](part1.md)
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)
MyST Parser does not provide a replacement for this feature, meaning the
toctree must be defined manually. This is done using MyST's syntax for
Sphinx directives:
```{toctree}
:maxdepth: 1
Part 1: Starting from scratch <part1.md>
Part 2: Submitting a patch to coreboot.org <part2.md>
Part 3: Writing unit tests <part3.md>
Managing local additions <managing_local_additions.md>
Flashing firmware <flashing_firmware/index.md>
```
Internally, auto_toc_tree essentially converts lists of references into
the Sphinx toctree structure that the MyST syntax above more directly
represents.
The toctrees were converted to the MyST syntax using the following
command and Python script:
`find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py`
```
import re
import sys
in_list = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()
with open(sys.argv[1], "w") as f:
for line in lines:
match = re.match(r"^[-*+] \[(.*)\]\((.*)\)$", line)
if match is not None:
if not in_list:
in_list = True
f.write("```{toctree}\n")
f.write(":maxdepth: 1\n\n")
f.write(match.group(1) + " <" + match.group(2) + ">\n")
else:
if in_list:
f.write("```\n")
f.write(line)
in_list = False
if in_list:
f.write("```\n")
```
While this does add a little more work for creating the toctree, this
does give more control over exactly what goes into the toctree. For
instance, lists of links to external resources currently end up in the
toctree, but we may want to limit it to pages within coreboot.
This change does break rendering and navigation of the documentation in
applications that can render Markdown, such as Okular, Gitiles, or the
GitHub mirror. Assuming the docs are mainly intended to be viewed after
being rendered to doc.coreboot.org, this is probably not an issue in
practice.
Another difference is that MyST natively supports Markdown tables,
whereas with Recommonmark, tables had to be written in embedded rST [4].
However, MyST also supports embedded rST, so the existing tables can be
easily converted as the syntax is nearly identical.
These were converted using
`find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"`
Makefile.sphinx and conf.py were regenerated from scratch by running
`sphinx-quickstart` using the updated version of Sphinx, which removes a
lot of old commented out boilerplate. Any relevant changes coreboot had
made on top of the previous autogenerated versions of these files were
ported over to the newly generated file.
From some initial testing the generated webpages appear and function
identically to the existing documentation built with Recommonmark.
TEST: `make -C util/docker docker-build-docs` builds the documentation
successfully and the generated output renders properly when viewed in
a web browser.
[1] https://github.com/readthedocs/recommonmark/issues/221
[2] https://pypi.org/project/recommonmark/
[3] https://myst-parser.readthedocs.io/en/latest/
[4] https://doc.coreboot.org/getting_started/writing_documentation.html
Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
5.3 KiB
HP Compaq 8200 Elite SFF
This page describes how to run coreboot on the Compaq 8200 Elite SFF desktop from HP.
TODO
The following things are still missing from this coreboot port:
- Extended HWM reporting
- Advanced LED control
- Advanced power configuration in S3
Flashing coreboot
+---------------------+-------------------------+
| Type | Value |
+=====================+=========================+
| Socketed flash | no |
+---------------------+-------------------------+
| Model | MX25L6406E/MX25L6408E |
+---------------------+-------------------------+
| Size | 8 MiB |
+---------------------+-------------------------+
| In circuit flashing | yes |
+---------------------+-------------------------+
| Package | SOIC-8 |
+---------------------+-------------------------+
| Write protection | bios region |
+---------------------+-------------------------+
| Dual BIOS feature | No |
+---------------------+-------------------------+
| Internal flashing | yes |
+---------------------+-------------------------+
Flash layout
The original layout of the flash should look like this:
00000000:00000fff fd
00510000:007fffff bios
00003000:0050ffff me
00001000:00002fff gbe
Internal programming
The SPI flash can be accessed using flashrom.
$ flashrom -p internal -c MX25L6406E/MX25L6408E -w coreboot.rom
After shorting the FDO jumper you gain access to the full flash, but you still cannot write in the bios region due to SPI protected ranges.
Position of FDO jumper close to the IO and second fan connector
To write to the bios region you can use an IFD Hack originally developed for MacBooks, but with modified values described in this guide. You should read both guides before attempting the procedure.
Since you can still write in the flash descriptor, you can shrink the ME and then move the bios region into where the ME originally was. coreboot does not by default restrict writing to any part of the flash, so you will first flash a small coreboot build and after it boots, flash the full one.
The temporary flash layout with the neutered ME firmware should look like this:
00000000:00000fff fd
00023000:001fffff bios
00003000:00022fff me
00001000:00002fff gbe
00200000:007fffff pd
It is very important to use these exact numbers or you will need to fix it using external flashing, but you should already be familiar with the risks if you got this far.
The temporary ROM chip size to set in menuconfig is 2 MB but the default CBFS size is too large for that, you can use up to about 0x1D0000.
When building both the temporary and the permanent installation, don't forget to also add the gigabit ethernet configuration when adding the flash descriptor and ME firmware.
You can pad the ROM to the required 8MB with zeros using:
$ dd if=/dev/zero of=6M.bin bs=1024 count=6144
$ cat coreboot.rom 6M.bin > coreboot8.rom
If you want to continue using the neutered ME firmware use this flash layout for stage 2:
00000000:00000fff fd
00023000:007fffff bios
00003000:00022fff me
00001000:00002fff gbe
If you want to use the original ME firmware use the original flash layout.
More about flashing internally and getting the flash layout here.
External programming
External programming with an SPI adapter and flashrom does work, but it powers the whole southbridge complex. You need to supply enough current through the programming adapter.
If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder, as otherwise there's not enough space near the flash.
Position of SOIC-8 flash IC near 2nd DIMM holder
Closeup view of SOIC-8 flash IC
Technology
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+
| Southbridge | bd82x6x |
+------------------+--------------------------------------------------+
| CPU | model_206ax |
+------------------+--------------------------------------------------+
| SuperIO | :doc:`../../superio/nuvoton/npcd378` |
+------------------+--------------------------------------------------+
| EC | |
+------------------+--------------------------------------------------+
| Coprocessor | Intel ME |
+------------------+--------------------------------------------------+