556373e354
Since the code for reporting the memory map below cbmem_top is basically identical for all non-CAR AMD SoCs, factor this out into a common read_lower_soc_memmap_resources implementation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id64462b97d144ccdf78ebb051d82a4aa37f8ee98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81389 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
72 lines
1.9 KiB
C
72 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpigen_pci.h>
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#include <amdblocks/ioapic.h>
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#include <amdblocks/data_fabric.h>
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#include <amdblocks/memmap.h>
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#include <amdblocks/root_complex.h>
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#include <amdblocks/smn.h>
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#include <arch/ioapic.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <types.h>
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#include <vendorcode/amd/opensil/genoa_poc/opensil.h>
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#define IOHC_IOAPIC_BASE_ADDR_LO 0x2f0
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void read_soc_memmap_resources(struct device *domain, unsigned long *idx)
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{
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read_lower_soc_memmap_resources(domain, idx);
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add_opensil_memmap(domain, idx);
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}
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static void genoa_domain_set_resources(struct device *domain)
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{
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if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
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printk(BIOS_DEBUG, "Setting VGA decoding for domain 0x%x\n",
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domain->path.domain.domain);
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const union df_vga_en vga_en = {
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.ve = 1,
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.dst_fabric_id = get_iohc_fabric_id(domain),
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};
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data_fabric_broadcast_write32(DF_VGA_EN, vga_en.raw);
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}
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pci_domain_set_resources(domain);
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/* Enable IOAPIC memory decoding */
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struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX);
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if (res) {
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const uint32_t iohc_misc_base = get_iohc_misc_smn_base(domain);
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uint32_t ioapic_base = smn_read32(iohc_misc_base | IOHC_IOAPIC_BASE_ADDR_LO);
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ioapic_base |= (1 << 0);
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smn_write32(iohc_misc_base | IOHC_IOAPIC_BASE_ADDR_LO, ioapic_base);
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}
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}
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static const char *genoa_domain_acpi_name(const struct device *domain)
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{
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const char *domain_acpi_names[4] = {
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"S0B0",
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"S0B1",
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"S0B2",
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"S0B3",
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};
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if (domain->path.domain.domain < ARRAY_SIZE(domain_acpi_names))
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return domain_acpi_names[domain->path.domain.domain];
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return NULL;
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}
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struct device_operations genoa_pci_domain_ops = {
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.read_resources = amd_pci_domain_read_resources,
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.set_resources = genoa_domain_set_resources,
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.scan_bus = amd_pci_domain_scan_bus,
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.init = amd_pci_domain_init,
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.acpi_name = genoa_domain_acpi_name,
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.acpi_fill_ssdt = pci_domain_fill_ssdt,
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};
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