88ded318c3
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Yul Rottmann <yulrottmann@bitel.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
281 lines
7.5 KiB
C
281 lines
7.5 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
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* Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
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* Copyright (C) 2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* Contains the ITE IT87* SPI specific routines
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*/
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#include <stdio.h>
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#include <pci/pci.h>
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#include <stdint.h>
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#include <string.h>
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#include "flash.h"
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#include "spi.h"
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#define ITE_SUPERIO_PORT1 0x2e
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#define ITE_SUPERIO_PORT2 0x4e
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uint16_t it8716f_flashport = 0;
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/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
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int fast_spi = 1;
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/* Generic Super I/O helper functions */
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uint8_t regval(uint16_t port, uint8_t reg)
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{
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OUTB(reg, port);
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return INB(port + 1);
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}
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void regwrite(uint16_t port, uint8_t reg, uint8_t val)
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{
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OUTB(reg, port);
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OUTB(val, port + 1);
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}
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/* Helper functions for most recent ITE IT87xx Super I/O chips */
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#define CHIP_ID_BYTE1_REG 0x20
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#define CHIP_ID_BYTE2_REG 0x21
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static void enter_conf_mode_ite(uint16_t port)
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{
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OUTB(0x87, port);
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OUTB(0x01, port);
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OUTB(0x55, port);
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if (port == ITE_SUPERIO_PORT1)
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OUTB(0x55, port);
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else
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OUTB(0xaa, port);
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}
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static void exit_conf_mode_ite(uint16_t port)
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{
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regwrite(port, 0x02, 0x02);
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}
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static uint16_t find_ite_spi_flash_port(uint16_t port)
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{
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uint8_t tmp = 0;
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uint16_t id, flashport = 0;
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enter_conf_mode_ite(port);
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id = regval(port, CHIP_ID_BYTE1_REG) << 8;
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id |= regval(port, CHIP_ID_BYTE2_REG);
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/* TODO: Handle more IT87xx if they support flash translation */
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if (0x8716 == id || 0x8718 == id) {
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/* NOLDN, reg 0x24, mask out lowest bit (suspend) */
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tmp = regval(port, 0x24) & 0xFE;
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printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
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0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
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printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
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0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
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printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
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0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
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printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
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0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
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printf("LPC write to serial flash %sabled\n",
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(tmp & 1 << 4) ? "en" : "dis");
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/* If any serial flash segment is enabled, enable writing. */
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if ((tmp & 0xe) && (!(tmp & 1 << 4))) {
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printf("Enabling LPC write to serial flash\n");
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tmp |= 1 << 4;
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regwrite(port, 0x24, tmp);
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}
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printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
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/* LDN 0x7, reg 0x64/0x65 */
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regwrite(port, 0x07, 0x7);
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flashport = regval(port, 0x64) << 8;
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flashport |= regval(port, 0x65);
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}
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exit_conf_mode_ite(port);
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return flashport;
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}
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int it87xx_probe_spi_flash(const char *name)
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{
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it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT1);
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if (!it8716f_flashport)
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it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT2);
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if (it8716f_flashport)
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flashbus = BUS_TYPE_IT87XX_SPI;
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return (!it8716f_flashport);
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}
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/*
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* The IT8716F only supports commands with length 1,2,4,5 bytes including
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* command byte and can not read more than 3 bytes from the device.
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*
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* This function expects writearr[0] to be the first byte sent to the device,
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* whereas the IT8716F splits commands internally into address and non-address
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* commands with the address in inverse wire order. That's why the register
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* ordering in case 4 and 5 may seem strange.
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*/
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int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr)
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{
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uint8_t busy, writeenc;
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int i;
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do {
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busy = INB(it8716f_flashport) & 0x80;
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} while (busy);
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if (readcnt > 3) {
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printf("%s called with unsupported readcnt %i.\n",
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__FUNCTION__, readcnt);
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return 1;
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}
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switch (writecnt) {
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case 1:
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OUTB(writearr[0], it8716f_flashport + 1);
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writeenc = 0x0;
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break;
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case 2:
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OUTB(writearr[0], it8716f_flashport + 1);
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OUTB(writearr[1], it8716f_flashport + 7);
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writeenc = 0x1;
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break;
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case 4:
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OUTB(writearr[0], it8716f_flashport + 1);
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OUTB(writearr[1], it8716f_flashport + 4);
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OUTB(writearr[2], it8716f_flashport + 3);
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OUTB(writearr[3], it8716f_flashport + 2);
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writeenc = 0x2;
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break;
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case 5:
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OUTB(writearr[0], it8716f_flashport + 1);
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OUTB(writearr[1], it8716f_flashport + 4);
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OUTB(writearr[2], it8716f_flashport + 3);
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OUTB(writearr[3], it8716f_flashport + 2);
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OUTB(writearr[4], it8716f_flashport + 7);
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writeenc = 0x3;
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break;
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default:
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printf("%s called with unsupported writecnt %i.\n",
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__FUNCTION__, writecnt);
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return 1;
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}
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/*
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* Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes.
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* Note:
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* We can't use writecnt directly, but have to use a strange encoding.
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*/
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OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4)
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| ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport);
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if (readcnt > 0) {
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do {
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busy = INB(it8716f_flashport) & 0x80;
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} while (busy);
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for (i = 0; i < readcnt; i++)
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readarr[i] = INB(it8716f_flashport + 5 + i);
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}
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return 0;
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}
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/* Page size is usually 256 bytes */
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static void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios)
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{
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int i;
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spi_write_enable();
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OUTB(0x06, it8716f_flashport + 1);
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OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
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for (i = 0; i < 256; i++) {
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bios[256 * block + i] = buf[256 * block + i];
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}
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OUTB(0, it8716f_flashport);
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/* Wait until the Write-In-Progress bit is cleared.
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* This usually takes 1-10 ms, so wait in 1 ms steps.
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*/
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while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
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usleep(1000);
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}
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/*
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* IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
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* Program chip using firmware cycle byte programming. (SLOW!)
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*/
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int it8716f_over512k_spi_chip_write(struct flashchip *flash, uint8_t *buf)
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{
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int total_size = 1024 * flash->total_size;
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int i;
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fast_spi = 0;
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spi_disable_blockprotect();
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for (i = 0; i < total_size; i++) {
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spi_write_enable();
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spi_byte_program(i, buf[i]);
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while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
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myusec_delay(10);
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}
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/* resume normal ops... */
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OUTB(0x20, it8716f_flashport);
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return 0;
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}
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/*
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* IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
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* Need to read this big flash using firmware cycles 3 byte at a time.
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*/
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int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf)
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{
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int total_size = 1024 * flash->total_size;
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int i;
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fast_spi = 0;
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if (total_size > 512 * 1024) {
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for (i = 0; i < total_size; i += 3) {
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int toread = 3;
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if (total_size - i < toread)
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toread = total_size - i;
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spi_nbyte_read(i, buf + i, toread);
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}
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} else {
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memcpy(buf, (const char *)flash->virtual_memory, total_size);
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}
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return 0;
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}
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int it8716f_spi_chip_write(struct flashchip *flash, uint8_t *buf)
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{
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int total_size = 1024 * flash->total_size;
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int i;
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if (total_size > 512 * 1024) {
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it8716f_over512k_spi_chip_write(flash, buf);
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} else {
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for (i = 0; i < total_size / 256; i++) {
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it8716f_spi_page_program(i, buf,
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(uint8_t *)flash->virtual_memory);
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}
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}
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return 0;
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}
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