35599f9a66
Recommonmark has been deprecated since 2021 [1] and the last release was
over 3 years ago [2]. As per their announcement, Markedly Structured
Text (MyST) Parser [3] is the recommended replacement.
For the most part, the existing documentation is compatible with MyST,
as both parsers are built around the CommonMark flavor of Markdown. The
main difference that affects coreboot is how the Sphinx toctree is
generated. Recommonmark has a feature called auto_toc_tree, which
converts single level lists of references into a toctree:
* [Part 1: Starting from scratch](part1.md)
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)
MyST Parser does not provide a replacement for this feature, meaning the
toctree must be defined manually. This is done using MyST's syntax for
Sphinx directives:
```{toctree}
:maxdepth: 1
Part 1: Starting from scratch <part1.md>
Part 2: Submitting a patch to coreboot.org <part2.md>
Part 3: Writing unit tests <part3.md>
Managing local additions <managing_local_additions.md>
Flashing firmware <flashing_firmware/index.md>
```
Internally, auto_toc_tree essentially converts lists of references into
the Sphinx toctree structure that the MyST syntax above more directly
represents.
The toctrees were converted to the MyST syntax using the following
command and Python script:
`find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py`
```
import re
import sys
in_list = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()
with open(sys.argv[1], "w") as f:
for line in lines:
match = re.match(r"^[-*+] \[(.*)\]\((.*)\)$", line)
if match is not None:
if not in_list:
in_list = True
f.write("```{toctree}\n")
f.write(":maxdepth: 1\n\n")
f.write(match.group(1) + " <" + match.group(2) + ">\n")
else:
if in_list:
f.write("```\n")
f.write(line)
in_list = False
if in_list:
f.write("```\n")
```
While this does add a little more work for creating the toctree, this
does give more control over exactly what goes into the toctree. For
instance, lists of links to external resources currently end up in the
toctree, but we may want to limit it to pages within coreboot.
This change does break rendering and navigation of the documentation in
applications that can render Markdown, such as Okular, Gitiles, or the
GitHub mirror. Assuming the docs are mainly intended to be viewed after
being rendered to doc.coreboot.org, this is probably not an issue in
practice.
Another difference is that MyST natively supports Markdown tables,
whereas with Recommonmark, tables had to be written in embedded rST [4].
However, MyST also supports embedded rST, so the existing tables can be
easily converted as the syntax is nearly identical.
These were converted using
`find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"`
Makefile.sphinx and conf.py were regenerated from scratch by running
`sphinx-quickstart` using the updated version of Sphinx, which removes a
lot of old commented out boilerplate. Any relevant changes coreboot had
made on top of the previous autogenerated versions of these files were
ported over to the newly generated file.
From some initial testing the generated webpages appear and function
identically to the existing documentation built with Recommonmark.
TEST: `make -C util/docker docker-build-docs` builds the documentation
successfully and the generated output renders properly when viewed in
a web browser.
[1] https://github.com/readthedocs/recommonmark/issues/221
[2] https://pypi.org/project/recommonmark/
[3] https://myst-parser.readthedocs.io/en/latest/
[4] https://doc.coreboot.org/getting_started/writing_documentation.html
Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
5.0 KiB
PC Engines APU2
This page describes how to run coreboot on PC Engines APU2 platform.
Technology
+------------+---------------------------------------------------------------+
| CPU | AMD G series GX-412TC |
+------------+---------------------------------------------------------------+
| CPU core | 1 GHz quad Puma core with 64 bit support |
| | 32K data + 32K instruction cache per core, shared 2MB L2 cache|
+------------+---------------------------------------------------------------+
| DRAM | 2 or 4 GB DDR3-1333 DRAM |
+------------+---------------------------------------------------------------+
| Boot | From SD card, USB, mSATA SSD, SATA |
+------------+---------------------------------------------------------------+
| Power | 6 to 12W of 12V power |
+------------+---------------------------------------------------------------+
| Firmware | coreboot with support for iPXE and USB boot |
+------------+---------------------------------------------------------------+
Required proprietary blobs
To build working coreboot image some blobs are needed.
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+
| amdfw.rom* | AMD Platform Security Processor | Required |
+-----------------+---------------------------------+---------------------+
| AGESA.bin | AGESA Platform Initialization | Required |
+-----------------+---------------------------------+---------------------+
| xhci.bin | AMD XHCI controller | Optional |
+-----------------+---------------------------------+---------------------+
(*) - package containing all required blobs for PSP. Directory, in which all blobs are listed and available is: 3rdparty/southbridge/amd/avalon/PSP
Flashing coreboot
+---------------------+--------------------------+
| Type | Value |
+=====================+==========================+
| Socketed flash | no |
+---------------------+--------------------------+
| Model | W25Q64 |
+---------------------+--------------------------+
| Size | 8 MiB |
+---------------------+--------------------------+
| Package | SOIC-8 |
+---------------------+--------------------------+
| Write protection | jumper on WP# pin* |
+---------------------+--------------------------+
| Dual BIOS feature | no |
+---------------------+--------------------------+
| Internal flashing | yes |
+---------------------+--------------------------+
(*) - It is used in normal SPI mode, but can be dangerous when using Quad SPI Flash. Then, pull-down resistors should be considered rather than jumper.
Internal programming
The SPI flash can be accessed using flashrom.
flashrom -p internal -w coreboot.rom
External programming
IMPORTANT: When programming SPI flash, first you need to enter apu2 in S5 (Soft-off) power state. S5 state can be forced by shorting power button pin on J2 header.
The external access to flash chip is available through standard SOP-8 clip or SOP-8 header next to the flash chip on the board. Notice that not all boards have a header soldered down originally. Hence, there could be an empty slot with 8 eyelets, so you can solder down a header on your own. The SPI flash chip and SPI header are marked in the picture below. Also there is SPI header and SPI flash pin layout included. Depend on using header or clip there are important rules:
- using header J6 - don't connect 1,7,8 pins
- using clip U23 - don't connect 3,7,8 pins
Also signatures at the schematic can be ambiguous:
- J6 SPIDI = U23 SO = MISO
- J6 SPIDO = U23 SI = MOSI
There is no restrictions as to the programmer device. It is only recommended to flash firmware without supplying power. External programming can be performed, for example using OrangePi and Armbian. You can exploit linux_spi driver which provides communication with SPI devices. Example command to program SPI flash with OrangePi using linux_spi:
flashrom -f -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000
apu2 platform with marked in SPI header and SPI flash chip
SPI header pin layout
Schematics
PC Engines APU2 platform schematics are available for free on PC Engines official site. Both configurations (2GB/4GB) have the same PCB and schematic.