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6cd2c2f6ff792d1a170cd090e3347cfe2e14ac15
system76-coreboot/src/northbridge/intel
History
Felix Held 6cd2c2f6ff northbridge/x4x: add MCHBAR AND/OR/AND_OR access macros
Change-Id: Ie95321f3eb6fb17b17eb25e8a54670654c373706
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30 19:10:02 +00:00
..
e7505
nb/intel/e7505: Leave ROM as un-cacheable in postcar
2018-06-20 19:00:07 +00:00
fsp_rangeley
src/northbridge: Use "foo *bar" instead of "foo* bar"
2018-07-09 09:29:53 +00:00
fsp_sandybridge
src/northbridge: Use "foo *bar" instead of "foo* bar"
2018-07-09 09:29:53 +00:00
gm45
src/northbridge: Use "foo *bar" instead of "foo* bar"
2018-07-09 09:29:53 +00:00
haswell
src/nb: Fix non-local header treated as local
2018-07-02 07:39:16 +00:00
i440bx
nb/intel/i440bx: Switch to POSTCAR_STAGE
2018-06-17 19:17:11 +00:00
i945
nb/i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMs
2018-07-12 11:52:52 +00:00
nehalem
northbridge/nehalem: add MCHBAR AND/OR/AND_OR macros
2018-07-30 12:33:36 +00:00
pineview
src/northbridge: Use "foo *bar" instead of "foo* bar"
2018-07-09 09:29:53 +00:00
sandybridge
sandybridge/raminit_common: use MCHBAR32 macro everywhere
2018-07-29 18:06:44 +00:00
x4x
northbridge/x4x: add MCHBAR AND/OR/AND_OR access macros
2018-07-30 19:10:02 +00:00
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