Felix Held 6cd2c2f6ff northbridge/x4x: add MCHBAR AND/OR/AND_OR access macros ...

Change-Id: Ie95321f3eb6fb17b17eb25e8a54670654c373706
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

2018-07-30 19:10:02 +00:00

..

acpi

sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables

2018-06-29 07:45:30 +00:00

acpi.c

nb/x4x: Get rid of device_t

2018-04-30 09:22:32 +00:00

bootblock.c

nb/intel/x4x: Fix issues found by checkpatch.pl

2017-03-21 20:11:15 +01:00

chip.h

northbridge/intel/x4x: Intel 4-series northbridge support

2015-12-29 18:03:33 +01:00

dq_dqs.c

nb/intel/x4x: Implement write leveling

2018-05-24 13:03:45 +00:00

early_init.c

nb/intel/x4x: Change memory layout to improve MTRR

2018-05-01 17:42:30 +00:00

gma.c

nb/intel/x4x: Deprecate native graphic init

2018-06-14 09:40:55 +00:00

iomap.h

nb/intel/x4x: Fix issues found by checkpatch.pl

2017-03-21 20:11:15 +01:00

Kconfig

nb/intel/x4x: Deprecate native graphic init

2018-06-14 09:40:55 +00:00

Makefile.inc

nb/intel/x4x: Switch to POSTCAR_STAGE

2018-06-05 07:49:20 +00:00

northbridge.c

sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables

2018-06-29 07:45:30 +00:00

ram_calc.c

nb/intel/x4x: Switch to POSTCAR_STAGE

2018-06-05 07:49:20 +00:00

raminit_ddr23.c

nb/intel/x4x: Fix a few things in set_enhanced_mode

2018-06-14 09:37:50 +00:00

raminit_tables.c

nb/intel/x4x: Adapt post JEDEC for DDR3

2018-05-24 13:05:32 +00:00

raminit.c

nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset

2018-06-17 14:17:31 +00:00

rcven.c

nb/intel/x4x/rcven.c: Change the verbosity of some messages

2018-04-17 10:41:57 +00:00

x4x.h

northbridge/x4x: add MCHBAR AND/OR/AND_OR access macros

2018-07-30 19:10:02 +00:00