2d33dc4096
Signed-off-by: Björn Busse <bj.rn@co-assembler.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
112 lines
3.2 KiB
C
112 lines
3.2 KiB
C
/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008-2010 by coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include "inteltool.h"
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/*
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* (G)MCH MMIO Config Space
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*/
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int print_mchbar(struct pci_dev *nb)
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{
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int i, size = (16 * 1024);
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volatile uint8_t *mchbar;
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uint64_t mchbar_phys;
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printf("\n============= MCHBAR ============\n\n");
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switch (nb->device_id) {
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case PCI_DEVICE_ID_INTEL_82915:
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case PCI_DEVICE_ID_INTEL_82945GM:
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case PCI_DEVICE_ID_INTEL_82945GSE:
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case PCI_DEVICE_ID_INTEL_82945P:
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case PCI_DEVICE_ID_INTEL_82975X:
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mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
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break;
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case PCI_DEVICE_ID_INTEL_PM965:
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case PCI_DEVICE_ID_INTEL_82Q35:
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case PCI_DEVICE_ID_INTEL_82G33:
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case PCI_DEVICE_ID_INTEL_82Q33:
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mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_Q965:
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case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
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case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
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mchbar_phys = pci_read_long(nb, 0x48);
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/* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads.
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* If it isn't, try to set it. This may fail, because there is
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* some bit that locks that bit, and isn't in the public
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* datasheets.
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*/
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if(!(mchbar_phys & 1))
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{
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printf("Access to the MCHBAR is currently disabled, "\
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"attempting to enable.\n");
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mchbar_phys |= 0x1;
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pci_write_long(nb, 0x48, mchbar_phys);
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if(pci_read_long(nb, 0x48) & 1)
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printf("Enabled successfully.\n");
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else
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printf("Enable FAILED!\n");
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}
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mchbar_phys &= 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_82443LX:
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case PCI_DEVICE_ID_INTEL_82443BX:
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case PCI_DEVICE_ID_INTEL_82810:
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case PCI_DEVICE_ID_INTEL_82810E_MC:
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case PCI_DEVICE_ID_INTEL_82810DC:
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case PCI_DEVICE_ID_INTEL_82830M:
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printf("This northbrigde does not have MCHBAR.\n");
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return 1;
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case PCI_DEVICE_ID_INTEL_GS45:
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mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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default:
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printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n");
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return 1;
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}
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mchbar = map_physical(mchbar_phys, size);
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if (mchbar == NULL) {
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perror("Error mapping MCHBAR");
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exit(1);
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}
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printf("MCHBAR = 0x%08llx (MEM)\n\n", mchbar_phys);
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for (i = 0; i < size; i += 4) {
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if (*(uint32_t *)(mchbar + i))
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printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i));
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}
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unmap_physical((void *)mchbar, size);
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return 0;
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}
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