b39bc2510e
Change-Id: Id12ec4d5f11f4285a1379cf32a5d0f6cd2ce9e70 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38519 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
115 lines
5.1 KiB
Markdown
115 lines
5.1 KiB
Markdown
# PNP devices
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Typical PNP devices are Super I/Os, LPC-connected TPMs and board
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management controllers.
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PNP devices are usually connected to the LPC or eSPI bus of a system
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and shouldn't be confused with PCI(e) devices that use a completely
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different plug and play mechanism. PNP originates in the ISA plug and
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play specification. Since the original ISA bus is more or less extinct,
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the auto-detection part of ISA PNP is mostly irrelevant nowadays. For
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the register offsets for different functionality, appendix A of that
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specification is still the main reference though.
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## Configuration access and config mode
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Super I/O chips connected via LPC to the southbridge usually have their
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I/O-mapped configuration interface with a size of two bytes at the base
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address `0x2e` or `0x4e`. Other PNP devices have their configuration
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interface at other addresses.
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The two byte registers allow access to an indirect 256 bytes big
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register space that contains the configuration. By writing the index to
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the lower byte (e.g. `0x2e`), you can access the register contents at
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that index by reading/writing the higher byte (e.g. `0x2f`).
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To prevent accidental changes of the Super I/O (SIO) configuration,
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the SIOs need a configuration mode unlock sequence. After changing the
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configuration, the configuration mode should be left again, by sending
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the configuration mode lock sequence.
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## Logical device numbers (LDN)
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Each PNP device can contain multiple logical devices. The bytes from
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`0x00` to `0x2f` in the indirect configuration register space are common
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for all LDNs, but some SIO chips require a certain LDN to be selected in
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order to write certain registers in there. An LDN gets selected by
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writing the LDN number to the LDN select register `0x07`. Registers
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`0x30` to `0xff` are specific to each LDN number.
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coreboot encodes the physical LDN number in the lower byte of the LDN
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number.
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### Virtual logical device numbers
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Register `0x30` is the LDN enable register and since it is an 8 bit
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register, it can contain up to 8 enable bits for different parts of
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the functionality of that logical device. To set a certain enable bit
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in one physical LDN, the concept of virtual LDNs was introduced.
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Virtual LDNs share the registers of their base LDN, but allow to
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specify which part of a LDN should be enabled.
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coreboot encodes the enable bit number and by that the virtual LDN
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part in the lower 3 bits of the higher byte of the LDN number.
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## I/O resources
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Starting at register address `0x60`, each LDN has 2 byte wide I/O base
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address registers. The size of an I/O resource is always a power of
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two.
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### I/O resource masks
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The I/O resource masks encode both the size and the maximum base
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address of the corresponding IO resource. The number of zeros counted
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from the least significant bit encode the resource size. If N is the
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number of LSBs being zero, which can also be zero if the LSB is a one,
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the resource has N address bits and a size of 2\*\*N bytes. The mask
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address is also the highest possible address to map the I/O region.
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A typical example for an I/O resource mask is `0x07f8` which is
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`0b0000011111111000` in binary notation. The three LSBs are zeros here,
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so it's an eight byte I/O resource with three address offset bits
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inside the resource. The highest base address it can be mapped to is
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`0x07f8`, so the region will end at `0x07ff`.
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The Super I/O datasheets typically contain the information about the
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I/O resource masks. On most Super I/O chips the mask can also be found
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out by writing `0xffff` to the corresponding I/O base address register
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and reading back the value; since the lowest and highest bits are
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hard-wired to zero according to the I/O resource size and maximal
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possible I/O address, this gives the mask.
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## IRQ resources
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Each physical LDN has up to two configurable interrupt request register
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pairs `0x70`, `0x71` and `0x72`, `0x73`. Each pair can be configured to
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use a certain IRQ number. Writing 1 to 15 into the first register
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selects the IRQ number generated by the corresponding IRQ source and
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enables IRQ generation; writing 0 to it disables the generation of IRQs
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for the source. The second register selects the IRQ type (level or edge)
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and IRQ level (high or low). For LPC SIOs the IRQ type is hard-wired to
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edge.
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On the LPC bus a shared SERIRQ line is used to signal IRQs to the
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host; the IRQ number gets encoded by the number of LPC clock cycles
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after the start frame before the device pulls the open drain
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connection low.
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SERIRQ can be used in two different modes: In the continuous SERIRQ
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mode the host continuously sends IRQ frame starts and the devices
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signal their IRQ request by pulling low the SERIRQ line at the right
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time. In quiet SERIRQ mode the host doesn't send IRQ frame starts, so
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the devices have to send both the IRQ frame start and the encoded IRQ
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number. The quiet mode is often broken.
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## DRQ resources
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Each physical LDN has two legacy ISA-style DMA request channel
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registers at `0x74` and `0x75`. Those are only used for legacy devices
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like parallel printer ports or floppy disk controllers.
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Each device using LPC legacy DMA needs its own LDMA line to the host.
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Some newer chipsets have dropped the LDMA line and with that the
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legacy DMA capability on LPC.
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