wpsw_boot is deprecated in favour of wpsw_cur. As such, coreboot no longer needs to share "write protect" GPIO with depthcharge. BUG=b:124141368, chromium:950273 TEST=make clean && make test-abuild BRANCH=none Change-Id: I2fcb7f82aa063fd72928171af5cbef0356ba620c Signed-off-by: Joel Kitching <kitching@google.com> Cq-Depend: chromium:2088434 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39318 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
53 lines
1.5 KiB
C
53 lines
1.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <boot/coreboot_tables.h>
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#include <ec/google/chromeec/ec.h>
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#include <ec/google/chromeec/ec_commands.h>
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#include <soc/cpu.h>
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#include <soc/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <bootmode.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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/* Lid: active high (LID_GPIO) */
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{EXYNOS5_GPX3, ACTIVE_HIGH, gpio_get_value(GPIO_X35), "lid"},
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/* Power: virtual GPIO active low (POWER_GPIO) */
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{EXYNOS5_GPX1, ACTIVE_LOW, gpio_get_value(GPIO_X13), "power"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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int get_recovery_mode_switch(void)
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{
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uint64_t ec_events;
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/* The GPIO is active low. */
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if (!gpio_get_value(GPIO_Y10)) // RECMODE_GPIO
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return 1;
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ec_events = google_chromeec_get_events_b();
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return !!(ec_events &
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
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}
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int get_write_protect_state(void)
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{
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return !gpio_get_value(GPIO_D16);
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}
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