system76-coreboot

Files

Ionela Voinescu 823f6072a7 pistachio: Remove 50% DDR bandwidth restriction

The existing DDR setup configures the burst length to be 8. However
the DDR controller can only be given sufficient data per clock to
satisfy a burst length of 4, hence the bursts are only half
populated. This results in a 50% drop of efficiency.

Fix this by configuring the burst size to 4.

BUG=chrome-os-partner:31438, chrome-os-partner:37087
TEST=tested on Pistachio bring up board -> DDR initialized
     properly and ramstage executed correctly
BRANCH=none

Change-Id: I761ba73a04688841ca39a370b7cb99b6e0b22964
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0e590ab8387dbbccef45dc84d1eeafee2abc9e2e
Original-Change-Id: I585385b65e330624ad70292349e50c6695eeeb6c
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/256305
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9847
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

2015-04-21 08:26:34 +02:00

broadcom

arm(64): Globally replace writel(v, a) with write32(a, v)

2015-04-21 08:22:28 +02:00

imgtec

pistachio: Remove 50% DDR bandwidth restriction

2015-04-21 08:26:34 +02:00

intel

broadwell: Clear USB3.0 PORTSC status bits in sleep_prepare.

2015-04-21 08:09:30 +02:00

marvell

chromeos: Move memlayout.h/symbols.h into common directory